From patchwork Thu Mar 17 22:30:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 552734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F32CEC43219 for ; Thu, 17 Mar 2022 22:31:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229853AbiCQWcX (ORCPT ); Thu, 17 Mar 2022 18:32:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229820AbiCQWcU (ORCPT ); Thu, 17 Mar 2022 18:32:20 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 539F6180068 for ; Thu, 17 Mar 2022 15:31:01 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 01FFB2C0AE0; Thu, 17 Mar 2022 22:31:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1647556260; bh=CB9o5+iAQCH3vvVKMRvsbRs7DvyhBXWTzdG/VJgZrQI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DqMZa1NQkjW9x3ndN2WpCPdlTImxyUrB9k3h48QYxcxCGFZn+aecnwp3E5nscaCNd lVfsmi4gpFaSzCMh+uCAXHjVOYC5gnX+treV3T3VXHP9TCHk7/9CxeZV9i3BPzZvA6 FHM4cjbwjWRpepb7/MJDREWnZoNwLEeCAiE1K304t2LcVKNFdXhtVdlhN/nS1P7IBT G5oUhFlTzfMoehjSten+SuSe9/Vaeidxavoeo8GV4s4hamB1tU0UvpQ1gENhBwHxk6 18c4wVqqO2o4oxeqmCbft5QqJo6nhMzgGJOGC65RrncYMV8WIieFD+9Ia4VoXB9f3x 1py/vFxz58Mcg== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Fri, 18 Mar 2022 11:30:59 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id A23B213EE37; Fri, 18 Mar 2022 11:30:59 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id A1E892A004D; Fri, 18 Mar 2022 11:30:56 +1300 (NZDT) From: Chris Packham To: jdelvare@suse.com, linux@roeck-us.net, robh+dt@kernel.org Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v2 1/3] dt-bindings: hwmon: Document adt7475 pin-function properties Date: Fri, 18 Mar 2022 11:30:48 +1300 Message-Id: <20220317223051.1227110-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220317223051.1227110-1-chris.packham@alliedtelesis.co.nz> References: <20220317223051.1227110-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=VwQbUJbxAAAA:8 a=XrEdriJqPTbsqx2b3kgA:9 a=AjGcO6oz07-iQ99wixmX:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The adt7473, adt7475, adt7476 and adt7490 have pins that can be used for different functions. Add bindings so that it is possible to describe what pin functions are intended by the hardware design. Signed-off-by: Chris Packham Reviewed-by: Krzysztof Kozlowski --- Notes: Changes in v2: - Add review from Krzysztof .../devicetree/bindings/hwmon/adt7475.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/hwmon/adt7475.yaml b/Documentation/devicetree/bindings/hwmon/adt7475.yaml index 7d9c083632b9..22beb37f1bf1 100644 --- a/Documentation/devicetree/bindings/hwmon/adt7475.yaml +++ b/Documentation/devicetree/bindings/hwmon/adt7475.yaml @@ -61,6 +61,26 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] + "adi,pin(5|10)-function": + description: | + Configures the function for pin 5 on the adi,adt7473 and adi,adt7475. Or + pin 10 on the adi,adt7476 and adi,adt7490. + $ref: /schemas/types.yaml#/definitions/string + enum: + - pwm2 + - smbalert# + + "adi,pin(9|14)-function": + description: | + Configures the function for pin 9 on the adi,adt7473 and adi,adt7475. Or + pin 14 on the adi,adt7476 and adi,adt7490 + $ref: /schemas/types.yaml#/definitions/string + enum: + - tach4 + - therm# + - smbalert# + - gpio + required: - compatible - reg @@ -79,6 +99,8 @@ examples: adi,bypass-attenuator-in0 = <1>; adi,bypass-attenuator-in1 = <0>; adi,pwm-active-state = <1 0 1>; + adi,pin10-function = "smbalert#"; + adi,pin14-function = "tach4"; }; }; From patchwork Thu Mar 17 22:30:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 552303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3956FC43217 for ; Thu, 17 Mar 2022 22:31:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229845AbiCQWcW (ORCPT ); Thu, 17 Mar 2022 18:32:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229816AbiCQWcT (ORCPT ); Thu, 17 Mar 2022 18:32:19 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51DC8180065 for ; Thu, 17 Mar 2022 15:31:01 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id E59D62C0851; Thu, 17 Mar 2022 22:30:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1647556259; bh=xoqzMpiZ/zfpU5hHFDSo09vL8SqsDvZiM5uWIRZaC5Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RcD/h0d6r7KgnBuh8bM/D5E60OsIk6jSt7L6DmSHkFGfjVR8t8Kj60W/3WJPfofOQ 2/2XGaO9GCGjDQVXlXYqZVzAyoqp8SHRA8ytkdOsNH9HUs7BU6Ka8fGGzjNjuGtCOw Esva2fcN+04LdejMYp8m7lkGdVTuBg0tQypc+bwp9DCOvytNqQTg60DVF3SNU52Zf6 uhPTEwz862j05fbhxXAeweiPPCD0EGjPAAwLjxPy8nNdJy8kzIA+yh+3qJdTE/1k2q rGMCit0Mjz2Q7mYtduvEa2PZsPgQosgWT46Q8yKzNMSeKr9dB/SKLDxYBU0nQyAbdt NAy4xw4Zvgk+Q== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Fri, 18 Mar 2022 11:30:59 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id A462613EE43; Fri, 18 Mar 2022 11:30:59 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id A5D9D2A004D; Fri, 18 Mar 2022 11:30:56 +1300 (NZDT) From: Chris Packham To: jdelvare@suse.com, linux@roeck-us.net, robh+dt@kernel.org Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v2 2/3] hwmon: (adt7475) Add support for pin configuration Date: Fri, 18 Mar 2022 11:30:49 +1300 Message-Id: <20220317223051.1227110-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220317223051.1227110-1-chris.packham@alliedtelesis.co.nz> References: <20220317223051.1227110-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=cFeUy8Ca9zMUrnV-lPcA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The adt7473, adt7475, adt7476 and adt7490 have pins that can be used for different functions. On the adt7473 and adt7475 this is pins 5 and 9. On the adt7476 and adt7490 this is pins 10 and 14. The first pin can either be PWM2(default) or SMBALERT#. The second pin can be TACH4(default), THERM#, SMBALERT# or GPIO. The adt7475 driver has always been able to detect the configuration if it had been done by an earlier boot stage. Add support for configuring the pins based on the hardware description in the device tree. Signed-off-by: Chris Packham --- Notes: Changes in v2: - Use load_config{3,4} instead of load_pin{10,14}_config - Handle errors from adt7475_read() - Remove obsolete check on chip type - Use enum chips instead of int - Update error messages drivers/hwmon/adt7475.c | 96 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/drivers/hwmon/adt7475.c b/drivers/hwmon/adt7475.c index 9d5b019651f2..6de501de41b2 100644 --- a/drivers/hwmon/adt7475.c +++ b/drivers/hwmon/adt7475.c @@ -112,6 +112,8 @@ #define CONFIG3_THERM 0x02 #define CONFIG4_PINFUNC 0x03 +#define CONFIG4_THERM 0x01 +#define CONFIG4_SMBALERT 0x02 #define CONFIG4_MAXDUTY 0x08 #define CONFIG4_ATTN_IN10 0x30 #define CONFIG4_ATTN_IN43 0xC0 @@ -1460,6 +1462,96 @@ static int adt7475_update_limits(struct i2c_client *client) return 0; } +static int load_config3(const struct i2c_client *client, const char *propname) +{ + const char *function; + u8 config3; + int ret; + + ret = of_property_read_string(client->dev.of_node, propname, &function); + if (!ret) { + ret = adt7475_read(REG_CONFIG3); + if (ret < 0) + return ret; + + config3 = ret & ~CONFIG3_SMBALERT; + if (!strcmp("pwm2", function)) + ; + else if (!strcmp("smbalert#", function)) + config3 |= CONFIG3_SMBALERT; + else + return -EINVAL; + + return i2c_smbus_write_byte_data(client, REG_CONFIG3, config3); + } + + return 0; +} + +static int load_config4(const struct i2c_client *client, const char *propname) +{ + const char *function; + u8 config4; + int ret; + + ret = of_property_read_string(client->dev.of_node, propname, &function); + if (!ret) { + ret = adt7475_read(REG_CONFIG4); + if (ret < 0) + return ret; + + config4 = ret & ~CONFIG4_PINFUNC; + + if (!strcmp("tach4", function)) + ; + else if (!strcmp("therm#", function)) + config4 |= CONFIG4_THERM; + else if (!strcmp("smbalert#", function)) + config4 |= CONFIG4_SMBALERT; + else if (!strcmp("gpio", function)) + config4 |= CONFIG4_PINFUNC; + else + return -EINVAL; + + return i2c_smbus_write_byte_data(client, REG_CONFIG4, config4); + } + + return 0; +} + +static int load_config(const struct i2c_client *client, enum chips chip) +{ + int err; + const char *prop1, *prop2; + + switch (chip) { + case adt7473: + case adt7475: + prop1 = "adi,pin5-function"; + prop2 = "adi,pin9-function"; + break; + case adt7476: + case adt7490: + prop1 = "adi,pin10-function"; + prop2 = "adi,pin14-function"; + break; + } + + err = load_config3(client, prop1); + if (err) { + dev_err(&client->dev, "failed to configure %s\n", prop1); + return err; + } + + err = load_config4(client, prop2); + if (err) { + dev_err(&client->dev, "failed to configure %s\n", prop2); + return err; + } + + return 0; +} + static int set_property_bit(const struct i2c_client *client, char *property, u8 *config, u8 bit_index) { @@ -1585,6 +1677,10 @@ static int adt7475_probe(struct i2c_client *client) revision = adt7475_read(REG_DEVID2) & 0x07; } + ret = load_config(client, chip); + if (ret) + return ret; + config3 = adt7475_read(REG_CONFIG3); /* Pin PWM2 may alternatively be used for ALERT output */ if (!(config3 & CONFIG3_SMBALERT)) From patchwork Thu Mar 17 22:30:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 552302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AA8DC4321E for ; Thu, 17 Mar 2022 22:31:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229820AbiCQWcY (ORCPT ); Thu, 17 Mar 2022 18:32:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229835AbiCQWcV (ORCPT ); Thu, 17 Mar 2022 18:32:21 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93F14180078 for ; Thu, 17 Mar 2022 15:31:01 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 0FB442C0C23; Thu, 17 Mar 2022 22:31:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1647556260; bh=5yzcYUXA1wnj+z0MDGmniYGpzv7rc9CIlYccVyLXRjE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bl2yLBAlym2GIxAbqdK9FeXyK0q7GXittuf5QdUPpLQ/qOq9rdV9au0y/vaaQGrGL oKy1rOUlWBDgTqJA8/rTYi7oLWH0N1iddQhHBcDsTuLeinNYeYK+zSEazkQKVmbkz2 nbitzFPdylzq1d0hn23FlZeDSBylLasZ9HLtEgdwpPbSm/q1N/jPAkoMU5B5zcYbkg ePm6LXfSuXCmIPrCVOoEkgiTAq2KvfmvE/LN2+t+r3p5mB7ZcMsbt/k5SQsqw0yy7L o5fpkZ9zP2ZYbAU2TKgKVReBYS5RoPscaAe+rc9vRtTBqLNlrWnyyJc8qlIvYD6cUN 33VDvC3RFKmOw== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Fri, 18 Mar 2022 11:30:59 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id A769E13EE8E; Fri, 18 Mar 2022 11:30:59 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id A8E0A2A2679; Fri, 18 Mar 2022 11:30:56 +1300 (NZDT) From: Chris Packham To: jdelvare@suse.com, linux@roeck-us.net, robh+dt@kernel.org Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v2 3/3] hwmon: (adt7475) Use enum chips when loading attenuator settings Date: Fri, 18 Mar 2022 11:30:50 +1300 Message-Id: <20220317223051.1227110-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220317223051.1227110-1-chris.packham@alliedtelesis.co.nz> References: <20220317223051.1227110-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=1utJVCOB_o5uIfT7QvUA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Simplify load_attenuators() by making use of enum chips instead of int. Signed-off-by: Chris Packham --- Notes: Changes in v2: - New drivers/hwmon/adt7475.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwmon/adt7475.c b/drivers/hwmon/adt7475.c index 6de501de41b2..ebe4a85eb62e 100644 --- a/drivers/hwmon/adt7475.c +++ b/drivers/hwmon/adt7475.c @@ -1569,7 +1569,7 @@ static int set_property_bit(const struct i2c_client *client, char *property, return ret; } -static int load_attenuators(const struct i2c_client *client, int chip, +static int load_attenuators(const struct i2c_client *client, enum chips chip, struct adt7475_data *data) { int ret; @@ -1588,7 +1588,7 @@ static int load_attenuators(const struct i2c_client *client, int chip, data->config4); if (ret < 0) return ret; - } else if (chip == adt7473 || chip == adt7475) { + } else { set_property_bit(client, "adi,bypass-attenuator-in1", &data->config2, 5);