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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 01/51] tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCH Date: Wed, 16 Mar 2022 22:04:48 -0700 Message-Id: <20220317050538.924111-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::631 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With TCG_OPF_COND_BRANCH, we extended the lifetimes of globals across extended basic blocks. This means that the liveness computed in pass 1 does not kill globals in the same way as normal temps. Introduce TYPE_EBB to match this lifetime, so that we get correct register allocation for the temps that we introduce during the indirect lowering pass. Fixes: b4cb76e6208 ("tcg: Do not kill globals at conditional branches") Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/tcg/tcg.h | 2 ++ tcg/tcg.c | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 73869fd9d0..27de13fae0 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -433,6 +433,8 @@ typedef enum TCGTempVal { typedef enum TCGTempKind { /* Temp is dead at the end of all basic blocks. */ TEMP_NORMAL, + /* Temp is live across conditional branch, but dead otherwise. */ + TEMP_EBB, /* Temp is saved across basic blocks but dead at the end of TBs. */ TEMP_LOCAL, /* Temp is saved across both basic blocks and translation blocks. */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 33a97eabdb..45030e88fd 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1674,6 +1674,7 @@ static void tcg_reg_alloc_start(TCGContext *s) case TEMP_GLOBAL: break; case TEMP_NORMAL: + case TEMP_EBB: val = TEMP_VAL_DEAD; /* fall through */ case TEMP_LOCAL: @@ -1701,6 +1702,9 @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, case TEMP_LOCAL: snprintf(buf, buf_size, "loc%d", idx - s->nb_globals); break; + case TEMP_EBB: + snprintf(buf, buf_size, "ebb%d", idx - s->nb_globals); + break; case TEMP_NORMAL: snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); break; @@ -2378,6 +2382,7 @@ static void la_bb_end(TCGContext *s, int ng, int nt) state = TS_DEAD | TS_MEM; break; case TEMP_NORMAL: + case TEMP_EBB: case TEMP_CONST: state = TS_DEAD; break; @@ -2427,6 +2432,7 @@ static void la_bb_sync(TCGContext *s, int ng, int nt) case TEMP_NORMAL: s->temps[i].state = TS_DEAD; break; + case TEMP_EBB: case TEMP_CONST: continue; default: @@ -2797,6 +2803,7 @@ static bool liveness_pass_2(TCGContext *s) TCGTemp *dts = tcg_temp_alloc(s); dts->type = its->type; dts->base_type = its->base_type; + dts->kind = TEMP_EBB; its->state_ptr = dts; } else { its->state_ptr = NULL; @@ -3107,6 +3114,7 @@ static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) new_type = TEMP_VAL_MEM; break; case TEMP_NORMAL: + case TEMP_EBB: new_type = free_or_dead < 0 ? TEMP_VAL_MEM : TEMP_VAL_DEAD; break; case TEMP_CONST: @@ -3353,6 +3361,7 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) temp_save(s, ts, allocated_regs); break; case TEMP_NORMAL: + case TEMP_EBB: /* The liveness analysis already ensures that temps are dead. Keep an tcg_debug_assert for safety. */ tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); @@ -3390,6 +3399,7 @@ static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs) case TEMP_NORMAL: tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); break; + case TEMP_EBB: case TEMP_CONST: break; default: From patchwork Thu Mar 17 05:04:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552208 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp874914mag; Wed, 16 Mar 2022 22:11:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyNbTTr2Oi/jl8UrvfyoqhClrQIXokHh32GEi2VcEcx7B2IdfdVdI3vVTZrK2rXpjAJyYSg X-Received: by 2002:a05:6214:2487:b0:435:92e5:7f with SMTP id gi7-20020a056214248700b0043592e5007fmr2298364qvb.76.1647493910720; Wed, 16 Mar 2022 22:11:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647493910; cv=none; d=google.com; s=arc-20160816; b=o+IKrs0UqHPWEYnT7shXu8v1Pfj/0eHqQ7jsxwNTGcjAnrqtsemRKY7eLlI96xfJYb +Wysb98z1oGUPXeFYZt//1GheiwsENlwIZqWUebcdQWubJvno6N0hgdTL2rBMEJ1HwNg oHI+XgkiBR/HppfwliMamXcUOjlJhYNzRzbZHkZoLmUnvcP7t4GLsz8VA56C5vwl48UN myimkY82BBdAKsJjWvxiia55zeVs8igUKVQj+PU7LWuB2li2WgXTsM27WcGetNKsn7wI N6ytfEE9qjjbSncDSryoKH10+rruUoJ8tpdI8W3/j/kxfEYJ+JBWUN3MlOH4PE+nzWm4 ALFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NA9HskFqPeLh+02a0cXnYrdAXovGtw+F2Po8AxVhC7E=; b=YEVH85OA5FmUCX7rzNZqzXfEhDZG9zAq4/fgUJ4zuPJzA1qTFIiEs1L1nfMhkXPc2S 6pmB998Slp8YFXBmeOMvgx7EcARSSOnX9YgEecR81CZowB3QDkVvv3o/38SzH/go/h5v qkTv7Weop7sWnvsSreZtc3pld2ynQ4mtLg15XV6v6tEjCdHyaMUEIcHScoD5Hs7Lt1SG k3MGbX3ZdUaBesKwzUDpvj15HK6HTfisni1cy7jwF2WL2SHFsxLr4IyDpxmtZTg0ZSPo ax6NpROt1Bbr822qfL98IyxeForiK7b7LR51GPJGc3/2/d0u0plDUgCYHe2qoIbKMwHV +Wxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jQKBj7M1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 02/51] target/nios2: Check supervisor on eret Date: Wed, 16 Mar 2022 22:04:49 -0700 Message-Id: <20220317050538.924111-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1036 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Amir Gonnen eret instruction is only allowed in supervisor mode. Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-2-amir.gonnen@neuroblade.ai> Signed-off-by: Richard Henderson --- target/nios2/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index f89271dbed..341f3a8273 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -384,6 +384,8 @@ static const Nios2Instruction i_type_instructions[] = { */ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) { + gen_check_supervisor(dc); + tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]); From patchwork Thu Mar 17 05:04:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552212 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp876178mag; Wed, 16 Mar 2022 22:14:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwMV1IEi4GRbcY/rdA6cVZPg/i6jsBQ1MKLInet6qQEuUA9n5mtD2FfXZ+5EPCruO5SPNV6 X-Received: by 2002:a05:620a:1925:b0:67d:93f9:3c0 with SMTP id bj37-20020a05620a192500b0067d93f903c0mr1851278qkb.256.1647494075164; Wed, 16 Mar 2022 22:14:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647494075; cv=none; d=google.com; s=arc-20160816; b=KvSRKrGkuPfxeqrJ5iEt5BJwcq8TXTxcVhZsViRqwck9u2PZtEZdlIeLovN6nUgKhP 4taozQIqsOOCWRfZ5dhmnCGGVyvIRAsgsKfKm6X/gCSv+/ux3JSpDgt7kTaQ+0ofPQSG xtFyjxIbrEYP4L9pw3FFkGTfVdZ5i/ybn/rKiOvxF+4VG/z9fOclCvim2ViDOUmEXBxj 4yDnF2j6iKvgEm6CVHF46s+aVerMegUO4zB93B3BaJtjMv5Gfv08U5QdhvIL/QXZO4wh lceXExGO3lX4eY506tVk1itpU6iMWIV6tdGJQ7g8a7zPR/JB1QXQ0o2v6EDpUxnQeaMK HUhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bz8zlZqp+XNpUuV3WS3uKIWPzFVnLucU6nOyII1L55M=; b=m5wf4JrFt/XSkzdDzBx03codPY8QXK9yyU+exmH1ssan5sgTp0+GUkBoXbAs5/zw5h 3HDqr+JJSRGlaPzKRGfkghVTGP9ZN7auHeMjv/HbdbPGef3KH8rtfCTJGMLpNf7DCKsS jbS1/B2BnKyAqXXa+oXfWmAezTfafGxj0q6LjndlVe/9QzNosdSDBYFu2MRNnJXVF9yR kh2CQvqXuXQSV9JqKkUyvXbPCaUye2umeRRkqGW6wJtxBOE1k29VN/Bh8irTl1KFFxwL 75LBOsFZHX3V4Jmi7pnZgRaPPps/IrT+Ja/qm7nTbFbrHQNzl0GQjn2uwj3ynO3X8I1z 4Jsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BHf8zlCw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 03/51] target/nios2: Stop generating code if gen_check_supervisor fails Date: Wed, 16 Mar 2022 22:04:50 -0700 Message-Id: <20220317050538.924111-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::629 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Whether the cpu is in user-mode or not is something that we know at translation-time. We do not need to generate code after having raised an exception. Suggested-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/translate.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 341f3a8273..1e0ab686dc 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -169,12 +169,14 @@ static void gen_excp(DisasContext *dc, uint32_t code, uint32_t flags) t_gen_helper_raise_exception(dc, flags); } -static void gen_check_supervisor(DisasContext *dc) +static bool gen_check_supervisor(DisasContext *dc) { if (dc->base.tb->flags & CR_STATUS_U) { /* CPU in user mode, privileged instruction called, stop. */ t_gen_helper_raise_exception(dc, EXCP_SUPERI); + return false; } + return true; } /* @@ -384,7 +386,9 @@ static const Nios2Instruction i_type_instructions[] = { */ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) { - gen_check_supervisor(dc); + if (!gen_check_supervisor(dc)) { + return; + } tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]); @@ -447,7 +451,9 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - gen_check_supervisor(dc); + if (!gen_check_supervisor(dc)) { + return; + } if (unlikely(instr.c == R_ZERO)) { return; @@ -474,9 +480,13 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) /* ctlN <- rA */ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) { - gen_check_supervisor(dc); + if (!gen_check_supervisor(dc)) { + return; + } -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else R_TYPE(instr, code); TCGv v = load_gpr(dc, instr.a); From patchwork Thu Mar 17 05:04:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552206 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp872980mag; Wed, 16 Mar 2022 22:07:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwuDU6+kU3chlTt4Om4vpYi8HbUgoQOYYiJDFr+M81a3IuWkpOR18I9NUA9ECuS/q+7YLZm X-Received: by 2002:a05:6214:f61:b0:435:92db:2f8b with SMTP id iy1-20020a0562140f6100b0043592db2f8bmr2058528qvb.121.1647493652502; Wed, 16 Mar 2022 22:07:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647493652; cv=none; d=google.com; s=arc-20160816; b=Yf6AJSzlRttNOEnCiqZN6VbctLTsS2V92eG+JNBwHpNFZR1bcWUchJJDkb/gkvEe0m 3S8Y5JbqZjtxy15Xmi/j3ckn4iblwm8ufXTYfAKSWZQmJUiB6XZUNVSAg7DXraceKK0Y HL/YDGQC1XgAV5HCop4bPQZDLtRdXCTnMlq7UZpQaGGA2cInnIQ7kXKO6yRfljLJFAOW kSHxOl8NJpRi9s7xPlsSxlySyR/B9f1//eGCaF8k3mZKTzHyVhPeq8PJDxGL8Lbi7iKd cNnGGf4yXQhLuNrEnop2/9z9H8aIGgIaZsdk8In8Zhau7UHnovBri3xk56AF8CdZOmJW 8T5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tamfos1uvfrgy6OTL/hYTKA67kxVDj5ysduH3BCBsBo=; b=t4UD1pjGz/zfKR5capbKBnABreIYUtU6YcRDhm1y2wdgM43pgJNz9uz4v5M6l59Ivt 7ghTN/UqapXbaf+rQxhtF/82P7DqWCc1LYlusJm1Ayviav7FgdGN/Tic/aGDIK8khPYW CPz5BHr8SrO3zCOiznYw4F1IMJzdfMe5saZTXlWd1CkFl2J/VVn6SUnF7HvyQJujez+E Ft8skeXsQDF6IaHcYUGSFjSpdgz9akciWaAEs9SLH1+xZx5rAQMXrFAxKjV29stOfjNQ AiSC5eWxdJcCdl/XvFOxiAR/p4gbAhi4uSg9pctp5Oc36Sg2jDUWcFnvV8uKN8s0tS+l SnOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QAHbwSdI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 04/51] target/nios2: Add NUM_GP_REGS and NUM_CP_REGS Date: Wed, 16 Mar 2022 22:04:51 -0700 Message-Id: <20220317050538.924111-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Amir Gonnen Split NUM_CORE_REGS into components that can be used elsewhere. Reviewed-by: Peter Maydell Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-3-amir.gonnen@neuroblade.ai> [rth: Split out of a larger patch for shadow register sets.] Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index ca0f3420cd..adeb16377d 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -56,9 +56,11 @@ struct Nios2CPUClass { #define EXCEPTION_ADDRESS 0x00000004 #define FAST_TLB_MISS_ADDRESS 0x00000008 +#define NUM_GP_REGS 32 +#define NUM_CR_REGS 32 /* GP regs + CR regs + PC */ -#define NUM_CORE_REGS (32 + 32 + 1) +#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1) /* General purpose register aliases */ #define R_ZERO 0 @@ -79,7 +81,7 @@ struct Nios2CPUClass { #define R_RA 31 /* Control register aliases */ -#define CR_BASE 32 +#define CR_BASE NUM_GP_REGS #define CR_STATUS (CR_BASE + 0) #define CR_STATUS_PIE (1 << 0) #define CR_STATUS_U (1 << 1) From patchwork Thu Mar 17 05:04:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552220 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp878586mag; Wed, 16 Mar 2022 22:20:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzDWGJzXVoKnFyCSTxI1OfJtuee+OhYxxHR7xF93/E1x0aw+M0FKs7O9QipyHV6RfWCO+7B X-Received: by 2002:a05:620a:2909:b0:67b:32f1:d17f with SMTP id m9-20020a05620a290900b0067b32f1d17fmr1819622qkp.489.1647494404882; Wed, 16 Mar 2022 22:20:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647494404; cv=none; d=google.com; s=arc-20160816; b=KCyE0egteKIWQ0oa7hX2poK0uSG3oQq+7RlRopC27lRLHzS0M6qpe78HPG9fA3SWyY 46IPi2ULiAR3bk9fD/MrGwHFRQ6Qr1s4qsigBHtZiDJ1d5uP1NjbQkjR8Qh2X8DbWcer 02eIsuvwDSp9YY6pP5rbUrH73J94l417KOz8jIoSsehQSHd/8kr2LUoJMKUK8GbCyPfk wwQ9fslNXyYujgOzmXl3sEPjFsc6o5BT0li/5onv99H/DamY1oiJNA+Ol53fzGrPo+uc WUXmztMKHV0SPkevdwmkH+Uu8U79g9S8U7ZWb3Offx3EFDBSkKLM8j+5ENhQb/cQh16e qNFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bkOrHFoETWid+QekyrDcDE4JYVn7YyGDinnjYK+GH7Y=; b=XfkQwNUt+ikAte0GvYELRylQrjjvf7MDYlzQpBgKdT2QQVkfFZ8681NULfxUsAq+SG rrFeVCWG2HZkTOnriXR4c9uqAOo1UmR684LqjfLrrjJd7FkhB7E5O18wJNfnWrXqSDSL j9WONH9n7MNMUkKwDb/RzPiay5/4AJj/2WaxLg5/3mwRplX8V45AdvOCR6io1KXMD4rL gZvsGGiBR4VPyxdysWN86GrPsWXzavQzqhib/sdASCwjbzp/agGDOBDLgwsuwZ0g9pXg 9Mfo4hdWFl5DiregWN/BkYQF1c+dBGogPaXRFxY6B2pnROZgpNqfXMdhVQ3T5Jm6MwZk VZrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lcjLPhW7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 05/51] target/nios2: Split PC out of env->regs[] Date: Wed, 16 Mar 2022 22:04:52 -0700 Message-Id: <20220317050538.924111-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::630 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It is cleaner to have a separate name for this variable. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 10 +++----- linux-user/elfload.c | 2 +- linux-user/nios2/cpu_loop.c | 17 ++++++------- linux-user/nios2/signal.c | 6 ++--- target/nios2/cpu.c | 8 +++--- target/nios2/helper.c | 51 +++++++++++++++++-------------------- target/nios2/translate.c | 29 +++++++++++---------- 7 files changed, 58 insertions(+), 65 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index adeb16377d..9be128d63a 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -59,8 +59,8 @@ struct Nios2CPUClass { #define NUM_GP_REGS 32 #define NUM_CR_REGS 32 -/* GP regs + CR regs + PC */ -#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1) +/* GP regs + CR regs */ +#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS) /* General purpose register aliases */ #define R_ZERO 0 @@ -130,9 +130,6 @@ struct Nios2CPUClass { #define CR_MPUBASE (CR_BASE + 14) #define CR_MPUACC (CR_BASE + 15) -/* Other registers */ -#define R_PC 64 - /* Exceptions */ #define EXCP_BREAK 0x1000 #define EXCP_RESET 0 @@ -158,6 +155,7 @@ struct Nios2CPUClass { struct CPUArchState { uint32_t regs[NUM_CORE_REGS]; + uint32_t pc; #if !defined(CONFIG_USER_ONLY) Nios2MMU mmu; @@ -241,7 +239,7 @@ typedef Nios2CPU ArchCPU; static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { - *pc = env->regs[R_PC]; + *pc = env->pc; *cs_base = 0; *flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U)); } diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 9628a38361..23ff9659a5 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1170,7 +1170,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, (*regs)[30] = -1; /* R_SSTATUS */ (*regs)[31] = tswapreg(env->regs[R_RA]); - (*regs)[32] = tswapreg(env->regs[R_PC]); + (*regs)[32] = tswapreg(env->pc); (*regs)[33] = -1; /* R_STATUS */ (*regs)[34] = tswapreg(env->regs[CR_ESTATUS]); diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 1e93ef34e6..7b20c024db 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -56,25 +56,24 @@ void cpu_loop(CPUNios2State *env) env->regs[2] = abs(ret); /* Return value is 0..4096 */ env->regs[7] = ret > 0xfffff000u; - env->regs[R_PC] += 4; + env->pc += 4; break; case 1: qemu_log_mask(CPU_LOG_INT, "\nTrap 1\n"); - force_sig_fault(TARGET_SIGUSR1, 0, env->regs[R_PC]); + force_sig_fault(TARGET_SIGUSR1, 0, env->pc); break; case 2: qemu_log_mask(CPU_LOG_INT, "\nTrap 2\n"); - force_sig_fault(TARGET_SIGUSR2, 0, env->regs[R_PC]); + force_sig_fault(TARGET_SIGUSR2, 0, env->pc); break; case 31: qemu_log_mask(CPU_LOG_INT, "\nTrap 31\n"); - force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[R_PC]); + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc); break; default: qemu_log_mask(CPU_LOG_INT, "\nTrap %d\n", env->error_code); - force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, - env->regs[R_PC]); + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, env->pc); break; case 16: /* QEMU specific, for __kuser_cmpxchg */ @@ -99,7 +98,7 @@ void cpu_loop(CPUNios2State *env) o = env->regs[5]; n = env->regs[6]; env->regs[2] = qatomic_cmpxchg(h, o, n) - o; - env->regs[R_PC] += 4; + env->pc += 4; } break; } @@ -117,7 +116,7 @@ void cpu_loop(CPUNios2State *env) info.si_errno = 0; /* TODO: check env->error_code */ info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->regs[R_PC]; + info._sifields._sigfault._addr = env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); } break; @@ -155,6 +154,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) env->regs[R_SP] = regs->sp; env->regs[R_GP] = regs->gp; env->regs[CR_ESTATUS] = regs->estatus; - env->regs[R_PC] = regs->ea; + env->pc = regs->ea; /* TODO: unsigned long orig_r7; */ } diff --git a/linux-user/nios2/signal.c b/linux-user/nios2/signal.c index 517cd39270..ccfaa75d3b 100644 --- a/linux-user/nios2/signal.c +++ b/linux-user/nios2/signal.c @@ -73,7 +73,7 @@ static void rt_setup_ucontext(struct target_ucontext *uc, CPUNios2State *env) __put_user(env->regs[R_RA], &gregs[23]); __put_user(env->regs[R_FP], &gregs[24]); __put_user(env->regs[R_GP], &gregs[25]); - __put_user(env->regs[R_PC], &gregs[27]); + __put_user(env->pc, &gregs[27]); __put_user(env->regs[R_SP], &gregs[28]); } @@ -122,7 +122,7 @@ static int rt_restore_ucontext(CPUNios2State *env, struct target_ucontext *uc, __get_user(env->regs[R_GP], &gregs[25]); /* Not really necessary no user settable bits */ __get_user(temp, &gregs[26]); - __get_user(env->regs[R_PC], &gregs[27]); + __get_user(env->pc, &gregs[27]); __get_user(env->regs[R_RA], &gregs[23]); __get_user(env->regs[R_SP], &gregs[28]); @@ -180,7 +180,7 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, env->regs[4] = sig; env->regs[5] = frame_addr + offsetof(struct target_rt_sigframe, info); env->regs[6] = frame_addr + offsetof(struct target_rt_sigframe, uc); - env->regs[R_PC] = ka->_sa_handler; + env->pc = ka->_sa_handler; unlock_user_struct(frame, frame_addr, 1); } diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 6975ae4bdb..40031c9f20 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -31,7 +31,7 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) Nios2CPU *cpu = NIOS2_CPU(cs); CPUNios2State *env = &cpu->env; - env->regs[R_PC] = value; + env->pc = value; } static bool nios2_cpu_has_work(CPUState *cs) @@ -54,7 +54,7 @@ static void nios2_cpu_reset(DeviceState *dev) ncc->parent_reset(dev); memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS); - env->regs[R_PC] = cpu->reset_addr; + env->pc = cpu->reset_addr; #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ @@ -161,7 +161,7 @@ static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) if (n < 32) { /* GP regs */ return gdb_get_reg32(mem_buf, env->regs[n]); } else if (n == 32) { /* PC */ - return gdb_get_reg32(mem_buf, env->regs[R_PC]); + return gdb_get_reg32(mem_buf, env->pc); } else if (n < 49) { /* Status regs */ return gdb_get_reg32(mem_buf, env->regs[n - 1]); } @@ -183,7 +183,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) if (n < 32) { /* GP regs */ env->regs[n] = ldl_p(mem_buf); } else if (n == 32) { /* PC */ - env->regs[R_PC] = ldl_p(mem_buf); + env->pc = ldl_p(mem_buf); } else if (n < 49) { /* Status regs */ env->regs[n - 1] = ldl_p(mem_buf); } diff --git a/target/nios2/helper.c b/target/nios2/helper.c index e5c98650e1..31cec29e89 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -35,7 +35,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) Nios2CPU *cpu = NIOS2_CPU(cs); CPUNios2State *env = &cpu->env; cs->exception_index = -1; - env->regs[R_EA] = env->regs[R_PC] + 4; + env->regs[R_EA] = env->pc + 4; } void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, @@ -58,7 +58,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_IRQ: assert(env->regs[CR_STATUS] & CR_STATUS_PIE); - qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc); env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; env->regs[CR_STATUS] |= CR_STATUS_IH; @@ -67,14 +67,13 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &= ~(0x1F << 2); env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; - env->regs[R_EA] = env->regs[R_PC] + 4; - env->regs[R_PC] = cpu->exception_addr; + env->regs[R_EA] = env->pc + 4; + env->pc = cpu->exception_addr; break; case EXCP_TLBD: if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc); /* Fast TLB miss */ /* Variation from the spec. Table 3-35 of the cpu reference shows @@ -90,11 +89,10 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_TLBMISC] &= ~CR_TLBMISC_DBL; env->regs[CR_TLBMISC] |= CR_TLBMISC_WR; - env->regs[R_EA] = env->regs[R_PC] + 4; - env->regs[R_PC] = cpu->fast_tlb_miss_addr; + env->regs[R_EA] = env->pc + 4; + env->pc = cpu->fast_tlb_miss_addr; } else { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc); /* Double TLB miss */ env->regs[CR_STATUS] |= CR_STATUS_EH; @@ -105,14 +103,14 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_TLBMISC] |= CR_TLBMISC_DBL; - env->regs[R_PC] = cpu->exception_addr; + env->pc = cpu->exception_addr; } break; case EXCP_TLBR: case EXCP_TLBW: case EXCP_TLBX: - qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc); env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; env->regs[CR_STATUS] |= CR_STATUS_EH; @@ -125,19 +123,18 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_TLBMISC] |= CR_TLBMISC_WR; } - env->regs[R_EA] = env->regs[R_PC] + 4; - env->regs[R_PC] = cpu->exception_addr; + env->regs[R_EA] = env->pc + 4; + env->pc = cpu->exception_addr; break; case EXCP_SUPERA: case EXCP_SUPERI: case EXCP_SUPERD: - qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc); if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; - env->regs[R_EA] = env->regs[R_PC] + 4; + env->regs[R_EA] = env->pc + 4; } env->regs[CR_STATUS] |= CR_STATUS_EH; @@ -146,17 +143,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &= ~(0x1F << 2); env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; - env->regs[R_PC] = cpu->exception_addr; + env->pc = cpu->exception_addr; break; case EXCP_ILLEGAL: case EXCP_TRAP: - qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc); if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; - env->regs[R_EA] = env->regs[R_PC] + 4; + env->regs[R_EA] = env->pc + 4; } env->regs[CR_STATUS] |= CR_STATUS_EH; @@ -165,24 +161,23 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &= ~(0x1F << 2); env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; - env->regs[R_PC] = cpu->exception_addr; + env->pc = cpu->exception_addr; break; case EXCP_BREAK: - qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc); /* The semihosting instruction is "break 1". */ if (semihosting_enabled() && - cpu_ldl_code(env, env->regs[R_PC]) == 0x003da07a) { + cpu_ldl_code(env, env->pc) == 0x003da07a) { qemu_log_mask(CPU_LOG_INT, "Entering semihosting\n"); - env->regs[R_PC] += 4; + env->pc += 4; do_nios2_semihosting(env); break; } if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { env->regs[CR_BSTATUS] = env->regs[CR_STATUS]; - env->regs[R_BA] = env->regs[R_PC] + 4; + env->regs[R_BA] = env->pc + 4; } env->regs[CR_STATUS] |= CR_STATUS_EH; @@ -191,7 +186,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &= ~(0x1F << 2); env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; - env->regs[R_PC] = cpu->exception_addr; + env->pc = cpu->exception_addr; break; default: diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 1e0ab686dc..154ffacbea 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -104,6 +104,7 @@ typedef struct DisasContext { } DisasContext; static TCGv cpu_R[NUM_CORE_REGS]; +static TCGv cpu_pc; typedef struct Nios2Instruction { void (*handler)(DisasContext *dc, uint32_t code, uint32_t flags); @@ -144,7 +145,7 @@ static void t_gen_helper_raise_exception(DisasContext *dc, { TCGv_i32 tmp = tcg_const_i32(index); - tcg_gen_movi_tl(cpu_R[R_PC], dc->pc); + tcg_gen_movi_tl(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->base.is_jmp = DISAS_NORETURN; @@ -156,10 +157,10 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest) if (translator_use_goto_tb(&dc->base, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_tl(cpu_R[R_PC], dest); + tcg_gen_movi_tl(cpu_pc, dest); tcg_gen_exit_tb(tb, n); } else { - tcg_gen_movi_tl(cpu_R[R_PC], dest); + tcg_gen_movi_tl(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } } @@ -391,7 +392,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) } tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); - tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]); + tcg_gen_mov_tl(cpu_pc, cpu_R[R_EA]); dc->base.is_jmp = DISAS_JUMP; } @@ -399,7 +400,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) /* PC <- ra */ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_RA]); + tcg_gen_mov_tl(cpu_pc, cpu_R[R_RA]); dc->base.is_jmp = DISAS_JUMP; } @@ -407,7 +408,7 @@ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) /* PC <- ba */ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_BA]); + tcg_gen_mov_tl(cpu_pc, cpu_R[R_BA]); dc->base.is_jmp = DISAS_JUMP; } @@ -417,7 +418,7 @@ static void jmp(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - tcg_gen_mov_tl(cpu_R[R_PC], load_gpr(dc, instr.a)); + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); dc->base.is_jmp = DISAS_JUMP; } @@ -440,7 +441,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - tcg_gen_mov_tl(cpu_R[R_PC], load_gpr(dc, instr.a)); + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next); dc->base.is_jmp = DISAS_JUMP; @@ -742,7 +743,7 @@ illegal_op: t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); } -static const char * const regnames[] = { +static const char * const regnames[NUM_CORE_REGS] = { "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", @@ -759,7 +760,6 @@ static const char * const regnames[] = { "reserved6", "reserved7", "reserved8", "reserved9", "reserved10", "reserved11", "reserved12", "reserved13", "reserved14", "reserved15", "reserved16", "reserved17", - "rpc" }; #include "exec/gen-icount.h" @@ -827,7 +827,7 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_TOO_MANY: case DISAS_UPDATE: /* Save the current PC back into the CPU register */ - tcg_gen_movi_tl(cpu_R[R_PC], dc->base.pc_next); + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); tcg_gen_exit_tb(NULL, 0); break; @@ -876,8 +876,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) return; } - qemu_fprintf(f, "IN: PC=%x %s\n", - env->regs[R_PC], lookup_symbol(env->regs[R_PC])); + qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); for (i = 0; i < NUM_CORE_REGS; i++) { qemu_fprintf(f, "%9s=%8.8x ", regnames[i], env->regs[i]); @@ -903,10 +902,12 @@ void nios2_tcg_init(void) offsetof(CPUNios2State, regs[i]), regnames[i]); } + cpu_pc = tcg_global_mem_new(cpu_env, + offsetof(CPUNios2State, pc), "pc"); } void restore_state_to_opc(CPUNios2State *env, TranslationBlock *tb, target_ulong *data) { - env->regs[R_PC] = data[0]; + env->pc = data[0]; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 06/51] target/nios2: Split out helper for eret instruction Date: Wed, 16 Mar 2022 22:04:53 -0700 Message-Id: <20220317050538.924111-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::636 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Amir Gonnen The implementation of eret will become much more complex with the introduction of shadow registers. Reviewed-by: Peter Maydell Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-3-amir.gonnen@neuroblade.ai> [rth: Split out of a larger patch for shadow register sets. Directly exit to the cpu loop from the helper.] Signed-off-by: Richard Henderson --- target/nios2/helper.h | 1 + target/nios2/op_helper.c | 9 +++++++++ target/nios2/translate.c | 10 ++++++---- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target/nios2/helper.h b/target/nios2/helper.h index a44ecfdf7a..525b6b685b 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -21,6 +21,7 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) #if !defined(CONFIG_USER_ONLY) +DEF_HELPER_3(eret, noreturn, env, i32, i32) DEF_HELPER_2(mmu_write_tlbacc, void, env, i32) DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32) DEF_HELPER_2(mmu_write_pteaddr, void, env, i32) diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index caa885f7b4..ee5ad8b23f 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -30,3 +30,12 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index) cs->exception_index = index; cpu_loop_exit(cs); } + +#ifndef CONFIG_USER_ONLY +void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) +{ + env->regs[CR_STATUS] = new_status; + env->pc = new_pc; + cpu_loop_exit(env_cpu(env)); +} +#endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 154ffacbea..7c2c430e99 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -391,10 +391,12 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) return; } - tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); - tcg_gen_mov_tl(cpu_pc, cpu_R[R_EA]); - - dc->base.is_jmp = DISAS_JUMP; +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + gen_helper_eret(cpu_env, cpu_R[CR_ESTATUS], cpu_R[R_EA]); + dc->base.is_jmp = DISAS_NORETURN; +#endif } /* PC <- ra */ From patchwork Thu Mar 17 05:04:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552224 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp879951mag; Wed, 16 Mar 2022 22:23:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz4fQXxSfzFF1etMLI6LYtIaQGyGh0/DjpVLbKve/9HkpdxQsMx6S8yAU8ecQu4iBQHrFSK X-Received: by 2002:a05:622a:48e:b0:2e0:706f:1d4 with SMTP id p14-20020a05622a048e00b002e0706f01d4mr2407963qtx.326.1647494592500; Wed, 16 Mar 2022 22:23:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647494592; cv=none; d=google.com; s=arc-20160816; b=uqk4vLx90A3q+vnW6Uvr6CDBzWlwGgH8Dv2DvhYqbAKNOTM41cri/tFZg8mTyb/jWP Qqkk8L29wBVMnlZc/vAAZuQgQlDkdgbtuGHZlkV+xiiHMQ6Q3zlF+NRNirl3IbvYrOnc +ybegyV4o3GOj+IANt/4a8tJoVXeHkCbxIDMYcoafzFR7WBXh4iGP+qgoRBUaEZhzRNP 4sMg/qvgFyxxfCGOT5i9HerhzOVrnDB/GJED5MpEZHBnmALrJXy3y9HuiZmZSQ5C4Sq+ gorOJKx7dGTzi2TWSw/sdyKr7HEl4Tkq6jU6903fslWVBt/aSTR29cbY8mJWqFdSW+RP QeBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=L+hHIFlWfBTWBYr3FWgA0oFT6zz/eF9rCjwaIxiotag=; b=O9zwF6Xy+R+U8dmiiGCWGd+6V6Lejtn0zSGXQkpia+g6qo5Lz2QSioc7AhbzuWIsWb Q7pw1oj8BVbyGuFrVeTNqXokyntLA99zsbtEqan2Hjo5ch6WMukr1hwButofC2y6J2Gc GpM3u1KJwCjj85bH52+UnjZZtiWA+vVJPouLfIcyYE698vITgqKd/fj8Z/w9m+3wk9fH IjzZQ4/RVx4iGgB3uFWpjPehsYUiZd8nNjOBVNfM/t4sETXc0tvRBnn4YnK/2WHQ6vFv 8pqHaGiajKFiM46WaetJFdp8tW7F6JjgfgkmhBSiWEb3mfRppZc3y2cPVWfZp0Ooyymj 2kqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CBkjPBEj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 07/51] target/nios2: Fix BRET instruction Date: Wed, 16 Mar 2022 22:04:54 -0700 Message-Id: <20220317050538.924111-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We had failed to copy BSTATUS back to STATUS, and diagnose supervisor-only. The spec is light on the specifics of the implementation of bret, but it is an easy assumption that the restore into STATUS should work the same as eret. Therefore, reuse the existing helper_eret. Reviewed-by: Peter Maydell Reported-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/translate.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 7c2c430e99..3f7bbd6d7b 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -407,12 +407,22 @@ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) dc->base.is_jmp = DISAS_JUMP; } -/* PC <- ba */ +/* + * status <- bstatus + * PC <- ba + */ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_pc, cpu_R[R_BA]); + if (!gen_check_supervisor(dc)) { + return; + } - dc->base.is_jmp = DISAS_JUMP; +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + gen_helper_eret(cpu_env, cpu_R[CR_BSTATUS], cpu_R[R_BA]); + dc->base.is_jmp = DISAS_NORETURN; +#endif } /* PC <- rA */ From patchwork Thu Mar 17 05:04:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552228 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp881827mag; Wed, 16 Mar 2022 22:27:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJztl3rTZAeicoGyF2SvnqyGYJ1fOh8xTNhmcVyPuFARHZtki8XCQxyCRIl9jlxftXrRec80 X-Received: by 2002:ad4:5c83:0:b0:435:8969:57f8 with SMTP id o3-20020ad45c83000000b00435896957f8mr2183587qvh.50.1647494851584; Wed, 16 Mar 2022 22:27:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647494851; cv=none; d=google.com; s=arc-20160816; b=C+vs6OrfnynEHsXBrl/TVgLUCH5qJhldzWU0FDB7FDO+ex0xAb2MMTD0z2mS0T8n2R Xy8qCZXjDwK/fGQuUV4srPFKqRnkASUcoODtlO0j7sj3tsKv4K8YACwOOiCAyfsozRrR gccMzeTyU8Jm0CHjg5IVt7c3/NwK/A3EBJvI92udjxQff1UDeaKQvSXVexm+CRFZhkKb O17jw3isZaVN20osq6uA2wnCpfBso6H6MmG4ZBjCNyPoBf7ghRdWKgtLgwG9O4B0CEgu bw6owXDHXThOY/w3GHTWH40EUoYmXqKejDB7pSqc2yNcAddc/QDYU67Hlhfm2vBHhnEo BkFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PuQXs01EVc8/4vklrwlVd1dwEAykk2bEYyKpnLalt08=; b=IJGnpSpxBkDgWkIZW23tjiKspDlcqVL0kx3l5fHfIhh2q8gCZbPxx0y8ZmYTycMaDs O2xSogAGFP7hljv5EdlB01KPGIT1Ix3Em5gMXpcmHGu4mQ5ZLX4ML3M1yD528RrbwQ4C Ybl8zE0CUlO7H7X2ReDiHJz/Ub9p6uhBFYo1wsdSeLINxz2akVcdobHMuHYE3GrQxRvc UZGkc+afBssiCPKSqIJjHqxYuxYohNvIDSkG5mRLxhrsv2ox72cuRpb+NjoTnU8viRsw Xq8HZd4z4MWBxgsVxhQEl30qvQVfaemjhC7/J8/HbAJbApv1f1LbDkS8nIaThfrtrSaZ BApg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NlDtwI6a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 08/51] target/nios2: Do not create TCGv for control registers Date: Wed, 16 Mar 2022 22:04:55 -0700 Message-Id: <20220317050538.924111-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We don't need to reference them often, and when we do it is just as easy to load/store from cpu_env directly. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/translate.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 3f7bbd6d7b..e6e9a5ac6f 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -103,7 +103,7 @@ typedef struct DisasContext { int mem_idx; } DisasContext; -static TCGv cpu_R[NUM_CORE_REGS]; +static TCGv cpu_R[NUM_GP_REGS]; static TCGv cpu_pc; typedef struct Nios2Instruction { @@ -394,7 +394,11 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - gen_helper_eret(cpu_env, cpu_R[CR_ESTATUS], cpu_R[R_EA]); + TCGv tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_ESTATUS])); + gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]); + tcg_temp_free(tmp); + dc->base.is_jmp = DISAS_NORETURN; #endif } @@ -420,7 +424,11 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - gen_helper_eret(cpu_env, cpu_R[CR_BSTATUS], cpu_R[R_BA]); + TCGv tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_BSTATUS])); + gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]); + tcg_temp_free(tmp); + dc->base.is_jmp = DISAS_NORETURN; #endif } @@ -463,6 +471,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags) static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); + TCGv t1, t2; if (!gen_check_supervisor(dc)) { return; @@ -482,10 +491,19 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) * must perform the AND here, and anywhere else we need the * guest value of ipending. */ - tcg_gen_and_tl(cpu_R[instr.c], cpu_R[CR_IPENDING], cpu_R[CR_IENABLE]); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); + tcg_gen_ld_tl(t1, cpu_env, + offsetof(CPUNios2State, regs[CR_IPENDING])); + tcg_gen_ld_tl(t2, cpu_env, + offsetof(CPUNios2State, regs[CR_IENABLE])); + tcg_gen_and_tl(cpu_R[instr.c], t1, t2); + tcg_temp_free(t1); + tcg_temp_free(t2); break; default: - tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]); + tcg_gen_ld_tl(cpu_R[instr.c], cpu_env, + offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); break; } } @@ -522,7 +540,8 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) dc->base.is_jmp = DISAS_UPDATE; /* fall through */ default: - tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v); + tcg_gen_st_tl(v, cpu_env, + offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); break; } #endif @@ -909,7 +928,7 @@ void nios2_tcg_init(void) { int i; - for (i = 0; i < NUM_CORE_REGS; i++) { + for (i = 0; i < NUM_GP_REGS; i++) { cpu_R[i] = tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, regs[i]), regnames[i]); From patchwork Thu Mar 17 05:04:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552211 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp875523mag; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 09/51] linux-user/nios2: Only initialize SP and PC in target_cpu_copy_regs Date: Wed, 16 Mar 2022 22:04:56 -0700 Message-Id: <20220317050538.924111-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::535 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Drop the set of estatus in init_thread; it was clearly intended to be setting the value of CR_STATUS for the application, but we never actually performed that copy. However, the proper value is set in nios2_cpu_reset so we don't need to do anything here. We only initialize SP and EA in init_thread, there's no value in copying other uninitialized data into ENV. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/elfload.c | 1 - linux-user/nios2/cpu_loop.c | 22 ---------------------- 2 files changed, 23 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 23ff9659a5..8c85c933b7 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1096,7 +1096,6 @@ static void init_thread(struct target_pt_regs *regs, struct image_info *infop) { regs->ea = infop->entry; regs->sp = infop->start_stack; - regs->estatus = 0x3; } #define LO_COMMPAGE TARGET_PAGE_SIZE diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 7b20c024db..fa234cb2af 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -132,28 +132,6 @@ void cpu_loop(CPUNios2State *env) void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - env->regs[0] = 0; - env->regs[1] = regs->r1; - env->regs[2] = regs->r2; - env->regs[3] = regs->r3; - env->regs[4] = regs->r4; - env->regs[5] = regs->r5; - env->regs[6] = regs->r6; - env->regs[7] = regs->r7; - env->regs[8] = regs->r8; - env->regs[9] = regs->r9; - env->regs[10] = regs->r10; - env->regs[11] = regs->r11; - env->regs[12] = regs->r12; - env->regs[13] = regs->r13; - env->regs[14] = regs->r14; - env->regs[15] = regs->r15; - /* TODO: unsigned long orig_r2; */ - env->regs[R_RA] = regs->ra; - env->regs[R_FP] = regs->fp; env->regs[R_SP] = regs->sp; - env->regs[R_GP] = regs->gp; - env->regs[CR_ESTATUS] = regs->estatus; env->pc = regs->ea; - /* TODO: unsigned long orig_r7; */ } From patchwork Thu Mar 17 05:04:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552207 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp873008mag; Wed, 16 Mar 2022 22:07:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJydfPl/h5YAafis1dfizVA12kJ+zv1A3UiMwpK6Lr9kLaCphgTHKwAsMhdVxXl/8hxtWO7+ X-Received: by 2002:a05:6214:2627:b0:435:42bf:f2f9 with SMTP id gv7-20020a056214262700b0043542bff2f9mr2256947qvb.36.1647493659216; Wed, 16 Mar 2022 22:07:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647493659; cv=none; d=google.com; s=arc-20160816; b=afzW5M0bh0UA+QzlbtqF8b5/iB4VG5GH764oOMAetloP3z+MO7GBekb0jlTl/BjOVy K53xdgtXYDF4OJa+MN0qi+W1w5Sy8VGN862nU6S28rdy0/YNks7A+wVCHlAQJWY1cmRp kK14UcfLEvOax5bwt2cF21B1ACvTAFNwpK4pZzI8JEjOYY/v+iMbsmnCnvnSEd+Jozy4 M7Eylb5iMOtmNdZvXZJtAA7p8Z2DwkpL7YjNwEKI4Q9vpXowAOzz5rlhGYS/NbUgpzJs pAJagP2rLZuLXaHlNv47EyPgeuMOr6QtU3lYeBHMwzp2HXDlCOAc4469TvCvFwsz6yCp 2P9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Cj1Mv1TK+d1R4GNVLpYWtLlcIcx/OqQSWvfjy4IfC40=; b=oFB4Aquzrce0ZaKUBJakHFlD2nxH8JVjfXkPU2O5wdoYBtoHjjWvS2kPTszn9wmwPD oetrTeqmRqEAh+gB5F/SP14Hrr1Xn/hzlQ8CmLDUvg5hf4j4iKAdlYNDu12yyhJAtnsh itGA/jQmDJCKuJq/d9Am5PBts2Zd8VP/DXHdpkSKwjiXdY6lqT8KIrC4GKXHTtTU4FbY NS21BdMtOwTpBzUW48Fgr1Loda1lRnHoFHl5vrdf7S2xvjimDRpjUhepoU4fFxp4BSFC YX4StgF4nDsarD7U5sgK7UHwLSWTe7o/xjn4msv0/cd4D0zpwOJVHtQucRSXsVEc3xOF UCHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Irf3JKD0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 10/51] target/nios2: Remove cpu_interrupts_enabled Date: Wed, 16 Mar 2022 22:04:57 -0700 Message-Id: <20220317050538.924111-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is unused. The real computation of this value is located in nios2_cpu_exec_interrupt. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 9be128d63a..59e950dae6 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -226,11 +226,6 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr); #endif -static inline int cpu_interrupts_enabled(CPUNios2State *env) -{ - return env->regs[CR_STATUS] & CR_STATUS_PIE; -} - typedef CPUNios2State CPUArchState; typedef Nios2CPU ArchCPU; From patchwork Thu Mar 17 05:04:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552233 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp883387mag; Wed, 16 Mar 2022 22:31:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx7kRErepAnrzjppNY9wXyAk5XWZgtmuRE6VHVDsJ8xEHmgq4VKS+HydrY5OlH2mGg2kmg5 X-Received: by 2002:a05:622a:451:b0:2e1:cb95:8eb with SMTP id o17-20020a05622a045100b002e1cb9508ebmr2450137qtx.540.1647495065960; Wed, 16 Mar 2022 22:31:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647495065; cv=none; d=google.com; s=arc-20160816; b=oefbNd4XFAyeR3uy348VO830v+SzyS8NLrp6PEO6b8X3U3H6fQV4GiQ437AtPHC48f eye+BWXDMsdgHEKar7ZOcccgdcu9G+gM6urBxnm0L1LyaKOBIFLN7fC9OV9VTYjiliX0 coEkqine5p2TJLHH++F0kB6LZ3Id9cL4WUgNN8Bi3MdmFlJUkDLegRBJ4kjIolhDUGCU urOQbci2svlb/GBK3TIwcIz9nATtI2BUrggMQdYiU6bBTA976fHWH45DfnlALfdMrTWg 6EWyRH+vY2T1A0fmWTvJ+m7xBW3lOfC0R2IfDPxQuXvN1LorZlaeAgiav7sbRYYj69w2 57WA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ODzUuO9Bo/dCZ/z6T/TQX0tDH/2DhM3+AVV8gLtx3XM=; b=AYTKiKVHO9VbD+ghCo46KivUL3AqjHiM7cvk8GvZBODWyeidnrtHakjjHTcuUU61Wc 2BqTRvqbeFo+u104YW5h3lD4bTYC26jVUYjFH89HkrhV+xQgB8A5kyFAdZEdGUs4Rawv q8SfHMQLhLEKOzbzAGbWxNCZaSYtJhQXciG8GYjpnyVpI4jbqeMV+BND1/A6VOQP3wEs lQ3Klok643hIuTS9FoRQs+V+82EQGG1b/N+UhCDnGgdPJscEscOl503PZCnS12PaTzkq +adT6yZ1zwXkp0A/LC/iWyQ20qNCdM00DUVHJbnSDBYVucjn2qn08Dw/Kaqic50STvmO sA0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=v3a4TL5Q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 11/51] target/nios2: Split control registers away from general registers Date: Wed, 16 Mar 2022 22:04:58 -0700 Message-Id: <20220317050538.924111-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Place the control registers into their own array, env->ctrl[]. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 43 ++++++++-------- target/nios2/cpu.c | 19 +++---- target/nios2/helper.c | 106 +++++++++++++++++++-------------------- target/nios2/mmu.c | 26 +++++----- target/nios2/op_helper.c | 2 +- target/nios2/translate.c | 35 +++++++------ 6 files changed, 118 insertions(+), 113 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 59e950dae6..1bcbc9ed63 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -59,9 +59,6 @@ struct Nios2CPUClass { #define NUM_GP_REGS 32 #define NUM_CR_REGS 32 -/* GP regs + CR regs */ -#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS) - /* General purpose register aliases */ #define R_ZERO 0 #define R_AT 1 @@ -81,8 +78,7 @@ struct Nios2CPUClass { #define R_RA 31 /* Control register aliases */ -#define CR_BASE NUM_GP_REGS -#define CR_STATUS (CR_BASE + 0) +#define CR_STATUS 0 #define CR_STATUS_PIE (1 << 0) #define CR_STATUS_U (1 << 1) #define CR_STATUS_EH (1 << 2) @@ -92,19 +88,19 @@ struct Nios2CPUClass { #define CR_STATUS_PRS (63 << 16) #define CR_STATUS_NMI (1 << 22) #define CR_STATUS_RSIE (1 << 23) -#define CR_ESTATUS (CR_BASE + 1) -#define CR_BSTATUS (CR_BASE + 2) -#define CR_IENABLE (CR_BASE + 3) -#define CR_IPENDING (CR_BASE + 4) -#define CR_CPUID (CR_BASE + 5) -#define CR_CTL6 (CR_BASE + 6) -#define CR_EXCEPTION (CR_BASE + 7) -#define CR_PTEADDR (CR_BASE + 8) +#define CR_ESTATUS 1 +#define CR_BSTATUS 2 +#define CR_IENABLE 3 +#define CR_IPENDING 4 +#define CR_CPUID 5 +#define CR_CTL6 6 +#define CR_EXCEPTION 7 +#define CR_PTEADDR 8 #define CR_PTEADDR_PTBASE_SHIFT 22 #define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) #define CR_PTEADDR_VPN_SHIFT 2 #define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT) -#define CR_TLBACC (CR_BASE + 9) +#define CR_TLBACC 9 #define CR_TLBACC_IGN_SHIFT 25 #define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) #define CR_TLBACC_C (1 << 24) @@ -113,7 +109,7 @@ struct Nios2CPUClass { #define CR_TLBACC_X (1 << 21) #define CR_TLBACC_G (1 << 20) #define CR_TLBACC_PFN_MASK 0x000FFFFF -#define CR_TLBMISC (CR_BASE + 10) +#define CR_TLBMISC 10 #define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) #define CR_TLBMISC_RD (1 << 19) @@ -124,11 +120,11 @@ struct Nios2CPUClass { #define CR_TLBMISC_BAD (1 << 2) #define CR_TLBMISC_PERM (1 << 1) #define CR_TLBMISC_D (1 << 0) -#define CR_ENCINJ (CR_BASE + 11) -#define CR_BADADDR (CR_BASE + 12) -#define CR_CONFIG (CR_BASE + 13) -#define CR_MPUBASE (CR_BASE + 14) -#define CR_MPUACC (CR_BASE + 15) +#define CR_ENCINJ 11 +#define CR_BADADDR 12 +#define CR_CONFIG 13 +#define CR_MPUBASE 14 +#define CR_MPUACC 15 /* Exceptions */ #define EXCP_BREAK 0x1000 @@ -154,7 +150,8 @@ struct Nios2CPUClass { #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 struct CPUArchState { - uint32_t regs[NUM_CORE_REGS]; + uint32_t regs[NUM_GP_REGS]; + uint32_t ctrl[NUM_CR_REGS]; uint32_t pc; #if !defined(CONFIG_USER_ONLY) @@ -212,7 +209,7 @@ void do_nios2_semihosting(CPUNios2State *env); static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) { - return (env->regs[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : + return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : MMU_SUPERVISOR_IDX; } @@ -236,7 +233,7 @@ static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc, { *pc = env->pc; *cs_base = 0; - *flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U)); + *flags = env->ctrl[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U); } #endif /* NIOS2_CPU_H */ diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 40031c9f20..182ddcc18f 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -53,14 +53,15 @@ static void nios2_cpu_reset(DeviceState *dev) ncc->parent_reset(dev); - memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS); + memset(env->regs, 0, sizeof(env->regs)); + memset(env->ctrl, 0, sizeof(env->ctrl)); env->pc = cpu->reset_addr; #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ - env->regs[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE; + env->ctrl[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE; #else - env->regs[CR_STATUS] = 0; + env->ctrl[CR_STATUS] = 0; #endif } @@ -71,9 +72,9 @@ static void nios2_cpu_set_irq(void *opaque, int irq, int level) CPUNios2State *env = &cpu->env; CPUState *cs = CPU(cpu); - env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level); + env->ctrl[CR_IPENDING] = deposit32(env->ctrl[CR_IPENDING], irq, 1, !!level); - if (env->regs[CR_IPENDING]) { + if (env->ctrl[CR_IPENDING]) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -131,8 +132,8 @@ static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) CPUNios2State *env = &cpu->env; if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->regs[CR_STATUS] & CR_STATUS_PIE) && - (env->regs[CR_IPENDING] & env->regs[CR_IENABLE])) { + (env->ctrl[CR_STATUS] & CR_STATUS_PIE) && + (env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE])) { cs->exception_index = EXCP_IRQ; nios2_cpu_do_interrupt(cs); return true; @@ -163,7 +164,7 @@ static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) } else if (n == 32) { /* PC */ return gdb_get_reg32(mem_buf, env->pc); } else if (n < 49) { /* Status regs */ - return gdb_get_reg32(mem_buf, env->regs[n - 1]); + return gdb_get_reg32(mem_buf, env->ctrl[n - 33]); } /* Invalid regs */ @@ -185,7 +186,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } else if (n == 32) { /* PC */ env->pc = ldl_p(mem_buf); } else if (n < 49) { /* Status regs */ - env->regs[n - 1] = ldl_p(mem_buf); + env->ctrl[n - 33] = ldl_p(mem_buf); } return 4; diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 31cec29e89..90f918524e 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -56,38 +56,38 @@ void nios2_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_IRQ: - assert(env->regs[CR_STATUS] & CR_STATUS_PIE); + assert(env->ctrl[CR_STATUS] & CR_STATUS_PIE); qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc); - env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; - env->regs[CR_STATUS] |= CR_STATUS_IH; - env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; + env->ctrl[CR_STATUS] |= CR_STATUS_IH; + env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->regs[CR_EXCEPTION] &= ~(0x1F << 2); - env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; env->regs[R_EA] = env->pc + 4; env->pc = cpu->exception_addr; break; case EXCP_TLBD: - if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc); /* Fast TLB miss */ /* Variation from the spec. Table 3-35 of the cpu reference shows * estatus not being changed for TLB miss but this appears to * be incorrect. */ - env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; - env->regs[CR_STATUS] |= CR_STATUS_EH; - env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; + env->ctrl[CR_STATUS] |= CR_STATUS_EH; + env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->regs[CR_EXCEPTION] &= ~(0x1F << 2); - env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; - env->regs[CR_TLBMISC] &= ~CR_TLBMISC_DBL; - env->regs[CR_TLBMISC] |= CR_TLBMISC_WR; + env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; + env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; env->regs[R_EA] = env->pc + 4; env->pc = cpu->fast_tlb_miss_addr; @@ -95,13 +95,13 @@ void nios2_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc); /* Double TLB miss */ - env->regs[CR_STATUS] |= CR_STATUS_EH; - env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_STATUS] |= CR_STATUS_EH; + env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->regs[CR_EXCEPTION] &= ~(0x1F << 2); - env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; - env->regs[CR_TLBMISC] |= CR_TLBMISC_DBL; + env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL; env->pc = cpu->exception_addr; } @@ -112,15 +112,15 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TLBX: qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc); - env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; - env->regs[CR_STATUS] |= CR_STATUS_EH; - env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; + env->ctrl[CR_STATUS] |= CR_STATUS_EH; + env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->regs[CR_EXCEPTION] &= ~(0x1F << 2); - env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; - if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { - env->regs[CR_TLBMISC] |= CR_TLBMISC_WR; + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { + env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; } env->regs[R_EA] = env->pc + 4; @@ -132,16 +132,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_SUPERD: qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc); - if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { - env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { + env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; env->regs[R_EA] = env->pc + 4; } - env->regs[CR_STATUS] |= CR_STATUS_EH; - env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_STATUS] |= CR_STATUS_EH; + env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->regs[CR_EXCEPTION] &= ~(0x1F << 2); - env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; env->pc = cpu->exception_addr; break; @@ -150,16 +150,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TRAP: qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc); - if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { - env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { + env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; env->regs[R_EA] = env->pc + 4; } - env->regs[CR_STATUS] |= CR_STATUS_EH; - env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_STATUS] |= CR_STATUS_EH; + env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->regs[CR_EXCEPTION] &= ~(0x1F << 2); - env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; env->pc = cpu->exception_addr; break; @@ -175,16 +175,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) break; } - if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { - env->regs[CR_BSTATUS] = env->regs[CR_STATUS]; + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { + env->ctrl[CR_BSTATUS] = env->ctrl[CR_STATUS]; env->regs[R_BA] = env->pc + 4; } - env->regs[CR_STATUS] |= CR_STATUS_EH; - env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_STATUS] |= CR_STATUS_EH; + env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->regs[CR_EXCEPTION] &= ~(0x1F << 2); - env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; env->pc = cpu->exception_addr; break; @@ -227,8 +227,8 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr, Nios2CPU *cpu = NIOS2_CPU(cs); CPUNios2State *env = &cpu->env; - env->regs[CR_BADADDR] = addr; - env->regs[CR_EXCEPTION] = EXCP_UNALIGN << 2; + env->ctrl[CR_BADADDR] = addr; + env->ctrl[CR_EXCEPTION] = EXCP_UNALIGN << 2; helper_raise_exception(env, EXCP_UNALIGN); } @@ -266,7 +266,7 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, return false; } cs->exception_index = EXCP_SUPERA; - env->regs[CR_BADADDR] = address; + env->ctrl[CR_BADADDR] = address; cpu_loop_exit_restore(cs, retaddr); } } @@ -295,16 +295,16 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } if (access_type == MMU_INST_FETCH) { - env->regs[CR_TLBMISC] &= ~CR_TLBMISC_D; + env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_D; } else { - env->regs[CR_TLBMISC] |= CR_TLBMISC_D; + env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D; } - env->regs[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK; - env->regs[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK; - env->mmu.pteaddr_wr = env->regs[CR_PTEADDR]; + env->ctrl[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK; + env->ctrl[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK; + env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR]; cs->exception_index = excp; - env->regs[CR_BADADDR] = address; + env->ctrl[CR_BADADDR] = address; cpu_loop_exit_restore(cs, retaddr); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 4daab2a7ab..95900724e8 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -95,8 +95,8 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) v & CR_TLBACC_PFN_MASK); /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ - if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) { - int way = (env->regs[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); + if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { + int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; int g = (v & CR_TLBACC_G) ? 1 : 0; @@ -117,8 +117,8 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) entry->data = newData; } /* Auto-increment tlbmisc.WAY */ - env->regs[CR_TLBMISC] = - (env->regs[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) | + env->ctrl[CR_TLBMISC] = + (env->ctrl[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) | (((way + 1) & (cpu->tlb_num_ways - 1)) << CR_TLBMISC_WAY_SHIFT); } @@ -153,17 +153,17 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; - env->regs[CR_TLBACC] &= CR_TLBACC_IGN_MASK; - env->regs[CR_TLBACC] |= entry->data; - env->regs[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0; - env->regs[CR_TLBMISC] = + env->ctrl[CR_TLBACC] &= CR_TLBACC_IGN_MASK; + env->ctrl[CR_TLBACC] |= entry->data; + env->ctrl[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0; + env->ctrl[CR_TLBMISC] = (v & ~CR_TLBMISC_PID_MASK) | ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << CR_TLBMISC_PID_SHIFT); - env->regs[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK; - env->regs[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT; + env->ctrl[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK; + env->ctrl[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT; } else { - env->regs[CR_TLBMISC] = v; + env->ctrl[CR_TLBMISC] = v; } env->mmu.tlbmisc_wr = v; @@ -175,8 +175,8 @@ void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v) (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT); /* Writes to PTEADDR don't change the read-back VPN value */ - env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) | - (env->regs[CR_PTEADDR] & CR_PTEADDR_VPN_MASK); + env->ctrl[CR_PTEADDR] = ((v & ~CR_PTEADDR_VPN_MASK) | + (env->ctrl[CR_PTEADDR] & CR_PTEADDR_VPN_MASK)); env->mmu.pteaddr_wr = v; } diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index ee5ad8b23f..08ed3b4598 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -34,7 +34,7 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index) #ifndef CONFIG_USER_ONLY void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) { - env->regs[CR_STATUS] = new_status; + env->ctrl[CR_STATUS] = new_status; env->pc = new_pc; cpu_loop_exit(env_cpu(env)); } diff --git a/target/nios2/translate.c b/target/nios2/translate.c index e6e9a5ac6f..2e486651f5 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -395,7 +395,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) g_assert_not_reached(); #else TCGv tmp = tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_ESTATUS])); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS])); gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]); tcg_temp_free(tmp); @@ -425,7 +425,7 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) g_assert_not_reached(); #else TCGv tmp = tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_BSTATUS])); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS])); gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]); tcg_temp_free(tmp); @@ -481,7 +481,7 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) return; } - switch (instr.imm5 + CR_BASE) { + switch (instr.imm5) { case CR_IPENDING: /* * The value of the ipending register is synthetic. @@ -493,17 +493,15 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) */ t1 = tcg_temp_new(); t2 = tcg_temp_new(); - tcg_gen_ld_tl(t1, cpu_env, - offsetof(CPUNios2State, regs[CR_IPENDING])); - tcg_gen_ld_tl(t2, cpu_env, - offsetof(CPUNios2State, regs[CR_IENABLE])); + tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDING])); + tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE])); tcg_gen_and_tl(cpu_R[instr.c], t1, t2); tcg_temp_free(t1); tcg_temp_free(t2); break; default: tcg_gen_ld_tl(cpu_R[instr.c], cpu_env, - offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); + offsetof(CPUNios2State, ctrl[instr.imm5])); break; } } @@ -521,7 +519,7 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) R_TYPE(instr, code); TCGv v = load_gpr(dc, instr.a); - switch (instr.imm5 + CR_BASE) { + switch (instr.imm5) { case CR_PTEADDR: gen_helper_mmu_write_pteaddr(cpu_env, v); break; @@ -541,7 +539,7 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) /* fall through */ default: tcg_gen_st_tl(v, cpu_env, - offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); + offsetof(CPUNios2State, ctrl[instr.imm5])); break; } #endif @@ -774,7 +772,7 @@ illegal_op: t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); } -static const char * const regnames[NUM_CORE_REGS] = { +static const char * const gr_regnames[NUM_GP_REGS] = { "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", @@ -783,6 +781,9 @@ static const char * const regnames[NUM_CORE_REGS] = { "r20", "r21", "r22", "r23", "et", "bt", "gp", "sp", "fp", "ea", "ba", "ra", +}; + +static const char * const cr_regnames[NUM_CR_REGS] = { "status", "estatus", "bstatus", "ienable", "ipending", "cpuid", "reserved0", "exception", "pteaddr", "tlbacc", "tlbmisc", "reserved1", @@ -909,8 +910,14 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); - for (i = 0; i < NUM_CORE_REGS; i++) { - qemu_fprintf(f, "%9s=%8.8x ", regnames[i], env->regs[i]); + for (i = 0; i < NUM_GP_REGS; i++) { + qemu_fprintf(f, "%9s=%8.8x ", gr_regnames[i], env->regs[i]); + if ((i + 1) % 4 == 0) { + qemu_fprintf(f, "\n"); + } + } + for (i = 0; i < NUM_CR_REGS; i++) { + qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]); if ((i + 1) % 4 == 0) { qemu_fprintf(f, "\n"); } @@ -931,7 +938,7 @@ void nios2_tcg_init(void) for (i = 0; i < NUM_GP_REGS; i++) { cpu_R[i] = tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, regs[i]), - regnames[i]); + gr_regnames[i]); } cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, pc), "pc"); From patchwork Thu Mar 17 05:04:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552237 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp885294mag; Wed, 16 Mar 2022 22:34:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyKorAt+9nlcXoWZ6A2OXyde/gGSivKLjri5u0JfriHDHNoy9eNqLp51nrGEXY9KX7lfPH7 X-Received: by 2002:a05:622a:1a27:b0:2e0:64c2:7469 with SMTP id f39-20020a05622a1a2700b002e064c27469mr2484014qtb.187.1647495269037; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 12/51] target/nios2: Clean up nios2_cpu_dump_state Date: Wed, 16 Mar 2022 22:04:59 -0700 Message-Id: <20220317050538.924111-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::430 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not print control registers for user-only mode. Rename reserved control registers to "resN", where N is the control register index. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/translate.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 2e486651f5..45fe2f9a05 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -783,16 +783,18 @@ static const char * const gr_regnames[NUM_GP_REGS] = { "fp", "ea", "ba", "ra", }; +#ifndef CONFIG_USER_ONLY static const char * const cr_regnames[NUM_CR_REGS] = { "status", "estatus", "bstatus", "ienable", - "ipending", "cpuid", "reserved0", "exception", + "ipending", "cpuid", "res6", "exception", "pteaddr", "tlbacc", "tlbmisc", "reserved1", "badaddr", "config", "mpubase", "mpuacc", - "reserved2", "reserved3", "reserved4", "reserved5", - "reserved6", "reserved7", "reserved8", "reserved9", - "reserved10", "reserved11", "reserved12", "reserved13", - "reserved14", "reserved15", "reserved16", "reserved17", + "res16", "res17", "res18", "res19", + "res20", "res21", "res22", "res23", + "res24", "res25", "res26", "res27", + "res28", "res29", "res30", "res31", }; +#endif #include "exec/gen-icount.h" @@ -904,10 +906,6 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) CPUNios2State *env = &cpu->env; int i; - if (!env) { - return; - } - qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); for (i = 0; i < NUM_GP_REGS; i++) { @@ -916,13 +914,14 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "\n"); } } + +#if !defined(CONFIG_USER_ONLY) for (i = 0; i < NUM_CR_REGS; i++) { qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]); if ((i + 1) % 4 == 0) { qemu_fprintf(f, "\n"); } } -#if !defined(CONFIG_USER_ONLY) qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n", env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, From patchwork Thu Mar 17 05:05:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552209 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp874994mag; Wed, 16 Mar 2022 22:12:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJycjMb3xSkkw77i88jkAqwLVXVFf7WyZHuGJt6Badt41+6T/bQda86EKorEOgI/yWij/+eq X-Received: by 2002:a05:6214:21a9:b0:440:c9fd:75bb with SMTP id t9-20020a05621421a900b00440c9fd75bbmr2347599qvc.68.1647493921566; Wed, 16 Mar 2022 22:12:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647493921; cv=none; d=google.com; s=arc-20160816; b=Y+nqChEE3cgCKd/k/0SaGtUCkbBH8EwwLW0rGuQVIc66yP/9cWOKnU/tJi52vK8yI9 ShuhzEnjEKeuFmcwOb2RSVeJL1x5EmL7fjKPQxYpGJ/haEDbOkQ4wfKoXAQ6RyWaUyYb AAiVqFahRtUMumpE2aCg+KS5Sf1Quor222KVpzkGw4n64CVFz7vaUqAJ/CiFynZYA88g NZdzP2c42/R5SE5UjecNq/kybWZI45exO59xJbWELrmFrOdNSvF/z4xpApObw39aGSag K01YRsW9vF/xbYGSGmWNQ4hXsFJ9FAqF5Rd9VGSILd6mFgUu0nHQ9h+VLoUe0yA6xDzx ypqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Gt6Df7YFZj3yIOaHOAXNxeneFRB5t2HH9HYYGKeZPd8=; b=B4D0tZ4a3+9Grhr3cgX8szaUX5UcRyhUqI1nPJ2QuirewtTXNbVlmcu+Kp7Eq9+WvU S8YDr+KijLbiiQ30xVdp6cIoImgFLhQhU1sXryvYnc3X/q0jsFQmQkM5juoKNUpe3A37 2mkKbywqXkbXrtMeZ8bkkpADo5Hj259gUlcbPhun7CW6FcQgyPDoVz7KQVMRCw2jJSsG yKqnn7T0d5xdSwodiWm/LsvuCud6p9xPZ+sd69KuQgUPtPsl21KnjoLgRz/LyK+5R2xs e4wGp8otXAyXoUIwF2D4SybFBhOQBzPEfnrc28KPjkdAavAdOwE1F0Rp3p1GWXxQ/m4h nBSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AoMDWL3R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 13/51] target/nios2: Use hw/registerfields.h for CR_STATUS fields Date: Wed, 16 Mar 2022 22:05:00 -0700 Message-Id: <20220317050538.924111-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add all fields; retain the helper macros for single bit fields. So far there are no uses of the multi-bit status fields. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 1bcbc9ed63..ecf8cc929f 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -23,6 +23,7 @@ #include "exec/cpu-defs.h" #include "hw/core/cpu.h" +#include "hw/registerfields.h" #include "qom/object.h" typedef struct CPUArchState CPUNios2State; @@ -79,15 +80,24 @@ struct Nios2CPUClass { /* Control register aliases */ #define CR_STATUS 0 -#define CR_STATUS_PIE (1 << 0) -#define CR_STATUS_U (1 << 1) -#define CR_STATUS_EH (1 << 2) -#define CR_STATUS_IH (1 << 3) -#define CR_STATUS_IL (63 << 4) -#define CR_STATUS_CRS (63 << 10) -#define CR_STATUS_PRS (63 << 16) -#define CR_STATUS_NMI (1 << 22) -#define CR_STATUS_RSIE (1 << 23) + +FIELD(CR_STATUS, PIE, 0, 1) +FIELD(CR_STATUS, U, 1, 1) +FIELD(CR_STATUS, EH, 2, 1) +FIELD(CR_STATUS, IH, 3, 1) +FIELD(CR_STATUS, IL, 4, 6) +FIELD(CR_STATUS, CRS, 10, 6) +FIELD(CR_STATUS, PRS, 16, 6) +FIELD(CR_STATUS, NMI, 22, 1) +FIELD(CR_STATUS, RSIE, 23, 1) + +#define CR_STATUS_PIE R_CR_STATUS_PIE_MASK +#define CR_STATUS_U R_CR_STATUS_U_MASK +#define CR_STATUS_EH R_CR_STATUS_EH_MASK +#define CR_STATUS_IH R_CR_STATUS_IH_MASK +#define CR_STATUS_NMI R_CR_STATUS_NMI_MASK +#define CR_STATUS_RSIE R_CR_STATUS_RSIE_MASK + #define CR_ESTATUS 1 #define CR_BSTATUS 2 #define CR_IENABLE 3 From patchwork Thu Mar 17 05:05:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552241 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp886616mag; Wed, 16 Mar 2022 22:37:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwpHjtc5tDdwU8xJ63HchWn2XPQEUu6fiRMOfA+T1iXUyTOm/yO9pl5cthGrIgKn2eyxRfr X-Received: by 2002:a05:6214:29ef:b0:440:ab99:5bc5 with SMTP id jv15-20020a05621429ef00b00440ab995bc5mr2180064qvb.113.1647495433852; Wed, 16 Mar 2022 22:37:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647495433; cv=none; d=google.com; s=arc-20160816; b=G9iuPDxsIWoBApPLg8SIZ3LLXYCPQESu/6kLjiA13u02pZ0SuPQGXEyX7uTL2T9UAU PtOWX8bxhlowZuStOytjKVvE3aBE0bQYdlxaEdU/E2g4z05ZCZPfm3F0GWj0l/rCtUQn a8oDe6l9AHP4Uio+qrTFbktiF50j5v4y02M4xsWKCaq/TZ309ciuaddFJAozXpCKMbvc 90itWQ8SLLLhXwAwTFutraCtNw2WRaJkVd6yOJJxA+88GksWQTAD+bKz6EviaoEJHqhk dSFqc+qFcX60KUT4OpXJq0GFPfeiKxwAIhyi00vOHQ3/PzOsna4185C3v/MuBarAdjTS 5vHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9FWwMXqC9iumPnJnO/Sltv35jl4kn2h5ImUTKmfNWoM=; b=F5C3fNu/tAHxB83qvESYGliwRzoY2r13C0iTwavbIBd6Z7pmzorF/rYHtO3LXntyXJ dDguFjo2XJpmmHFsZDg2dPfV61zzWB6FVlEqffzHNY7sj3ZGu2pwjRAumOCMs/KMdVuC 5dFBaOOdpiJ06IV2XeQbZAq20mcZsUC6ZHlUE9YS37uLF8O2ZiEbqA/+S5NAFllOFuwG AMAbbgdaxyZN/04GKx/t/rJY4ADw2f2yfIRiMTrf1cn9/G2JddepGSO5NoxKqzLVbsP9 zOJdezee6Bg8uAX2yuRs1+3X2oLuM1wdRPLgd2aIcGW3+1i2zdslMDM05jRw3j1TgP55 WDeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=c8da+3g+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 14/51] target/nios2: Use hw/registerfields.h for CR_EXCEPTION fields Date: Wed, 16 Mar 2022 22:05:01 -0700 Message-Id: <20220317050538.924111-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1031 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use FIELD_DP32 instead of manual shifting and masking. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 4 ++++ target/nios2/helper.c | 37 ++++++++++++++++++++++--------------- 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index ecf8cc929f..963cdec161 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -105,6 +105,10 @@ FIELD(CR_STATUS, RSIE, 23, 1) #define CR_CPUID 5 #define CR_CTL6 6 #define CR_EXCEPTION 7 + +FIELD(CR_EXCEPTION, CAUSE, 2, 5) +FIELD(CR_EXCEPTION, ECCFTL, 31, 1) + #define CR_PTEADDR 8 #define CR_PTEADDR_PTBASE_SHIFT 22 #define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 90f918524e..54458a5447 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -64,8 +64,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |= CR_STATUS_IH; env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); env->regs[R_EA] = env->pc + 4; env->pc = cpu->exception_addr; @@ -83,8 +84,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |= CR_STATUS_EH; env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; @@ -98,8 +100,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |= CR_STATUS_EH; env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL; @@ -116,8 +119,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |= CR_STATUS_EH; env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; @@ -140,8 +144,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |= CR_STATUS_EH; env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); env->pc = cpu->exception_addr; break; @@ -158,8 +163,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |= CR_STATUS_EH; env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); env->pc = cpu->exception_addr; break; @@ -183,8 +189,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |= CR_STATUS_EH; env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); env->pc = cpu->exception_addr; break; @@ -228,7 +235,7 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr, CPUNios2State *env = &cpu->env; env->ctrl[CR_BADADDR] = addr; - env->ctrl[CR_EXCEPTION] = EXCP_UNALIGN << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(0, CR_EXCEPTION, CAUSE, EXCP_UNALIGN); helper_raise_exception(env, EXCP_UNALIGN); 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 15/51] target/nios2: Use hw/registerfields.h for CR_TLBADDR fields Date: Wed, 16 Mar 2022 22:05:02 -0700 Message-Id: <20220317050538.924111-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::630 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use FIELD_EX32 and FIELD_DP32 instead of manual manipulation of the fields. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 8 ++++---- target/nios2/helper.c | 4 ++-- target/nios2/mmu.c | 17 +++++++++-------- target/nios2/translate.c | 2 +- 4 files changed, 16 insertions(+), 15 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 963cdec161..e1c2bf8c31 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -110,10 +110,10 @@ FIELD(CR_EXCEPTION, CAUSE, 2, 5) FIELD(CR_EXCEPTION, ECCFTL, 31, 1) #define CR_PTEADDR 8 -#define CR_PTEADDR_PTBASE_SHIFT 22 -#define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) -#define CR_PTEADDR_VPN_SHIFT 2 -#define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT) + +FIELD(CR_PTEADDR, VPN, 2, 20) +FIELD(CR_PTEADDR, PTBASE, 22, 10) + #define CR_TLBACC 9 #define CR_TLBACC_IGN_SHIFT 25 #define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 54458a5447..da3a289fc7 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -306,8 +306,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } else { env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D; } - env->ctrl[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK; - env->ctrl[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK; + env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN, + address >> TARGET_PAGE_BITS); env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR]; cs->exception_index = excp; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 95900724e8..75afc56daf 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -97,7 +97,7 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); - int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; + int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; int g = (v & CR_TLBACC_G) ? 1 : 0; int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0; @@ -148,7 +148,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) /* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */ if (v & CR_TLBMISC_RD) { int way = (v >> CR_TLBMISC_WAY_SHIFT); - int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; + int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); Nios2TLBEntry *entry = &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; @@ -160,8 +160,9 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) (v & ~CR_TLBMISC_PID_MASK) | ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << CR_TLBMISC_PID_SHIFT); - env->ctrl[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK; - env->ctrl[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT; + env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], + CR_PTEADDR, VPN, + entry->tag >> TARGET_PAGE_BITS); } else { env->ctrl[CR_TLBMISC] = v; } @@ -171,12 +172,12 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v) { - trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT, - (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT); + trace_nios2_mmu_write_pteaddr(FIELD_EX32(v, CR_PTEADDR, PTBASE), + FIELD_EX32(v, CR_PTEADDR, VPN)); /* Writes to PTEADDR don't change the read-back VPN value */ - env->ctrl[CR_PTEADDR] = ((v & ~CR_PTEADDR_VPN_MASK) | - (env->ctrl[CR_PTEADDR] & CR_PTEADDR_VPN_MASK)); + env->ctrl[CR_PTEADDR] = ((v & ~R_CR_PTEADDR_VPN_MASK) | + (env->ctrl[CR_PTEADDR] & R_CR_PTEADDR_VPN_MASK)); env->mmu.pteaddr_wr = v; } diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 45fe2f9a05..9b81a2b29e 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -923,7 +923,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n", - env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK, + env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, env->mmu.tlbacc_wr); #endif From patchwork Thu Mar 17 05:05:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552215 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp876414mag; Wed, 16 Mar 2022 22:15:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwWQlp9Ize9AtcVZf9BgqLDyItBMEZcFF8kkJyHePC+XEmIU85o0ujUlelwhFmuwm/8vh2p X-Received: by 2002:a05:622a:58d:b0:2e1:d246:fb1 with SMTP id c13-20020a05622a058d00b002e1d2460fb1mr2447409qtb.132.1647494105938; Wed, 16 Mar 2022 22:15:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647494105; cv=none; d=google.com; s=arc-20160816; b=xqenN5iR8IykjkiEyXrK+JFlaHgX8qneMazkkLzlCqnMP/6sEF+kISrx71Vd6w3NZQ TRLK1iIytlwgqDfkXVr6QORnUtRXlR2JgsNs2A3jtp8KfXHOiDN3V7p0vIayiEreia64 PaKLxxY9iA8IkDXV2b/700tCQLJe0o5dSoFdMutmIxx3SygnFAGwprLBtw6SB2/ZAh5w AYx7CsGcOVFS7FRbxu2MyMTPnDzRfHM1yvp25P2zuciLauvG6ANk3RvgeE1fCHJXNSf/ 3fgZ7jrO/2RCSBFHq3pIDWtDm66M1kkRUwqWVdIXWVau0qMVCQEe00QmKcGKLMkfOdY4 JstQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GKFLxmbTYTFJV6/p4TM5MrilKQbtlOw6w8FSPR9X89E=; b=oiUzOJCb6I8KgYsKH+1ISQNNnYlrruVxGQIBE9EJFv5QBKaR4+z4f510F/5sVHqryQ YyukHMtvM8HWemu8LsLQy7y1bKjfZqZo44PtllYj+efXi8sobLeF4jm0h1APYBsCwG9x orSZ+KGd+Uwg/+RBMJPiK6N4t6lbd9pTrR1tixdbpMNVObZxKpXCba1R+OzyNyVNby47 cq/0+aiWL+yczCHDy1nLEl+XdcOBHtuqMocIWoQWi0E5yEqa2/+AFh4RjrbUxgTjogYI otSUjaE/W0wsWH4paVZvlcCSv6RFFlerHNhtGqBBPh0D5bOk3IhiLiqSKDu7jZ+HGt2c /oNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="SZpJt/il"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 16/51] target/nios2: Use hw/registerfields.h for CR_TLBACC fields Date: Wed, 16 Mar 2022 22:05:03 -0700 Message-Id: <20220317050538.924111-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Retain the helper macros for single bit fields as aliases to the longer R_*_MASK names. Use FIELD_EX32 and FIELD_DP32 instead of manually manipulating the fields. Since we're rewriting the references to CR_TLBACC_IGN_* anyway, we correct the name of this field to IG, which is its name in the official CPU documentation. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 23 +++++++++++++++-------- target/nios2/mmu.c | 16 ++++++++-------- 2 files changed, 23 insertions(+), 16 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index e1c2bf8c31..25b77916ca 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -115,14 +115,21 @@ FIELD(CR_PTEADDR, VPN, 2, 20) FIELD(CR_PTEADDR, PTBASE, 22, 10) #define CR_TLBACC 9 -#define CR_TLBACC_IGN_SHIFT 25 -#define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) -#define CR_TLBACC_C (1 << 24) -#define CR_TLBACC_R (1 << 23) -#define CR_TLBACC_W (1 << 22) -#define CR_TLBACC_X (1 << 21) -#define CR_TLBACC_G (1 << 20) -#define CR_TLBACC_PFN_MASK 0x000FFFFF + +FIELD(CR_TLBACC, PFN, 0, 20) +FIELD(CR_TLBACC, G, 20, 1) +FIELD(CR_TLBACC, X, 21, 1) +FIELD(CR_TLBACC, W, 22, 1) +FIELD(CR_TLBACC, R, 23, 1) +FIELD(CR_TLBACC, C, 24, 1) +FIELD(CR_TLBACC, IG, 25, 7) + +#define CR_TLBACC_C R_CR_TLBACC_C_MASK +#define CR_TLBACC_R R_CR_TLBACC_R_MASK +#define CR_TLBACC_W R_CR_TLBACC_W_MASK +#define CR_TLBACC_X R_CR_TLBACC_X_MASK +#define CR_TLBACC_G R_CR_TLBACC_G_MASK + #define CR_TLBMISC 10 #define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 75afc56daf..826cd2afb4 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -49,7 +49,7 @@ unsigned int mmu_translate(CPUNios2State *env, } lu->vaddr = vaddr & TARGET_PAGE_MASK; - lu->paddr = (entry->data & CR_TLBACC_PFN_MASK) << TARGET_PAGE_BITS; + lu->paddr = FIELD_EX32(entry->data, CR_TLBACC, PFN) << TARGET_PAGE_BITS; lu->prot = ((entry->data & CR_TLBACC_R) ? PAGE_READ : 0) | ((entry->data & CR_TLBACC_W) ? PAGE_WRITE : 0) | ((entry->data & CR_TLBACC_X) ? PAGE_EXEC : 0); @@ -86,27 +86,27 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) CPUState *cs = env_cpu(env); Nios2CPU *cpu = env_archcpu(env); - trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT, + trace_nios2_mmu_write_tlbacc(FIELD_EX32(v, CR_TLBACC, IG), (v & CR_TLBACC_C) ? 'C' : '.', (v & CR_TLBACC_R) ? 'R' : '.', (v & CR_TLBACC_W) ? 'W' : '.', (v & CR_TLBACC_X) ? 'X' : '.', (v & CR_TLBACC_G) ? 'G' : '.', - v & CR_TLBACC_PFN_MASK); + FIELD_EX32(v, CR_TLBACC, PFN)); /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; - int g = (v & CR_TLBACC_G) ? 1 : 0; - int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0; + int g = FIELD_EX32(v, CR_TLBACC, G); + int valid = FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000; Nios2TLBEntry *entry = &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; uint32_t newTag = (vpn << 12) | (g << 11) | (valid << 10) | pid; uint32_t newData = v & (CR_TLBACC_C | CR_TLBACC_R | CR_TLBACC_W | - CR_TLBACC_X | CR_TLBACC_PFN_MASK); + CR_TLBACC_X | R_CR_TLBACC_PFN_MASK); if ((entry->tag != newTag) || (entry->data != newData)) { if (entry->tag & (1 << 10)) { @@ -153,7 +153,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; - env->ctrl[CR_TLBACC] &= CR_TLBACC_IGN_MASK; + env->ctrl[CR_TLBACC] &= R_CR_TLBACC_IG_MASK; env->ctrl[CR_TLBACC] |= entry->data; env->ctrl[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0; env->ctrl[CR_TLBMISC] = @@ -208,7 +208,7 @@ void dump_mmu(CPUNios2State *env) entry->tag >> 12, entry->tag & ((1 << cpu->pid_num_bits) - 1), (entry->tag & (1 << 11)) ? 'G' : '-', - entry->data & CR_TLBACC_PFN_MASK, + FIELD_EX32(entry->data, CR_TLBACC, PFN), (entry->data & CR_TLBACC_C) ? 'C' : '-', (entry->data & CR_TLBACC_R) ? 'R' : '-', (entry->data & CR_TLBACC_W) ? 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 17/51] target/nios2: Rename CR_TLBMISC_WR to CR_TLBMISC_WE Date: Wed, 16 Mar 2022 22:05:04 -0700 Message-Id: <20220317050538.924111-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" WE is the architectural name of the field, not WR. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 2 +- target/nios2/helper.c | 4 ++-- target/nios2/mmu.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 25b77916ca..81472be686 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -134,7 +134,7 @@ FIELD(CR_TLBACC, IG, 25, 7) #define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) #define CR_TLBMISC_RD (1 << 19) -#define CR_TLBMISC_WR (1 << 18) +#define CR_TLBMISC_WE (1 << 18) #define CR_TLBMISC_PID_SHIFT 4 #define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT) #define CR_TLBMISC_DBL (1 << 3) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index da3a289fc7..308d66ad93 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -89,7 +89,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) cs->exception_index); env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; + env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; env->regs[R_EA] = env->pc + 4; env->pc = cpu->fast_tlb_miss_addr; @@ -124,7 +124,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) cs->exception_index); if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; + env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; } env->regs[R_EA] = env->pc + 4; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 826cd2afb4..0f33ea5e04 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -95,7 +95,7 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) FIELD_EX32(v, CR_TLBACC, PFN)); /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ - if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { + if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WE) { int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; @@ -133,7 +133,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT, (v & CR_TLBMISC_RD) ? 'R' : '.', - (v & CR_TLBMISC_WR) ? 'W' : '.', + (v & CR_TLBMISC_WE) ? 'W' : '.', (v & CR_TLBMISC_DBL) ? '2' : '.', (v & CR_TLBMISC_BAD) ? 'B' : '.', (v & CR_TLBMISC_PERM) ? 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 18/51] target/nios2: Use hw/registerfields.h for CR_TLBMISC fields Date: Wed, 16 Mar 2022 22:05:05 -0700 Message-Id: <20220317050538.924111-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1035 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use FIELD_EX32 and FIELD_DP32 instead of managing the masking by hand. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 29 +++++++++++++++++++---------- target/nios2/helper.c | 7 ++----- target/nios2/mmu.c | 35 +++++++++++++++++------------------ target/nios2/translate.c | 2 +- 4 files changed, 39 insertions(+), 34 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 81472be686..7f805a933e 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -131,16 +131,25 @@ FIELD(CR_TLBACC, IG, 25, 7) #define CR_TLBACC_G R_CR_TLBACC_G_MASK #define CR_TLBMISC 10 -#define CR_TLBMISC_WAY_SHIFT 20 -#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) -#define CR_TLBMISC_RD (1 << 19) -#define CR_TLBMISC_WE (1 << 18) -#define CR_TLBMISC_PID_SHIFT 4 -#define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT) -#define CR_TLBMISC_DBL (1 << 3) -#define CR_TLBMISC_BAD (1 << 2) -#define CR_TLBMISC_PERM (1 << 1) -#define CR_TLBMISC_D (1 << 0) + +FIELD(CR_TLBMISC, D, 0, 1) +FIELD(CR_TLBMISC, PERM, 1, 1) +FIELD(CR_TLBMISC, BAD, 2, 1) +FIELD(CR_TLBMISC, DBL, 3, 1) +FIELD(CR_TLBMISC, PID, 4, 14) +FIELD(CR_TLBMISC, WE, 18, 1) +FIELD(CR_TLBMISC, RD, 19, 1) +FIELD(CR_TLBMISC, WAY, 20, 4) +FIELD(CR_TLBMISC, EE, 24, 1) + +#define CR_TLBMISC_EE R_CR_TLBMISC_EE_MASK +#define CR_TLBMISC_RD R_CR_TLBMISC_RD_MASK +#define CR_TLBMISC_WE R_CR_TLBMISC_WE_MASK +#define CR_TLBMISC_DBL R_CR_TLBMISC_DBL_MASK +#define CR_TLBMISC_BAD R_CR_TLBMISC_BAD_MASK +#define CR_TLBMISC_PERM R_CR_TLBMISC_PERM_MASK +#define CR_TLBMISC_D R_CR_TLBMISC_D_MASK + #define CR_ENCINJ 11 #define CR_BADADDR 12 #define CR_CONFIG 13 diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 308d66ad93..52a49f7ead 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -301,11 +301,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, return false; } - if (access_type == MMU_INST_FETCH) { - env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_D; - } else { - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D; - } + env->ctrl[CR_TLBMISC] = FIELD_DP32(env->ctrl[CR_TLBMISC], CR_TLBMISC, D, + access_type != MMU_INST_FETCH); env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN, address >> TARGET_PAGE_BITS); env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR]; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 0f33ea5e04..d9b690b78e 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -33,7 +33,7 @@ unsigned int mmu_translate(CPUNios2State *env, target_ulong vaddr, int rw, int mmu_idx) { Nios2CPU *cpu = env_archcpu(env); - int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; + int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); int vpn = vaddr >> 12; int way, n_ways = cpu->tlb_num_ways; @@ -96,9 +96,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WE) { - int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); + int way = FIELD_EX32(env->ctrl[CR_TLBMISC], CR_TLBMISC, WAY); int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); - int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; + int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); int g = FIELD_EX32(v, CR_TLBACC, G); int valid = FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000; Nios2TLBEntry *entry = @@ -117,10 +117,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) entry->data = newData; } /* Auto-increment tlbmisc.WAY */ - env->ctrl[CR_TLBMISC] = - (env->ctrl[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) | - (((way + 1) & (cpu->tlb_num_ways - 1)) << - CR_TLBMISC_WAY_SHIFT); + env->ctrl[CR_TLBMISC] = FIELD_DP32(env->ctrl[CR_TLBMISC], + CR_TLBMISC, WAY, + (way + 1) & (cpu->tlb_num_ways - 1)); } /* Writes to TLBACC don't change the read-back value */ @@ -130,24 +129,25 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) { Nios2CPU *cpu = env_archcpu(env); + uint32_t new_pid = FIELD_EX32(v, CR_TLBMISC, PID); + uint32_t old_pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); + uint32_t way = FIELD_EX32(v, CR_TLBMISC, WAY); - trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT, + trace_nios2_mmu_write_tlbmisc(way, (v & CR_TLBMISC_RD) ? 'R' : '.', (v & CR_TLBMISC_WE) ? 'W' : '.', (v & CR_TLBMISC_DBL) ? '2' : '.', (v & CR_TLBMISC_BAD) ? 'B' : '.', (v & CR_TLBMISC_PERM) ? 'P' : '.', (v & CR_TLBMISC_D) ? 'D' : '.', - (v & CR_TLBMISC_PID_MASK) >> 4); + new_pid); - if ((v & CR_TLBMISC_PID_MASK) != - (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) { - mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> - CR_TLBMISC_PID_SHIFT); + if (new_pid != old_pid) { + mmu_flush_pid(env, old_pid); } + /* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */ if (v & CR_TLBMISC_RD) { - int way = (v >> CR_TLBMISC_WAY_SHIFT); int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); Nios2TLBEntry *entry = &env->mmu.tlb[(way * cpu->tlb_num_ways) + @@ -156,10 +156,9 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) env->ctrl[CR_TLBACC] &= R_CR_TLBACC_IG_MASK; env->ctrl[CR_TLBACC] |= entry->data; env->ctrl[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0; - env->ctrl[CR_TLBMISC] = - (v & ~CR_TLBMISC_PID_MASK) | - ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << - CR_TLBMISC_PID_SHIFT); + env->ctrl[CR_TLBMISC] = FIELD_DP32(v, CR_TLBMISC, PID, + entry->tag & + ((1 << cpu->pid_num_bits) - 1)); env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN, entry->tag >> TARGET_PAGE_BITS); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 9b81a2b29e..459e30b338 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -924,7 +924,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) } qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n", env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, - (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, + FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID), env->mmu.tlbacc_wr); #endif qemu_fprintf(f, "\n\n"); From patchwork Thu Mar 17 05:05:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552217 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp877485mag; Wed, 16 Mar 2022 22:17:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzkMoqua8EXwxX2g5ThcJCpC0fVQOqS1R8drrl4a6cj6oVOq9JgjZ9slwC0fDdNI5EEw1XM X-Received: by 2002:ac8:570c:0:b0:2e1:ee0c:71c5 with SMTP id 12-20020ac8570c000000b002e1ee0c71c5mr2408718qtw.365.1647494246125; Wed, 16 Mar 2022 22:17:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647494246; cv=none; d=google.com; s=arc-20160816; b=HvxNEkRLFs2J7+UmgCogGh+CnLplxsS02Ppjz9puRE2yPUOsc6yKDF9BUUggzXmrW5 hfM13ODC2Bu+/BxF/WpVWzMYaW8yYkl8yALK33KprXCkkgPlbd1ouVD8Ll5JJCqFdzfY jtZezpiCz8/E5iqk7JchTyaNum5Ax23I9b7au+xQT9N5dqjvLRXE04iZ54kwV9C/gthQ 9kO4AXmfe6qTuqfdBgA5mD/crIELohW+Q2SfC7mN7qAKk6i4mzJuFVhj4ceEOkyxVhv4 WBhCXspe2E7CvBbwQfG3zKDO5MdwnuBu9OeI/PTyiv2sPSrCKXNPsfUXWtoPKwCIUW8j KaxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=e6sq5+VxzJ+iyeBdvkBx4ESzy/gdXULWUf0uyVhwts4=; b=W//2nciV0T7f+L1dqc8ycU4SfrvO/g7NMbWthVmFzkYQRI6xzWY5122aaW9puaqD02 I3fRxOsqVCdrduj8aWJpuswFuXx8dhQh9vqaA32UYDT0gy7DyHY2Xnamz/OSKIWLm9ak XVBuMqFzTQRPP4n3/FPXKmssfnhABq4LDhL01cMZPQKGYUxinrFszFzp93sv8hYUpvMq U8QJRfZctzlEr7dB6yuqB4Ei5JNRw44ixsFC5MFDGgnIcc2yxcqS/AfcdtA3Ucn20Cbe zTrRXeQZQD+NQlUtgPTT3akDZsZ6LyVu0sZ2rfGznSWhi1iYT8rVglgOABFTp+aikPNT TpVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=h57VvCk4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 19/51] target/nios2: Move R_FOO and CR_BAR into enumerations Date: Wed, 16 Mar 2022 22:05:06 -0700 Message-Id: <20220317050538.924111-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These symbols become available to the debugger. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 72 ++++++++++++++++++++++------------------------ 1 file changed, 35 insertions(+), 37 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 7f805a933e..555972fe6b 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -61,25 +61,43 @@ struct Nios2CPUClass { #define NUM_CR_REGS 32 /* General purpose register aliases */ -#define R_ZERO 0 -#define R_AT 1 -#define R_RET0 2 -#define R_RET1 3 -#define R_ARG0 4 -#define R_ARG1 5 -#define R_ARG2 6 -#define R_ARG3 7 -#define R_ET 24 -#define R_BT 25 -#define R_GP 26 -#define R_SP 27 -#define R_FP 28 -#define R_EA 29 -#define R_BA 30 -#define R_RA 31 +enum { + R_ZERO = 0, + R_AT = 1, + R_RET0 = 2, + R_RET1 = 3, + R_ARG0 = 4, + R_ARG1 = 5, + R_ARG2 = 6, + R_ARG3 = 7, + R_ET = 24, + R_BT = 25, + R_GP = 26, + R_SP = 27, + R_FP = 28, + R_EA = 29, + R_BA = 30, + R_RA = 31, +}; /* Control register aliases */ -#define CR_STATUS 0 +enum { + CR_STATUS = 0, + CR_ESTATUS = 1, + CR_BSTATUS = 2, + CR_IENABLE = 3, + CR_IPENDING = 4, + CR_CPUID = 5, + CR_EXCEPTION = 7, + CR_PTEADDR = 8, + CR_TLBACC = 9, + CR_TLBMISC = 10, + CR_ENCINJ = 11, + CR_BADADDR = 12, + CR_CONFIG = 13, + CR_MPUBASE = 14, + CR_MPUACC = 15, +}; FIELD(CR_STATUS, PIE, 0, 1) FIELD(CR_STATUS, U, 1, 1) @@ -98,24 +116,12 @@ FIELD(CR_STATUS, RSIE, 23, 1) #define CR_STATUS_NMI R_CR_STATUS_NMI_MASK #define CR_STATUS_RSIE R_CR_STATUS_RSIE_MASK -#define CR_ESTATUS 1 -#define CR_BSTATUS 2 -#define CR_IENABLE 3 -#define CR_IPENDING 4 -#define CR_CPUID 5 -#define CR_CTL6 6 -#define CR_EXCEPTION 7 - FIELD(CR_EXCEPTION, CAUSE, 2, 5) FIELD(CR_EXCEPTION, ECCFTL, 31, 1) -#define CR_PTEADDR 8 - FIELD(CR_PTEADDR, VPN, 2, 20) FIELD(CR_PTEADDR, PTBASE, 22, 10) -#define CR_TLBACC 9 - FIELD(CR_TLBACC, PFN, 0, 20) FIELD(CR_TLBACC, G, 20, 1) FIELD(CR_TLBACC, X, 21, 1) @@ -130,8 +136,6 @@ FIELD(CR_TLBACC, IG, 25, 7) #define CR_TLBACC_X R_CR_TLBACC_X_MASK #define CR_TLBACC_G R_CR_TLBACC_G_MASK -#define CR_TLBMISC 10 - FIELD(CR_TLBMISC, D, 0, 1) FIELD(CR_TLBMISC, PERM, 1, 1) FIELD(CR_TLBMISC, BAD, 2, 1) @@ -150,12 +154,6 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define CR_TLBMISC_PERM R_CR_TLBMISC_PERM_MASK #define CR_TLBMISC_D R_CR_TLBMISC_D_MASK -#define CR_ENCINJ 11 -#define CR_BADADDR 12 -#define CR_CONFIG 13 -#define CR_MPUBASE 14 -#define CR_MPUACC 15 - /* Exceptions */ #define EXCP_BREAK 0x1000 #define EXCP_RESET 0 From patchwork Thu Mar 17 05:05:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552221 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp878632mag; Wed, 16 Mar 2022 22:20:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwe23/sRhNGYB0G3lQGQ0lN35hGeQfMnt/hyOwWFhodCpvUO41a7NOcnEWwSnU3ZWGU+hhy X-Received: by 2002:ac8:5e10:0:b0:2e1:cdc7:a73 with SMTP id h16-20020ac85e10000000b002e1cdc70a73mr2466817qtx.72.1647494414388; Wed, 16 Mar 2022 22:20:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647494414; cv=none; d=google.com; s=arc-20160816; b=k/WNsew9HO/ZIAeuaxV7fVg/qT4DLPAUtzQyTbZMwI8Px5sBVmLm2TwoAedUHBn+SJ DZHH1E5CWMw7ymNP4COPycjlBhQUOJijIaig5hH1HAOCuR45g08u4TAOBj6k4Zz/iiw7 Ick082XAJ2C57vuHZ4YUBZ9wYJfGcQiCLDtBUDX8n7JBEgd4b45BL4ieuJbi8nGkGwbG g8GL6qeqwu8MWVP+d90A8aTX01Pv6f30uARJ7aFQcb45WUrCNJ0cjHum92e6rLSsJuiU 3ODabI4qu5fT9oGOaC2NbQQ8Y/djtAC5e8uRBmFB9XVQSshiVcZ99zqQFvJoPC+yxyoN OZRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=62d8othJIfgAKm86Avncs/clZTnNTHcuD30Oj5z4NnM=; b=vTif4eDY1DmDpFH5cTNsm1l8jTxNGh9n0P8EapeDEAPEZpJmKAZ0cKu0ixNYNs76Kb a+1h24KVd8JmiqlvU/VaPWWYcS8Wa6IBrb2QpvFtGMSkK3L2bPfutGjIaTNWkfazEFL9 HMZYSbBacEFOgihdVO+8bWkSv8AZfSdY+GFTw0pJD/dAVs5vBq/SMkqeh4SuB/NXEAh1 6VPZq1l+vtUh05e49x1PDN3OupoCsi3sTSw85yuCDYLb+lyFRGZR1HGathyaCk7w/AO5 0no2J3lkmRV6HouQau8QZ8OJ5LMnX9DAMBe7Bduweff5tvjUeJiJdHuOO7zOPDAvkMRt Wxbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=R9UV28Lx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.05.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:05:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 20/51] target/nios2: Create EXCP_SEMIHOST for semi-hosting Date: Wed, 16 Mar 2022 22:05:07 -0700 Message-Id: <20220317050538.924111-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Decode 'break 1' during translation, rather than doing it again during exception processing. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 1 + target/nios2/helper.c | 14 ++++++-------- target/nios2/translate.c | 17 ++++++++++++++++- 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 555972fe6b..d003af5afc 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -156,6 +156,7 @@ FIELD(CR_TLBMISC, EE, 24, 1) /* Exceptions */ #define EXCP_BREAK 0x1000 +#define EXCP_SEMIHOST 0x1001 #define EXCP_RESET 0 #define EXCP_PRESET 1 #define EXCP_IRQ 2 diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 52a49f7ead..eeff032379 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -172,14 +172,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_BREAK: qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc); - /* The semihosting instruction is "break 1". */ - if (semihosting_enabled() && - cpu_ldl_code(env, env->pc) == 0x003da07a) { - qemu_log_mask(CPU_LOG_INT, "Entering semihosting\n"); - env->pc += 4; - do_nios2_semihosting(env); - break; - } if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { env->ctrl[CR_BSTATUS] = env->ctrl[CR_STATUS]; @@ -196,6 +188,12 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->pc = cpu->exception_addr; break; + case EXCP_SEMIHOST: + qemu_log_mask(CPU_LOG_INT, "BREAK semihosting at pc=%x\n", env->pc); + env->pc += 4; + do_nios2_semihosting(env); + break; + default: cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 459e30b338..cfad110186 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -33,6 +33,7 @@ #include "exec/translator.h" #include "qemu/qemu-print.h" #include "exec/gen-icount.h" +#include "semihosting/semihost.h" /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ @@ -686,6 +687,20 @@ static void trap(DisasContext *dc, uint32_t code, uint32_t flags) t_gen_helper_raise_exception(dc, EXCP_TRAP); } +static void gen_break(DisasContext *dc, uint32_t code, uint32_t flags) +{ +#ifndef CONFIG_USER_ONLY + /* The semihosting instruction is "break 1". */ + R_TYPE(instr, code); + if (semihosting_enabled() && instr.imm5 == 1) { + t_gen_helper_raise_exception(dc, EXCP_SEMIHOST); + return; + } +#endif + + t_gen_helper_raise_exception(dc, EXCP_BREAK); +} + static const Nios2Instruction r_type_instructions[] = { INSTRUCTION_ILLEGAL(), INSTRUCTION(eret), /* eret */ @@ -739,7 +754,7 @@ static const Nios2Instruction r_type_instructions[] = { INSTRUCTION(add), /* add */ INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(), - INSTRUCTION_FLG(gen_excp, EXCP_BREAK), /* break */ + INSTRUCTION(gen_break), /* break */ INSTRUCTION_ILLEGAL(), INSTRUCTION(nop), /* nop */ INSTRUCTION_ILLEGAL(), From patchwork Thu Mar 17 05:05:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552244 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp889624mag; Wed, 16 Mar 2022 22:43:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJznFaADZD7n5XI2p9dhpe7aFDQ9VVuUDZ8p1qzF5FV+dcw99rcY4puuMUHn9sSaQL2p1mzS X-Received: by 2002:a05:6214:62b:b0:43b:50eb:3607 with SMTP id a11-20020a056214062b00b0043b50eb3607mr2458078qvx.74.1647495814758; Wed, 16 Mar 2022 22:43:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647495814; cv=none; d=google.com; s=arc-20160816; b=C7DAmlO+k8r1iLtSHiNSLunc96OTXUYURun7OGa3wFhwmE5cFpFn3Mf/K+WgA2KLtj bD70vj2fOltyXdJ6jQt8D+bSn6wz4SoFUcQxgguCRpsQjZjKR4u+atHdcA3AB6BmfJvs S4/H11FceE3ycnGG/GWUH+wLgRUXUq9EO/vlpqvoBgqVmrnKUqdVhMjDAu7PJrcFaGtj +7MqQhiHpi/ySWg1oc83trjZz2ukwmS0v2d2Sy5cM0KS8BVWQWf+RPRUpkjNFo5dkYFZ XrLcojmabNZ3KP5mGS14nSKcV787agT2y6rxUP4JR9SFuL3piQPkygH0Xjhs44++n3T1 D4Gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rza+S9dP6OxTxmW7BN1PpFg5SK23R8f/DSGJ4keNmyI=; b=TPD504kX5XZ3PpnRzSlMrgi0RMYGCAfofNuyG2AcW1fYkBe6alGmwNkcgl/sBDRF6x KS0ZQPsl6nws5EvAKyu4m5v4smOHFgDMaOH+RxHUrw0cNT79wWHnn4hbPsUKWUBndbVM 94M75n0ZtBGRJEzzj5fXb34gHy1wCcsJyHRawPTadTSXVZJ5s8aU+o0ymga1tzYPid0r Ip3Eax93zpfji6g1ZfoCsTVE2YhcvAZoSsOhw16qfm4c16yAdbtmObhXzEaJRoZy57sW Ug1jpM38lfVLFUo5beHhvcgaU1aoiFnWZQ7U61ZYqYRINA1NW4+CcN9uNiUSYGE8yu+H rS9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bpW7YUUP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 21/51] target/nios2: Clean up nios2_cpu_do_interrupt Date: Wed, 16 Mar 2022 22:05:08 -0700 Message-Id: <20220317050538.924111-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out do_exception and do_iic_irq to handle bulk of the interrupt and exception processing. Parameterize the changes required to cpu state. The status.EH bit, which protects some data against double-faults, is only present with the MMU. Several exception cases did not check for status.EH being set, as required. The status.IH bit, which had been set by EXCP_IRQ, is exclusive to the external interrupt controller, which we do not yet implement. The internal interrupt controller, when the MMU is also present, sets the status.EH bit. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/helper.c | 141 +++++++++++++----------------------------- 1 file changed, 44 insertions(+), 97 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index eeff032379..6019e2443b 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -49,6 +49,42 @@ void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, #else /* !CONFIG_USER_ONLY */ +static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break) +{ + CPUNios2State *env = &cpu->env; + CPUState *cs = CPU(cpu); + uint32_t old_status = env->ctrl[CR_STATUS]; + uint32_t new_status = old_status; + + if ((old_status & CR_STATUS_EH) == 0) { + int r_ea = R_EA, cr_es = CR_ESTATUS; + + if (is_break) { + r_ea = R_BA; + cr_es = CR_BSTATUS; + } + env->ctrl[cr_es] = old_status; + env->regs[r_ea] = env->pc + 4; + + if (cpu->mmu_present) { + new_status |= CR_STATUS_EH; + } + } + + new_status &= ~(CR_STATUS_PIE | CR_STATUS_U); + + env->ctrl[CR_STATUS] = new_status; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); + env->pc = exception_addr; +} + +static void do_iic_irq(Nios2CPU *cpu) +{ + do_exception(cpu, cpu->exception_addr, false); +} + void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu = NIOS2_CPU(cs); @@ -56,57 +92,20 @@ void nios2_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_IRQ: - assert(env->ctrl[CR_STATUS] & CR_STATUS_PIE); - qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc); - - env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; - env->ctrl[CR_STATUS] |= CR_STATUS_IH; - env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - - env->regs[R_EA] = env->pc + 4; - env->pc = cpu->exception_addr; + do_iic_irq(cpu); break; case EXCP_TLBD: if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc); - - /* Fast TLB miss */ - /* Variation from the spec. Table 3-35 of the cpu reference shows - * estatus not being changed for TLB miss but this appears to - * be incorrect. */ - env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; - env->ctrl[CR_STATUS] |= CR_STATUS_EH; - env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; - - env->regs[R_EA] = env->pc + 4; - env->pc = cpu->fast_tlb_miss_addr; + do_exception(cpu, cpu->fast_tlb_miss_addr, false); } else { qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc); - - /* Double TLB miss */ - env->ctrl[CR_STATUS] |= CR_STATUS_EH; - env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL; - - env->pc = cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, false); } break; @@ -114,78 +113,28 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TLBW: case EXCP_TLBX: qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc); - - env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; - env->ctrl[CR_STATUS] |= CR_STATUS_EH; - env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; } - - env->regs[R_EA] = env->pc + 4; - env->pc = cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, false); break; case EXCP_SUPERA: case EXCP_SUPERI: case EXCP_SUPERD: qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc); - - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; - env->regs[R_EA] = env->pc + 4; - } - - env->ctrl[CR_STATUS] |= CR_STATUS_EH; - env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - - env->pc = cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, false); break; case EXCP_ILLEGAL: case EXCP_TRAP: qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc); - - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; - env->regs[R_EA] = env->pc + 4; - } - - env->ctrl[CR_STATUS] |= CR_STATUS_EH; - env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - - env->pc = cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, false); break; case EXCP_BREAK: qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc); - - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - env->ctrl[CR_BSTATUS] = env->ctrl[CR_STATUS]; - env->regs[R_BA] = env->pc + 4; - } - - env->ctrl[CR_STATUS] |= CR_STATUS_EH; - env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - - env->pc = cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, true); break; case EXCP_SEMIHOST: @@ -195,9 +144,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) break; default: - cpu_abort(cs, "unhandled exception type=%d\n", - cs->exception_index); - break; + cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index); } } From patchwork Thu Mar 17 05:05:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552225 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp879977mag; Wed, 16 Mar 2022 22:23:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx86wdX4xoDw+2avBovrYUmf+T7VlYPvn/0AupLFEWPJxAgZgkbPiZPsqd0wVTEckisFrnh X-Received: by 2002:a05:620a:1424:b0:67d:2bc6:856b with SMTP id k4-20020a05620a142400b0067d2bc6856bmr1836814qkj.434.1647494596439; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 22/51] target/nios2: Hoist CPU_LOG_INT logging Date: Wed, 16 Mar 2022 22:05:09 -0700 Message-Id: <20220317050538.924111-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Performing this early means that we can merge more cases within the non-logging switch statement. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/helper.c | 58 +++++++++++++++++++++++++++++++++++-------- 1 file changed, 47 insertions(+), 11 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 6019e2443b..285f3aae1d 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -90,20 +90,64 @@ void nios2_cpu_do_interrupt(CPUState *cs) Nios2CPU *cpu = NIOS2_CPU(cs); CPUNios2State *env = &cpu->env; + if (qemu_loglevel_mask(CPU_LOG_INT)) { + const char *name = NULL; + + switch (cs->exception_index) { + case EXCP_IRQ: + name = "interrupt"; + break; + case EXCP_TLBD: + if (env->ctrl[CR_STATUS] & CR_STATUS_EH) { + name = "TLB MISS (double)"; + } else { + name = "TLB MISS (fast)"; + } + break; + case EXCP_TLBR: + case EXCP_TLBW: + case EXCP_TLBX: + name = "TLB PERM"; + break; + case EXCP_SUPERA: + case EXCP_SUPERD: + name = "SUPERVISOR (address)"; + break; + case EXCP_SUPERI: + name = "SUPERVISOR (insn)"; + break; + case EXCP_ILLEGAL: + name = "ILLEGAL insn"; + break; + case EXCP_TRAP: + name = "TRAP insn"; + break; + case EXCP_BREAK: + name = "TRAP insn"; + break; + case EXCP_SEMIHOST: + name = "SEMIHOST insn"; + break; + } + if (name) { + qemu_log("%s at pc=0x%08x\n", name, env->pc); + } else { + qemu_log("Unknown exception %d at pc=0x%08x\n", + cs->exception_index, env->pc); + } + } + switch (cs->exception_index) { case EXCP_IRQ: - qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc); do_iic_irq(cpu); break; case EXCP_TLBD: if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc); env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; do_exception(cpu, cpu->fast_tlb_miss_addr, false); } else { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc); env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL; do_exception(cpu, cpu->exception_addr, false); } @@ -112,7 +156,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TLBR: case EXCP_TLBW: case EXCP_TLBX: - qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc); if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; } @@ -122,23 +165,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_SUPERA: case EXCP_SUPERI: case EXCP_SUPERD: - qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc); - do_exception(cpu, cpu->exception_addr, false); - break; - case EXCP_ILLEGAL: case EXCP_TRAP: - qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc); do_exception(cpu, cpu->exception_addr, false); break; case EXCP_BREAK: - qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc); do_exception(cpu, cpu->exception_addr, true); break; case EXCP_SEMIHOST: - qemu_log_mask(CPU_LOG_INT, "BREAK semihosting at pc=%x\n", env->pc); env->pc += 4; do_nios2_semihosting(env); break; From patchwork Thu Mar 17 05:05:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552214 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp876239mag; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 23/51] target/nios2: Handle EXCP_UNALIGN and EXCP_UALIGND Date: Wed, 16 Mar 2022 22:05:10 -0700 Message-Id: <20220317050538.924111-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These misaligned data and misaligned destination exceptions are defined, but not currently raised. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 285f3aae1d..0392c0ea84 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -119,6 +119,12 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_ILLEGAL: name = "ILLEGAL insn"; break; + case EXCP_UNALIGN: + name = "Misaligned (data)"; + break; + case EXCP_UNALIGND: + name = "Misaligned (destination)"; + break; case EXCP_TRAP: name = "TRAP insn"; break; @@ -167,6 +173,8 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_SUPERD: case EXCP_ILLEGAL: case EXCP_TRAP: + case EXCP_UNALIGN: + case EXCP_UNALIGND: do_exception(cpu, cpu->exception_addr, false); break; From patchwork Thu Mar 17 05:05:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552246 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp893009mag; Wed, 16 Mar 2022 22:50:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyw87ropz3igtEBxhQ5NBx4BuLZhs05vUEmy0/STwDNWTYOWCkcJlOUcTZcAk7yaUUl7EWe X-Received: by 2002:a05:620a:4545:b0:67b:14ce:ba7b with SMTP id u5-20020a05620a454500b0067b14ceba7bmr1917849qkp.200.1647496221446; Wed, 16 Mar 2022 22:50:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647496221; cv=none; d=google.com; s=arc-20160816; b=0U49J9yAZ+W6oxJj6gdV+esGTXErM32mP1KbWMaAiHC6Xl/xWdZpQPNfdM587XGQtv WvXnbmsiYj1QcF0FEZ10oF9X4drESFdnCBfMdhvTbjqOAWlPj8hydnccrWIICw/G6ve2 l7zDjS/xYe13YxwrqxIGpfUVWk/t7fMYQc1ldiJIoZsO096qcSmx6dgYtPluEUFcsGnm JiHG2FxNlP2l0D4QC5+UnRL9Wjz6vdK6D/6kiNFAlXI6EKjboE3c4a6YyJXs5CP+ORG6 P9YQ+jiATWdNxzq0qIgu2OUvCV0GFO8QTSWFvVAMU6YeizWQ7/lSnQ1PuWEqKxJhz18N +xQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kC6IYNjsGbxQ1O1vqjxYEFxpw4YN+TjfQjKfECaeneY=; b=qTotrvEehk772KV7hRtCKBuKzUp5pDYNh0aSDAlj3tgFjFjf7n/JScUMJUM17N7vse l6j3gGBKdoJHrdJyz1Z0x7Rd2mq1QeaH2luOlcsnwQbRo9Y41EftL1wbnVYK7rrx9kJb 3Ba8nMEcC6JHM+I8hQphALo8e0taPCqMhJ5Gru+6L9psFtHk8PPwuE8PNU3afoFEeALW B8loMKSE4VNaPM1vpXtwi+t0FLhyIK6u95wJ+omWeCCPqAUGeLeXA+wcUuCpcsG4pPFT ucrU4/G8Nb9T6kzoF4iUVWcjRr4lGOw+0JyYh5RRdoxIrugp6xn8p7cSxQ0tD78V1zC4 EEvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kJ0Y7HEY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 24/51] target/nios2: Cleanup set of CR_EXCEPTION for do_interrupt Date: Wed, 16 Mar 2022 22:05:11 -0700 Message-Id: <20220317050538.924111-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The register is entirely read-only for software, and we do not implement ECC, so we need not deposit the cause into an existing value; just create a new value from scratch. Furthermore, exception.CAUSE is not written for break exceptions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/helper.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 0392c0ea84..afbafd1fdc 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -74,9 +74,10 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break) new_status &= ~(CR_STATUS_PIE | CR_STATUS_U); env->ctrl[CR_STATUS] = new_status; - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); + if (!is_break) { + env->ctrl[CR_EXCEPTION] = FIELD_DP32(0, CR_EXCEPTION, CAUSE, + cs->exception_index); + } env->pc = exception_addr; } From patchwork Thu Mar 17 05:05:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552223 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp879705mag; Wed, 16 Mar 2022 22:22:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyoTvDOd3gHycVqE1n5+Jwc9X3YNef2NKT91QQaGl3Y59d783l+C9c7veqSK+jA80mXAQzI X-Received: by 2002:a05:622a:205:b0:2e1:cda9:88e9 with SMTP id b5-20020a05622a020500b002e1cda988e9mr2447250qtx.384.1647494558078; Wed, 16 Mar 2022 22:22:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647494558; cv=none; d=google.com; s=arc-20160816; b=fggsjLLdc0uB6uS6l8d7yDOmKl7cg6jNO3WY0+NRB09+rSo0ogHCqi0ycXAYa49SiV rxaXr4LjR2agNAdSwvicEVKnDzb/Ep1Fj4fSX8bZcwuJMKCl57fgfquamOfalElssznt 9sO4Rmzx1YXsk6lIiabJ+SPFAIM2OC8F5qy9pnDcSYXWfVDhbINkHwUx3rskSX7k7+ll FSHTg2VMQ2LY13Dw0Su0LxRfeC5n3SXKNK7cwjmTf8Tc87EUHdLLHQzEE2K8EjpnwkJE TIiZyPfoFu2WHKKciJ2F/vqnQFD4MZ+/D6rkVJXLx5IBZHjtpm3P7hpQ3H4BTI5dd8Xn XMSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EnAEYpcIY00+k1hPlmrXoRht11ltOEwUcRv8uGR7V3g=; b=zsTNGVTtRD+ZGSfyIT7jpQzZRGMbgE9TLVTilivgla2ozryMj908dBhQKjCqBg6KYP FrtMYCifEs5gop+Rr98upMnPE3NMyFZGd/wo6TN5ex8YlMMJLihjvi3IwWZQ6QzhGmgA oBmu4YztZSJLWSMYgc58bCSq4tj5P775/zIaQ03+RTAKOnmVXaLGjlaa5ZSmRvkFRRQW sS/C7hKLqD2htBz6GNBZ/Ir+ptoV0YJ7O43wZG4tawPiQe7AvXijgcDiA8MIhg22HvLO pVvjqa+UPn1xN0AOXyZGDUq7nbia09jKglkSstzLOvpowDSaMS+Bf6PtD01F+Hy+T7uK trPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RJzjZBB+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 25/51] target/nios2: Clean up handling of tlbmisc in do_exception Date: Wed, 16 Mar 2022 22:05:12 -0700 Message-Id: <20220317050538.924111-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1030 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The 4 lower bits, D, PERM, BAD, DBL, are unconditionally set on any exception with EH=0, or so says Table 42 (Processor Status After Taking Exception). We currently do not set PERM or BAD at all, and only set/clear DBL for tlb miss, and do not clear DBL for any other exception. It is a bit confusing to set D in tlb_fill and the rest during do_interrupt, so move the setting of D to do_interrupt as well. To do this, split EXP_TLBD into two cases, EXCP_TLB_X and EXCP_TLB_D, which allows us to distinguish them during do_interrupt. Choose a value for EXCP_TLB_D such that when truncated it produces the correct value for exception.CAUSE. Rename EXCP_TLB[RWX] to EXCP_PERM_[RWX], to emphasize that the exception is permissions related. Rename EXCP_SUPER[AD] to EXCP_SUPERA_[DX] to emphasize that they are both "supervisor address" exceptions, data and execute. Retain the setting of tlbmisc.WE for the fast-tlb-miss path, as it is being relied upon, but remove it from the permission path. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 13 +++--- target/nios2/helper.c | 102 +++++++++++++++++++++++++++++------------- 2 files changed, 77 insertions(+), 38 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index d003af5afc..c925cdd8e3 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -166,13 +166,14 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define EXCP_UNALIGN 6 #define EXCP_UNALIGND 7 #define EXCP_DIV 8 -#define EXCP_SUPERA 9 +#define EXCP_SUPERA_X 9 #define EXCP_SUPERI 10 -#define EXCP_SUPERD 11 -#define EXCP_TLBD 12 -#define EXCP_TLBX 13 -#define EXCP_TLBR 14 -#define EXCP_TLBW 15 +#define EXCP_SUPERA_D 11 +#define EXCP_TLB_X 12 +#define EXCP_TLB_D (0x1000 | EXCP_TLB_X) +#define EXCP_PERM_X 13 +#define EXCP_PERM_R 14 +#define EXCP_PERM_W 15 #define EXCP_MPUI 16 #define EXCP_MPUD 17 diff --git a/target/nios2/helper.c b/target/nios2/helper.c index afbafd1fdc..8b69918ba3 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -49,7 +49,8 @@ void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, #else /* !CONFIG_USER_ONLY */ -static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break) +static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, + uint32_t tlbmisc_set, bool is_break) { CPUNios2State *env = &cpu->env; CPUState *cs = CPU(cpu); @@ -68,6 +69,16 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break) if (cpu->mmu_present) { new_status |= CR_STATUS_EH; + + /* + * There are 4 bits that are always written. + * Explicitly clear them, to be set via the argument. + */ + env->ctrl[CR_TLBMISC] &= ~(CR_TLBMISC_D | + CR_TLBMISC_PERM | + CR_TLBMISC_BAD | + CR_TLBMISC_DBL); + env->ctrl[CR_TLBMISC] |= tlbmisc_set; } } @@ -83,13 +94,14 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break) static void do_iic_irq(Nios2CPU *cpu) { - do_exception(cpu, cpu->exception_addr, false); + do_exception(cpu, cpu->exception_addr, 0, false); } void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu = NIOS2_CPU(cs); CPUNios2State *env = &cpu->env; + uint32_t tlbmisc_set = 0; if (qemu_loglevel_mask(CPU_LOG_INT)) { const char *name = NULL; @@ -98,20 +110,21 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_IRQ: name = "interrupt"; break; - case EXCP_TLBD: + case EXCP_TLB_X: + case EXCP_TLB_D: if (env->ctrl[CR_STATUS] & CR_STATUS_EH) { name = "TLB MISS (double)"; } else { name = "TLB MISS (fast)"; } break; - case EXCP_TLBR: - case EXCP_TLBW: - case EXCP_TLBX: + case EXCP_PERM_R: + case EXCP_PERM_W: + case EXCP_PERM_X: name = "TLB PERM"; break; - case EXCP_SUPERA: - case EXCP_SUPERD: + case EXCP_SUPERA_X: + case EXCP_SUPERA_D: name = "SUPERVISOR (address)"; break; case EXCP_SUPERI: @@ -149,38 +162,60 @@ void nios2_cpu_do_interrupt(CPUState *cs) do_iic_irq(cpu); break; - case EXCP_TLBD: - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; - do_exception(cpu, cpu->fast_tlb_miss_addr, false); + case EXCP_TLB_D: + tlbmisc_set = CR_TLBMISC_D; + /* fall through */ + case EXCP_TLB_X: + if (env->ctrl[CR_STATUS] & CR_STATUS_EH) { + tlbmisc_set |= CR_TLBMISC_DBL; + /* + * Normally, we don't write to tlbmisc unless !EH, + * so do it manually for the double-tlb miss exception. + */ + env->ctrl[CR_TLBMISC] &= ~(CR_TLBMISC_D | + CR_TLBMISC_PERM | + CR_TLBMISC_BAD); + env->ctrl[CR_TLBMISC] |= tlbmisc_set; + do_exception(cpu, cpu->exception_addr, 0, false); } else { - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL; - do_exception(cpu, cpu->exception_addr, false); + /* + * ??? Implicitly setting tlbmisc.WE for the fast-tlb-miss + * handler appears to be out of spec. But, the linux kernel + * handler relies on it, writing to tlbacc without first + * setting tlbmisc.WE. + */ + tlbmisc_set |= CR_TLBMISC_WE; + do_exception(cpu, cpu->fast_tlb_miss_addr, tlbmisc_set, false); } break; - case EXCP_TLBR: - case EXCP_TLBW: - case EXCP_TLBX: - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; - } - do_exception(cpu, cpu->exception_addr, false); + case EXCP_PERM_R: + case EXCP_PERM_W: + tlbmisc_set = CR_TLBMISC_D; + /* fall through */ + case EXCP_PERM_X: + tlbmisc_set |= CR_TLBMISC_PERM; + do_exception(cpu, cpu->exception_addr, tlbmisc_set, false); + break; + + case EXCP_SUPERA_D: + case EXCP_UNALIGN: + tlbmisc_set = CR_TLBMISC_D; + /* fall through */ + case EXCP_SUPERA_X: + case EXCP_UNALIGND: + tlbmisc_set |= CR_TLBMISC_BAD; + do_exception(cpu, cpu->exception_addr, tlbmisc_set, false); break; - case EXCP_SUPERA: case EXCP_SUPERI: - case EXCP_SUPERD: case EXCP_ILLEGAL: case EXCP_TRAP: - case EXCP_UNALIGN: - case EXCP_UNALIGND: - do_exception(cpu, cpu->exception_addr, false); + do_exception(cpu, cpu->exception_addr, 0, false); break; case EXCP_BREAK: - do_exception(cpu, cpu->exception_addr, true); + do_exception(cpu, cpu->exception_addr, 0, true); break; case EXCP_SEMIHOST: @@ -235,7 +270,7 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, { Nios2CPU *cpu = NIOS2_CPU(cs); CPUNios2State *env = &cpu->env; - unsigned int excp = EXCP_TLBD; + unsigned int excp; target_ulong vaddr, paddr; Nios2MMULookup lu; unsigned int hit; @@ -262,7 +297,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (probe) { return false; } - cs->exception_index = EXCP_SUPERA; + cs->exception_index = (access_type == MMU_INST_FETCH + ? EXCP_SUPERA_X : EXCP_SUPERA_D); env->ctrl[CR_BADADDR] = address; cpu_loop_exit_restore(cs, retaddr); } @@ -283,8 +319,10 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } /* Permission violation */ - excp = (access_type == MMU_DATA_LOAD ? EXCP_TLBR : - access_type == MMU_DATA_STORE ? EXCP_TLBW : EXCP_TLBX); + excp = (access_type == MMU_DATA_LOAD ? EXCP_PERM_R : + access_type == MMU_DATA_STORE ? EXCP_PERM_W : EXCP_PERM_X); + } else { + excp = (access_type == MMU_INST_FETCH ? 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 26/51] target/nios2: Prevent writes to read-only or reserved control fields Date: Wed, 16 Mar 2022 22:05:13 -0700 Message-Id: <20220317050538.924111-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create an array of masks which detail the writable and readonly bits for each control register. Apply them when writing to control registers, including the write to status during eret. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 13 +++++ target/nios2/cpu.c | 100 +++++++++++++++++++++++++++++++++------ target/nios2/op_helper.c | 9 ++++ target/nios2/translate.c | 80 ++++++++++++++++++++++++------- 4 files changed, 171 insertions(+), 31 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index c925cdd8e3..410e76ccbb 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -190,6 +190,11 @@ struct CPUArchState { int error_code; }; +typedef struct { + uint32_t writable; + uint32_t readonly; +} ControlRegState; + /** * Nios2CPU: * @env: #CPUNios2State @@ -213,9 +218,17 @@ struct ArchCPU { uint32_t reset_addr; uint32_t exception_addr; uint32_t fast_tlb_miss_addr; + + /* Bits within each control register which are reserved or readonly. */ + ControlRegState cr_state[NUM_CR_REGS]; }; +static inline bool nios2_cr_reserved(const ControlRegState *s) +{ + return (s->writable | s->readonly) == 0; +} + void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); void dump_mmu(CPUNios2State *env); diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 182ddcc18f..8189937857 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -107,6 +107,64 @@ static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model) return object_class_by_name(TYPE_NIOS2_CPU); } +static void realize_cr_status(CPUState *cs) +{ + Nios2CPU *cpu = NIOS2_CPU(cs); + + /* Begin with all fields of all registers are reserved. */ + memset(cpu->cr_state, 0, sizeof(cpu->cr_state)); + + /* + * The combination of writable and readonly is the set of all + * non-reserved fields. We apply writable as a mask to bits, + * and merge in existing readonly bits, before storing. + */ +#define WR_REG(C) cpu->cr_state[C].writable = -1 +#define RO_REG(C) cpu->cr_state[C].readonly = -1 +#define WR_FIELD(C, F) cpu->cr_state[C].writable |= R_##C##_##F##_MASK +#define RO_FIELD(C, F) cpu->cr_state[C].readonly |= R_##C##_##F##_MASK + + WR_FIELD(CR_STATUS, PIE); + WR_REG(CR_ESTATUS); + WR_REG(CR_BSTATUS); + RO_REG(CR_CPUID); + RO_REG(CR_EXCEPTION); + WR_REG(CR_BADADDR); + + /* TODO: These control registers are not present with the EIC. */ + WR_REG(CR_IENABLE); + RO_REG(CR_IPENDING); + + if (cpu->mmu_present) { + WR_FIELD(CR_STATUS, U); + WR_FIELD(CR_STATUS, EH); + + WR_FIELD(CR_PTEADDR, VPN); + WR_FIELD(CR_PTEADDR, PTBASE); + + RO_FIELD(CR_TLBMISC, D); + RO_FIELD(CR_TLBMISC, PERM); + RO_FIELD(CR_TLBMISC, BAD); + RO_FIELD(CR_TLBMISC, DBL); + WR_FIELD(CR_TLBMISC, PID); + WR_FIELD(CR_TLBMISC, WE); + WR_FIELD(CR_TLBMISC, RD); + WR_FIELD(CR_TLBMISC, WAY); + + WR_REG(CR_TLBACC); + } + + /* + * TODO: ECC (config, eccinj) and MPU (config, mpubase, mpuacc) are + * unimplemented, so their corresponding control regs remain reserved. + */ + +#undef WR_REG +#undef RO_REG +#undef WR_FIELD +#undef RO_FIELD +} + static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -119,6 +177,7 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) return; } + realize_cr_status(cs); qemu_init_vcpu(cs); cpu_reset(cs); @@ -152,23 +211,26 @@ static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { Nios2CPU *cpu = NIOS2_CPU(cs); - CPUClass *cc = CPU_GET_CLASS(cs); CPUNios2State *env = &cpu->env; + uint32_t val; - if (n > cc->gdb_num_core_regs) { + if (n < 32) { /* GP regs */ + val = env->regs[n]; + } else if (n == 32) { /* PC */ + val = env->pc; + } else if (n < 49) { /* Status regs */ + unsigned cr = n - 33; + if (nios2_cr_reserved(&cpu->cr_state[cr])) { + val = 0; + } else { + val = env->ctrl[n - 33]; + } + } else { + /* Invalid regs */ return 0; } - if (n < 32) { /* GP regs */ - return gdb_get_reg32(mem_buf, env->regs[n]); - } else if (n == 32) { /* PC */ - return gdb_get_reg32(mem_buf, env->pc); - } else if (n < 49) { /* Status regs */ - return gdb_get_reg32(mem_buf, env->ctrl[n - 33]); - } - - /* Invalid regs */ - return 0; + return gdb_get_reg32(mem_buf, val); } static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) @@ -176,17 +238,25 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) Nios2CPU *cpu = NIOS2_CPU(cs); CPUClass *cc = CPU_GET_CLASS(cs); CPUNios2State *env = &cpu->env; + uint32_t val; if (n > cc->gdb_num_core_regs) { return 0; } + val = ldl_p(mem_buf); if (n < 32) { /* GP regs */ - env->regs[n] = ldl_p(mem_buf); + env->regs[n] = val; } else if (n == 32) { /* PC */ - env->pc = ldl_p(mem_buf); + env->pc = val; } else if (n < 49) { /* Status regs */ - env->ctrl[n - 33] = ldl_p(mem_buf); + unsigned cr = n - 33; + /* ??? Maybe allow the debugger to write to readonly fields. */ + val &= cpu->cr_state[cr].writable; + val |= cpu->cr_state[cr].readonly & env->ctrl[cr]; + env->ctrl[cr] = val; + } else { + g_assert_not_reached(); } return 4; diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 08ed3b4598..c56fc15283 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -34,6 +34,15 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index) #ifndef CONFIG_USER_ONLY void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) { + Nios2CPU *cpu = env_archcpu(env); + + /* + * Both estatus and bstatus have no constraints on write; + * do not allow reserved fields in status to be set. + */ + new_status &= (cpu->cr_state[CR_STATUS].writable | + cpu->cr_state[CR_STATUS].readonly); + env->ctrl[CR_STATUS] = new_status; env->pc = new_pc; cpu_loop_exit(env_cpu(env)); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index cfad110186..21dc6947cf 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -102,6 +102,7 @@ typedef struct DisasContext { TCGv_i32 zero; target_ulong pc; int mem_idx; + const ControlRegState *cr_state; } DisasContext; static TCGv cpu_R[NUM_GP_REGS]; @@ -471,17 +472,26 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags) /* rC <- ctlN */ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) { - R_TYPE(instr, code); - TCGv t1, t2; - if (!gen_check_supervisor(dc)) { return; } +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + R_TYPE(instr, code); + TCGv t1, t2; + if (unlikely(instr.c == R_ZERO)) { return; } + /* Reserved registers read as zero. */ + if (nios2_cr_reserved(&dc->cr_state[instr.imm5])) { + tcg_gen_movi_tl(cpu_R[instr.c], 0); + return; + } + switch (instr.imm5) { case CR_IPENDING: /* @@ -505,6 +515,7 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) offsetof(CPUNios2State, ctrl[instr.imm5])); break; } +#endif } /* ctlN <- rA */ @@ -519,6 +530,14 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) #else R_TYPE(instr, code); TCGv v = load_gpr(dc, instr.a); + uint32_t ofs = offsetof(CPUNios2State, ctrl[instr.imm5]); + uint32_t wr = dc->cr_state[instr.imm5].writable; + uint32_t ro = dc->cr_state[instr.imm5].readonly; + + /* Skip reserved or readonly registers. */ + if (wr == 0) { + return; + } switch (instr.imm5) { case CR_PTEADDR: @@ -530,17 +549,35 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) case CR_TLBMISC: gen_helper_mmu_write_tlbmisc(cpu_env, v); break; - case CR_IPENDING: - /* ipending is read only, writes ignored. */ - break; case CR_STATUS: case CR_IENABLE: /* If interrupts were enabled using WRCTL, trigger them. */ dc->base.is_jmp = DISAS_UPDATE; /* fall through */ default: - tcg_gen_st_tl(v, cpu_env, - offsetof(CPUNios2State, ctrl[instr.imm5])); + if (wr == -1) { + /* The register is entirely writable. */ + tcg_gen_st_tl(v, cpu_env, ofs); + } else { + /* + * The register is partially read-only or reserved: + * merge the value. + */ + TCGv n = tcg_temp_new(); + + tcg_gen_andi_tl(n, v, wr); + + if (ro != 0) { + TCGv o = tcg_temp_new(); + tcg_gen_ld_tl(o, cpu_env, ofs); + tcg_gen_andi_tl(o, o, ro); + tcg_gen_or_tl(n, n, o); + tcg_temp_free(o); + } + + tcg_gen_st_tl(n, cpu_env, ofs); + tcg_temp_free(n); + } break; } #endif @@ -818,9 +855,11 @@ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUNios2State *env = cs->env_ptr; + Nios2CPU *cpu = env_archcpu(env); int page_insns; dc->mem_idx = cpu_mmu_index(env, false); + dc->cr_state = cpu->cr_state; /* Bound the number of insns to execute to those left on the page. */ page_insns = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; @@ -931,16 +970,25 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) } #if !defined(CONFIG_USER_ONLY) - for (i = 0; i < NUM_CR_REGS; i++) { - qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]); - if ((i + 1) % 4 == 0) { - qemu_fprintf(f, "\n"); + int j; + + for (i = j = 0; i < NUM_CR_REGS; i++) { + if (!nios2_cr_reserved(&cpu->cr_state[i])) { + qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]); + if (++j % 4 == 0) { + qemu_fprintf(f, "\n"); + } } } - qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n", - env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, - FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID), - env->mmu.tlbacc_wr); + if (j % 4 != 0) { + qemu_fprintf(f, "\n"); + } + if (cpu->mmu_present) { + qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n", + env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, + FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID), + env->mmu.tlbacc_wr); + } #endif qemu_fprintf(f, "\n\n"); } From patchwork Thu Mar 17 05:05:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552218 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp877569mag; Wed, 16 Mar 2022 22:17:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzmSuN9oek1gK9ZqykW4+67H0HDJj/1pwih+qbcTy4gIQOc0MB9qctlTSiT1oBviYuS1pPd X-Received: by 2002:ac8:5d94:0:b0:2e1:ce44:5041 with SMTP id d20-20020ac85d94000000b002e1ce445041mr2432171qtx.356.1647494257023; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 27/51] target/nios2: Implement cpuid Date: Wed, 16 Mar 2022 22:05:14 -0700 Message-Id: <20220317050538.924111-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1033 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Copy the existing cpu_index into the space reserved for CR_CPUID. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 8189937857..2f1f5e35aa 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -168,6 +168,7 @@ static void realize_cr_status(CPUState *cs) static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); + Nios2CPU *cpu = NIOS2_CPU(cs); Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev); Error *local_err = NULL; @@ -181,6 +182,9 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); cpu_reset(cs); + /* We have reserved storage for cpuid; might as well use it. */ + cpu->env.ctrl[CR_CPUID] = cs->cpu_index; + ncc->parent_realize(dev, errp); } From patchwork Thu Mar 17 05:05:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552226 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp880059mag; Wed, 16 Mar 2022 22:23:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzmMpRw5uUFpz4DhHau+LTwnp7awYma3EKUBfYDfALdC2sg/jC1QIImR0vw2uVxDDvoERG8 X-Received: by 2002:a37:bc86:0:b0:663:814a:7788 with SMTP id m128-20020a37bc86000000b00663814a7788mr1815318qkf.349.1647494607643; Wed, 16 Mar 2022 22:23:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647494607; cv=none; d=google.com; s=arc-20160816; b=ZIMDYpRgJVG9QR5wwCAeE8hI1k4HO56NjuhixW8vyDnk+2jDM5gXUpNzykWJBU6fus qkXLSMsEjnRGh0JgK9dIxCD3kk4/y0sYVwFcxXXLsEKV55hnuEJ5xvdz4SM72Lu71l+o 8xTcQtWpV7PzRpcneIxGN0vLV7wsUUADmWGTtZV0I42I5GrBePnHiS6rPWRlfRLFpfPl oimEEzN0FDenn/1sqRa2vywP5iO0QzgqP4jPUh1wM49qvuS760NVVrdaTaKFR7rMJ1CW kA3xccastpt2baLj8WmIeQWVt6x1ygJCz/nkV0xwBAbp+HxCC7/0Bx2fTsWGYhj4tZqB CfZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=c1gnsNdU+y7p35LQc37uO6M9rdhacpyrBQDCJlMzk6g=; b=VVK7fhbCV9Kqau/q/mKbE+qliSgchm5CM+loB5g0I0adnnAZnWBYtG1/TIZBWV1FDa v9TbakADpu8N/KSDx3sOr/L7arTNrs+EzyNsQBqbbfIacy0aGWNM9aIgmsUIrDaKnYaz 5yms8JxCXHgW2Xo8ZX6maRb1FaOjp19Q9yJ+6ElCimEWd0/dc/yT09Q+Q7bEdjYUT5oz yNKl+I+qPbZGdndonOLtLvNb212xeTEikPXUGBlRtDoutyxtBbSwKE8GWXLHOJcXjDj/ ANXbkG2ZQ9/J13iIxWY1+V3Xw7UjW0nHTYEVJsBw2PPGFzbtJ/FpFAVtKBz/TNObVH/w +8Sg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lZQiZ3t+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 28/51] target/nios2: Implement CR_STATUS.RSIE Date: Wed, 16 Mar 2022 22:05:15 -0700 Message-Id: <20220317050538.924111-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1033 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Without EIC, this bit is RES1. So set the bit at reset, and add it to the readonly fields of CR_STATUS. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 2f1f5e35aa..9fc4fa7725 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -59,9 +59,9 @@ static void nios2_cpu_reset(DeviceState *dev) #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ - env->ctrl[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE; + env->ctrl[CR_STATUS] = CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE; #else - env->ctrl[CR_STATUS] = 0; + env->ctrl[CR_STATUS] = CR_STATUS_RSIE; #endif } @@ -132,6 +132,7 @@ static void realize_cr_status(CPUState *cs) WR_REG(CR_BADADDR); /* TODO: These control registers are not present with the EIC. */ + RO_FIELD(CR_STATUS, RSIE); WR_REG(CR_IENABLE); RO_REG(CR_IPENDING); From patchwork Thu Mar 17 05:05:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552222 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp878651mag; Wed, 16 Mar 2022 22:20:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxB0QCxANttYnnUbGXegAFhQ99IJi0DZ8SS1mOjxabhiYCDWyUyktemd+iN/0xxbvojIKHb X-Received: by 2002:ac8:59d5:0:b0:2e0:775e:ed9e with SMTP id f21-20020ac859d5000000b002e0775eed9emr2422181qtf.419.1647494416959; Wed, 16 Mar 2022 22:20:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647494416; cv=none; d=google.com; s=arc-20160816; b=N7y2tqEL8CUfwXp9iFdvDgU38J3Wl0ZI/NHa7BWfo4Pkr3P33k3FUXm79pxmg5EjHE F+/B9k1zkLmM4S9dkYhz0ft+nkbo2yEPl1jA2VeGeoArAWIPJvH9hkiM+LZcLow7VgYW TqirGzFmyRcCkCN8/ZUs5pNmFEi9iDgbQNMQFKY6hmU1v1fte7RFBkY39ffx8QTrhwRZ seI7V4D6HATI4c/vuLKvvf9YsXTT5r+6OP+pkM4royT515r1jFkVH4um4tdDJijWH6o+ iz8eN4qlkRPw4xDGS1HteqcI9bSEf3FCmYSckJKORYGn0nkOXiVGgQdRr3pwc6aUqPKP Gi/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1c7FByY8RueDOU9kVxB+CSgBA4nxhG+Xofet2o37MpM=; b=NoZ7Xq1zrQreLdtYU9zijC77u259RGSV+dGxyjqtGx+HlaUm+oIYpiSTNcLGwSCbJM gXOEqWF7ffjbqpEEsOCzPWuY+KwdZh3l2ke4m5XxmMLgmWuQzYQ6UxLFbuDnMv48+Cze hggvHv6Au78MyEvaZNQorrgX2MERMiVXi/08LZpdalqMMysHje5JTp+3FgDKOcjVyHCN o0cV4XOkP5q7Qf/EhhTrxmriLidYrEsI+DiwyQntFwDH66quK4H+8eZNRd67gVsQTVyQ Cm7rwbElrjWQ9bVZ3RuI20cIGkVSkoX36AhCkf7eJtVzcHL6mKdAPFT4JuMVOdFFWDbY x/Yg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=I+JIv442; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 29/51] target/nios2: Remove CPU_INTERRUPT_NMI Date: Wed, 16 Mar 2022 22:05:16 -0700 Message-Id: <20220317050538.924111-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::435 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This interrupt bit is never set, so testing it in nios2_cpu_has_work is pointless. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 2 -- target/nios2/cpu.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 410e76ccbb..161f8efe82 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -177,8 +177,6 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define EXCP_MPUI 16 #define EXCP_MPUD 17 -#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 - struct CPUArchState { uint32_t regs[NUM_GP_REGS]; uint32_t ctrl[NUM_CR_REGS]; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 9fc4fa7725..e041aa41d0 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -36,7 +36,7 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) static bool nios2_cpu_has_work(CPUState *cs) { - return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); + return cs->interrupt_request & CPU_INTERRUPT_HARD; } static void nios2_cpu_reset(DeviceState *dev) From patchwork Thu Mar 17 05:05:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552227 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp881352mag; Wed, 16 Mar 2022 22:26:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzANnl7NR5CYOZnkx19maQKN+ns9kQMBRspXo42FH3cdnSF+6O95OpFFN2tD5t8KiSr4rDH X-Received: by 2002:a05:6214:f0d:b0:435:7bdb:ce23 with SMTP id gw13-20020a0562140f0d00b004357bdbce23mr2250052qvb.88.1647494786259; Wed, 16 Mar 2022 22:26:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647494786; cv=none; d=google.com; s=arc-20160816; b=Z3aLkxpCdaK9irBS5P4SgtR70KGG6G+sBFjp0RBOJ2fnakrag3YTIwYcZhzqwO6/Hc xfvdVDh7Sy1whIAgM7HQ2EfzzHIvxmu70vqJrFOkrg9pUyhN8bw9yMCsWP3Qv9xnSl77 Fspi4k1iOFZWq1Q3zUx4rI0OERoA+EsFiFh7sGnzRwN+o9Qe8XltqWhcc2/nCqFBnweu YEe0gIIE/BUOGx2DwOhltSEB2+kNPZN+ccPKWeAxwvt+uVEVCfuIyuvV/Ip60Fnqu7P5 WCW4VSS5TpHy/i2/GqlIhLgk6Ok852eN2r1utu+OkKJJT60A1eaOuoVzva0H4Xl1G2n9 tDtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wzVt0A8IleUfz6PFweqvWR5Y/gzEkWSlkCYt5DnHYks=; b=ue1WYEZg+mcFBFty6L2i+PgIzMqOoH7+CE0Fvq8DWBqFxp7SKfOFgh49TIZcC6rePV 05QHzHS3PBA/l42qrb9FuRjYAbV+WVNLrzqixZGTaVzayBnBhEYdI9n1E09vsU/3K7GH 8oNLq1SGM7i3BEtAnnEbmGTK/pvrsRMYLkL+EpAjoUFmlNJx7xCP2t4nWobAtysevyUj EuOYLso1ME5VkT+sN1r8nw9mdEt9Evjr/Sg/yXvntjiZ7/NS13QVZWwuwommWB2BeNIe PgKCiJpLPUVpkoRK4YGsSz6SUEIYkRQ4PLmxxrpoT3JP83Vh42bzDj5TsvhkMQwB4VmT D2pg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=f+LHTyyA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 30/51] target/nios2: Support division error exception Date: Wed, 16 Mar 2022 22:05:17 -0700 Message-Id: <20220317050538.924111-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Division may (optionally) raise a division exception. Since the linux kernel has been prepared for this for some time, enable it by default. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 2 ++ target/nios2/helper.h | 2 ++ linux-user/nios2/cpu_loop.c | 4 +++ target/nios2/cpu.c | 1 + target/nios2/helper.c | 4 +++ target/nios2/op_helper.c | 29 ++++++++++++++++++ target/nios2/translate.c | 60 +++++++++++++------------------------ 7 files changed, 62 insertions(+), 40 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 161f8efe82..95079c186c 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -207,7 +207,9 @@ struct ArchCPU { CPUNegativeOffsetState neg; CPUNios2State env; + bool diverr_present; bool mmu_present; + uint32_t pid_num_bits; uint32_t tlb_num_ways; uint32_t tlb_num_entries; diff --git a/target/nios2/helper.h b/target/nios2/helper.h index 525b6b685b..6f5ec60b0d 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -19,6 +19,8 @@ */ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) +DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, s32, env, s32, s32) +DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) #if !defined(CONFIG_USER_ONLY) DEF_HELPER_3(eret, noreturn, env, i32, i32) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index fa234cb2af..ea364b7d1f 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -39,6 +39,10 @@ void cpu_loop(CPUNios2State *env) /* just indicate that signals should be handled asap */ break; + case EXCP_DIV: + force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); + break; + case EXCP_TRAP: switch (env->error_code) { case 0: diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e041aa41d0..07306efc35 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -268,6 +268,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } static Property nios2_properties[] = { + DEFINE_PROP_BOOL("diverr_present", Nios2CPU, diverr_present, true), DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true), /* ALTR,pid-num-bits */ DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8), diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 8b69918ba3..460032adc0 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -139,6 +139,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_UNALIGND: name = "Misaligned (destination)"; break; + case EXCP_DIV: + name = "DIV error"; + break; case EXCP_TRAP: name = "TRAP insn"; break; @@ -210,6 +213,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_SUPERI: case EXCP_ILLEGAL: + case EXCP_DIV: case EXCP_TRAP: do_exception(cpu, cpu->exception_addr, 0, false); break; diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index c56fc15283..c93b66c9aa 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -31,6 +31,35 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index) cpu_loop_exit(cs); } +static void maybe_raise_div(CPUNios2State *env, uintptr_t ra) +{ + Nios2CPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); + + if (cpu->diverr_present) { + cs->exception_index = EXCP_DIV; + cpu_loop_exit_restore(cs, ra); + } +} + +int32_t helper_divs(CPUNios2State *env, int32_t num, int32_t den) +{ + if (unlikely(den == 0) || unlikely(den == -1 && num == INT32_MIN)) { + maybe_raise_div(env, GETPC()); + return num; /* undefined */ + } + return num / den; +} + +uint32_t helper_divu(CPUNios2State *env, uint32_t num, uint32_t den) +{ + if (unlikely(den == 0)) { + maybe_raise_div(env, GETPC()); + return num; /* undefined */ + } + return num / den; +} + #ifndef CONFIG_USER_ONLY void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) { diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 21dc6947cf..c8fb05a9cb 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -654,59 +654,39 @@ gen_r_shift_s(ror, rotr_tl) static void divs(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); + TCGv dest; - /* Stores into R_ZERO are ignored */ - if (unlikely(instr.c == R_ZERO)) { - return; + if (instr.c == R_ZERO) { + dest = tcg_temp_new(); + } else { + dest = cpu_R[instr.c]; } - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); - TCGv t2 = tcg_temp_new(); - TCGv t3 = tcg_temp_new(); + gen_helper_divs(dest, cpu_env, + load_gpr(dc, instr.a), load_gpr(dc, instr.b)); - tcg_gen_ext32s_tl(t0, load_gpr(dc, instr.a)); - tcg_gen_ext32s_tl(t1, load_gpr(dc, instr.b)); - tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); - tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); - tcg_gen_and_tl(t2, t2, t3); - tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); - tcg_gen_or_tl(t2, t2, t3); - tcg_gen_movi_tl(t3, 0); - tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); - tcg_gen_div_tl(cpu_R[instr.c], t0, t1); - tcg_gen_ext32s_tl(cpu_R[instr.c], cpu_R[instr.c]); - - tcg_temp_free(t3); - tcg_temp_free(t2); - tcg_temp_free(t1); - tcg_temp_free(t0); + if (instr.c == R_ZERO) { + tcg_temp_free(dest); + } } static void divu(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); + TCGv dest; - /* Stores into R_ZERO are ignored */ - if (unlikely(instr.c == R_ZERO)) { - return; + if (instr.c == R_ZERO) { + dest = tcg_temp_new(); + } else { + dest = cpu_R[instr.c]; } - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); - TCGv t2 = tcg_const_tl(0); - TCGv t3 = tcg_const_tl(1); + gen_helper_divu(dest, cpu_env, + load_gpr(dc, instr.a), load_gpr(dc, instr.b)); - tcg_gen_ext32u_tl(t0, load_gpr(dc, instr.a)); - tcg_gen_ext32u_tl(t1, load_gpr(dc, instr.b)); - tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); - tcg_gen_divu_tl(cpu_R[instr.c], t0, t1); - tcg_gen_ext32s_tl(cpu_R[instr.c], cpu_R[instr.c]); - - tcg_temp_free(t3); - tcg_temp_free(t2); - tcg_temp_free(t1); - tcg_temp_free(t0); + if (instr.c == R_ZERO) { + tcg_temp_free(dest); + } } static void trap(DisasContext *dc, uint32_t code, uint32_t flags) From patchwork Thu Mar 17 05:05:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552229 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp881849mag; Wed, 16 Mar 2022 22:27:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw/5rrCLhlEfzrrlCI4bSHiESFdgC6v9JgxiFP9WNLaSSPn1wdFxL8FpDWITBJvrvbEvO3I X-Received: by 2002:a37:4550:0:b0:473:b21a:5c90 with SMTP id s77-20020a374550000000b00473b21a5c90mr1787180qka.158.1647494853557; Wed, 16 Mar 2022 22:27:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647494853; cv=none; d=google.com; s=arc-20160816; b=mPHEWQVnfyI55m/ZmUyaEnLBNAJoLZpS+B9767WqthVXF4Dzj2gAG2SM2suRlWaTdC c7m6YcCd1v92mOVZ6SQH5UsV0DQRu+D7z8qq7apocVB3kGGr7OA/Ao807Ua8CNoEYGzg ql/rwrHQlQ6lX1olEKfPvALHbW8AFYQw1DcaIht1o/c4hEgB+/aX2MTYh1XcHOciG4do vmF7dCJX6VZTCxTLyeBmbk3KAd+q44QkR6C2ABwi6xXwtKyQBg/B8NObIgMEZnYJYbd+ Vif+F0VEljDGCwewPJhugGiyikkS+n7Sif0UN7sMrUcN0QpG5GracxmfdXTVOJORc6Wn bihQ== ARC-Message-Signature: i=1; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 31/51] target/nios2: Use tcg_constant_tl Date: Wed, 16 Mar 2022 22:05:18 -0700 Message-Id: <20220317050538.924111-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::535 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Replace current uses of tcg_const_tl, and remove the frees. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/translate.c | 30 ++++++------------------------ 1 file changed, 6 insertions(+), 24 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index c8fb05a9cb..4ad47bb966 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -99,7 +99,6 @@ typedef struct DisasContext { DisasContextBase base; - TCGv_i32 zero; target_ulong pc; int mem_idx; const ControlRegState *cr_state; @@ -125,31 +124,20 @@ static uint8_t get_opxcode(uint32_t code) return instr.opx; } -static TCGv load_zero(DisasContext *dc) +static TCGv load_gpr(DisasContext *dc, unsigned reg) { - if (!dc->zero) { - dc->zero = tcg_const_i32(0); - } - return dc->zero; -} - -static TCGv load_gpr(DisasContext *dc, uint8_t reg) -{ - if (likely(reg != R_ZERO)) { - return cpu_R[reg]; - } else { - return load_zero(dc); + assert(reg < NUM_GP_REGS); + if (unlikely(reg == R_ZERO)) { + return tcg_constant_tl(0); } + return cpu_R[reg]; } static void t_gen_helper_raise_exception(DisasContext *dc, uint32_t index) { - TCGv_i32 tmp = tcg_const_i32(index); - tcg_gen_movi_tl(cpu_pc, dc->pc); - gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(index)); dc->base.is_jmp = DISAS_NORETURN; } @@ -876,14 +864,8 @@ static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) return; } - dc->zero = NULL; - instr = &i_type_instructions[op]; instr->handler(dc, code, instr->flags); - - if (dc->zero) { - tcg_temp_free(dc->zero); - } } static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) From patchwork Thu Mar 17 05:05:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552230 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp881860mag; Wed, 16 Mar 2022 22:27:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxm9OX22KIhJykeMU8AFwg88EdHQeOhaVn8JvUA9ta3nW9u0LS9LtAaujpIY55z8FFfmj+2 X-Received: by 2002:a37:6690:0:b0:67d:335c:29d4 with SMTP id a138-20020a376690000000b0067d335c29d4mr1832434qkc.726.1647494854739; Wed, 16 Mar 2022 22:27:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647494854; cv=none; d=google.com; s=arc-20160816; b=v/bYYuqHNhnB1TjRlOccZXXQUV+juh78d44DqQ0JqsnIRYra+s0Qt5KT5iGpiZo9+I 3QWjGGheNQ4du5c8BpqEQ/LxdOuk0JSC4g/ZYpNp6SKPKEG+o/zme6iR+fMWlMbnNGHS uFs7UIhQnE3poIFFoGbciSmB0WIv3DTxcihdtCfFvM6/J+7ePcCWOzCfxwPH62Me3ciT WjDDCkQtjqrPgyHN8p5bMjySjWyz+eUUBhEezvL0nVT8IoSv/2BT8ou8N5b+gwtV57Zp TdooHTuq0i6zSMEqij1PCoPg2X50pJB+sCp+GeQ4G9dbpItpU43R7VrmJ8z3hd3mOyOr l7Iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rjl4pB0UOR++7sXmU/aZUMTVos+sgfIbyM2Yn1YOAwo=; b=TYf/Lr4l6ZIgCryJ9qIycPIjj+iqMoqW4IzQz5fFqrEbXV2rSq/BLOuxwf1mjXrhGi Id2G/PazjuSiCzkmiMl04VdmoXuTcfoOQMKrCG8bwgCQjj3mxVJwpt+YSFTdT82voCmm PIGJOvG3an1KwBOgAWa0igCbhnmIa1Yil7bK47r8j0Pb2xqm1XTnaSkzfZkSytbVEcuu o/PlUKhYVIoezPcJE3YUoPFISK/gCX9rJgRl75G64wFzBUMtRn/VoFE7UQG9bo6EE96t 1Gg/6ClEXwQDj0Xp1OGGOCKAjgmTuk+KB5TdFLogvSW0WQXJk4k7DLOA8TnnD57eLO+g NHIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="pz+ZB/O4"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 32/51] target/nios2: Introduce dest_gpr Date: Wed, 16 Mar 2022 22:05:19 -0700 Message-Id: <20220317050538.924111-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Constrain all references to cpu_R[] to load_gpr and dest_gpr. This will be required for supporting shadow register sets. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/translate.c | 153 ++++++++++++++------------------------- 1 file changed, 55 insertions(+), 98 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 4ad47bb966..d5f2e98de9 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -101,6 +101,7 @@ typedef struct DisasContext { DisasContextBase base; target_ulong pc; int mem_idx; + TCGv sink; const ControlRegState *cr_state; } DisasContext; @@ -133,6 +134,18 @@ static TCGv load_gpr(DisasContext *dc, unsigned reg) return cpu_R[reg]; } +static TCGv dest_gpr(DisasContext *dc, unsigned reg) +{ + assert(reg < NUM_GP_REGS); + if (unlikely(reg == R_ZERO)) { + if (dc->sink == NULL) { + dc->sink = tcg_temp_new(); + } + return dc->sink; + } + return cpu_R[reg]; +} + static void t_gen_helper_raise_exception(DisasContext *dc, uint32_t index) { @@ -191,7 +204,7 @@ static void jmpi(DisasContext *dc, uint32_t code, uint32_t flags) static void call(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next); + tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); jmpi(dc, code, flags); } @@ -204,27 +217,10 @@ static void gen_ldx(DisasContext *dc, uint32_t code, uint32_t flags) I_TYPE(instr, code); TCGv addr = tcg_temp_new(); - TCGv data; - - /* - * WARNING: Loads into R_ZERO are ignored, but we must generate the - * memory access itself to emulate the CPU precisely. Load - * from a protected page to R_ZERO will cause SIGSEGV on - * the Nios2 CPU. - */ - if (likely(instr.b != R_ZERO)) { - data = cpu_R[instr.b]; - } else { - data = tcg_temp_new(); - } + TCGv data = dest_gpr(dc, instr.b); tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s); tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags); - - if (unlikely(instr.b == R_ZERO)) { - tcg_temp_free(data); - } - tcg_temp_free(addr); } @@ -254,7 +250,7 @@ static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags) I_TYPE(instr, code); TCGLabel *l1 = gen_new_label(); - tcg_gen_brcond_tl(flags, cpu_R[instr.a], cpu_R[instr.b], l1); + tcg_gen_brcond_tl(flags, load_gpr(dc, instr.a), load_gpr(dc, instr.b), l1); gen_goto_tb(dc, 0, dc->base.pc_next); gen_set_label(l1); gen_goto_tb(dc, 1, dc->base.pc_next + (instr.imm16.s & -4)); @@ -262,11 +258,12 @@ static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags) } /* Comparison instructions */ -#define gen_i_cmpxx(fname, op3) \ -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ -{ \ - I_TYPE(instr, (code)); \ - tcg_gen_setcondi_tl(flags, cpu_R[instr.b], cpu_R[instr.a], (op3)); \ +#define gen_i_cmpxx(fname, op3) \ +static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ +{ \ + I_TYPE(instr, (code)); \ + tcg_gen_setcondi_tl(flags, dest_gpr(dc, instr.b), \ + load_gpr(dc, instr.a), (op3)); \ } gen_i_cmpxx(gen_cmpxxsi, instr.imm16.s) @@ -277,13 +274,7 @@ gen_i_cmpxx(gen_cmpxxui, instr.imm16.u) static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ { \ I_TYPE(instr, (code)); \ - if (unlikely(instr.b == R_ZERO)) { /* Store to R_ZERO is ignored */ \ - return; \ - } else if (instr.a == R_ZERO) { /* MOVxI optimizations */ \ - tcg_gen_movi_tl(cpu_R[instr.b], (resimm) ? (op3) : 0); \ - } else { \ - tcg_gen_##insn##_tl(cpu_R[instr.b], cpu_R[instr.a], (op3)); \ - } \ + tcg_gen_##insn##_tl(dest_gpr(dc, instr.b), load_gpr(dc, instr.a), (op3)); \ } gen_i_math_logic(addi, addi, 1, instr.imm16.s) @@ -386,7 +377,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) #else TCGv tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS])); - gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]); + gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA)); tcg_temp_free(tmp); dc->base.is_jmp = DISAS_NORETURN; @@ -396,8 +387,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) /* PC <- ra */ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_pc, cpu_R[R_RA]); - + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, R_RA)); dc->base.is_jmp = DISAS_JUMP; } @@ -416,7 +406,7 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) #else TCGv tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS])); - gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]); + gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_BA)); tcg_temp_free(tmp); dc->base.is_jmp = DISAS_NORETURN; @@ -429,7 +419,6 @@ static void jmp(DisasContext *dc, uint32_t code, uint32_t flags) R_TYPE(instr, code); tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); - dc->base.is_jmp = DISAS_JUMP; } @@ -438,9 +427,7 @@ static void nextpc(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - if (likely(instr.c != R_ZERO)) { - tcg_gen_movi_tl(cpu_R[instr.c], dc->base.pc_next); - } + tcg_gen_movi_tl(dest_gpr(dc, instr.c), dc->base.pc_next); } /* @@ -452,7 +439,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags) R_TYPE(instr, code); tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); - tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next); + tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); dc->base.is_jmp = DISAS_JUMP; } @@ -468,15 +455,11 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) g_assert_not_reached(); #else R_TYPE(instr, code); - TCGv t1, t2; - - if (unlikely(instr.c == R_ZERO)) { - return; - } + TCGv t1, t2, dest = dest_gpr(dc, instr.c); /* Reserved registers read as zero. */ if (nios2_cr_reserved(&dc->cr_state[instr.imm5])) { - tcg_gen_movi_tl(cpu_R[instr.c], 0); + tcg_gen_movi_tl(dest, 0); return; } @@ -494,12 +477,12 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) t2 = tcg_temp_new(); tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDING])); tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE])); - tcg_gen_and_tl(cpu_R[instr.c], t1, t2); + tcg_gen_and_tl(dest, t1, t2); tcg_temp_free(t1); tcg_temp_free(t2); break; default: - tcg_gen_ld_tl(cpu_R[instr.c], cpu_env, + tcg_gen_ld_tl(dest, cpu_env, offsetof(CPUNios2State, ctrl[instr.imm5])); break; } @@ -575,10 +558,8 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - if (likely(instr.c != R_ZERO)) { - tcg_gen_setcond_tl(flags, cpu_R[instr.c], cpu_R[instr.a], - cpu_R[instr.b]); - } + tcg_gen_setcond_tl(flags, dest_gpr(dc, instr.c), + load_gpr(dc, instr.a), load_gpr(dc, instr.b)); } /* Math/logic instructions */ @@ -586,9 +567,7 @@ static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags) static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ { \ R_TYPE(instr, (code)); \ - if (likely(instr.c != R_ZERO)) { \ - tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), (op3)); \ - } \ + tcg_gen_##insn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), (op3)); \ } gen_r_math_logic(add, add_tl, load_gpr(dc, instr.b)) @@ -609,28 +588,24 @@ gen_r_math_logic(roli, rotli_tl, instr.imm5) static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ { \ R_TYPE(instr, (code)); \ - if (likely(instr.c != R_ZERO)) { \ - TCGv t0 = tcg_temp_new(); \ - tcg_gen_##insn(t0, cpu_R[instr.c], \ - load_gpr(dc, instr.a), load_gpr(dc, instr.b)); \ - tcg_temp_free(t0); \ - } \ + TCGv t0 = tcg_temp_new(); \ + tcg_gen_##insn(t0, dest_gpr(dc, instr.c), \ + load_gpr(dc, instr.a), load_gpr(dc, instr.b)); \ + tcg_temp_free(t0); \ } gen_r_mul(mulxss, muls2_tl) gen_r_mul(mulxuu, mulu2_tl) gen_r_mul(mulxsu, mulsu2_tl) -#define gen_r_shift_s(fname, insn) \ -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ -{ \ - R_TYPE(instr, (code)); \ - if (likely(instr.c != R_ZERO)) { \ - TCGv t0 = tcg_temp_new(); \ - tcg_gen_andi_tl(t0, load_gpr((dc), instr.b), 31); \ - tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), t0); \ - tcg_temp_free(t0); \ - } \ +#define gen_r_shift_s(fname, insn) \ +static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ +{ \ + R_TYPE(instr, (code)); \ + TCGv t0 = tcg_temp_new(); \ + tcg_gen_andi_tl(t0, load_gpr(dc, instr.b), 31); \ + tcg_gen_##insn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), t0); \ + tcg_temp_free(t0); \ } gen_r_shift_s(sra, sar_tl) @@ -642,39 +617,15 @@ gen_r_shift_s(ror, rotr_tl) static void divs(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); - TCGv dest; - - if (instr.c == R_ZERO) { - dest = tcg_temp_new(); - } else { - dest = cpu_R[instr.c]; - } - - gen_helper_divs(dest, cpu_env, + gen_helper_divs(dest_gpr(dc, instr.c), cpu_env, load_gpr(dc, instr.a), load_gpr(dc, instr.b)); - - if (instr.c == R_ZERO) { - tcg_temp_free(dest); - } } static void divu(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); - TCGv dest; - - if (instr.c == R_ZERO) { - dest = tcg_temp_new(); - } else { - dest = cpu_R[instr.c]; - } - - gen_helper_divu(dest, cpu_env, + gen_helper_divu(dest_gpr(dc, instr.c), cpu_env, load_gpr(dc, instr.a), load_gpr(dc, instr.b)); - - if (instr.c == R_ZERO) { - tcg_temp_free(dest); - } } static void trap(DisasContext *dc, uint32_t code, uint32_t flags) @@ -864,8 +815,14 @@ static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) return; } + dc->sink = NULL; + instr = &i_type_instructions[op]; instr->handler(dc, code, instr->flags); + + if (dc->sink) { + tcg_temp_free(dc->sink); + } } static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) From patchwork Thu Mar 17 05:05:20 2022 Content-Type: text/plain; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 33/51] target/nios2: Drop CR_STATUS_EH from tb->flags Date: Wed, 16 Mar 2022 22:05:20 -0700 Message-Id: <20220317050538.924111-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1031 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There's nothing about EH that affects translation, so there's no need to include it in tb->flags. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 95079c186c..d5255e9e76 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -276,7 +276,7 @@ static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc, { *pc = env->pc; *cs_base = 0; - *flags = env->ctrl[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U); + *flags = env->ctrl[CR_STATUS] & CR_STATUS_U; } #endif /* NIOS2_CPU_H */ From patchwork Thu Mar 17 05:05:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552236 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp885285mag; Wed, 16 Mar 2022 22:34:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwe3cPU7IbS5Nvc9imQ/7nHktPNxc7ft51DK6TLedxF2cMD9tsIWRY5WNvZEh1OdU1/c9rY X-Received: by 2002:a05:622a:650:b0:2e1:e5cb:e47d with SMTP id a16-20020a05622a065000b002e1e5cbe47dmr2483174qtb.223.1647495268019; Wed, 16 Mar 2022 22:34:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647495268; cv=none; d=google.com; s=arc-20160816; b=mBW0SJ659V8Lywi343UTU8jRd+Ptc/gF27hbpzq4Hl7Vbdg6QppPqgt5vIHpdplvcQ tePIk9nvY37+GlR/d6jFVgjHeotrmk1eSCV7CDqeI3OhoPHAUWFHLQiRilzsnJHmKWuh 8eqmjjqaZdYe74HDNwADbssF7ScOE5K2Lc7ZHu4jyyVCEf6C7g9elCGIid6pYlWvIIsH wBkJ0Bwd3cA4ri8zic9ieC2/HpCmrYYGEbbHMvgu7Uzs/ECc21bgtpAXAqGEPpjuuatw /1stEHQL/hzFlea9zljUeMFuv2bTgUoVMKwkvRWTCbU0NoeJJlZShPvw9BoR6B+OQAWN 3zww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5de5JN0djpoCpESfODi2INQYJ/S5KNFn/Rt19ewlkfA=; b=hltSkCgICZszl5oxtXmVFgkoWQMf06rUAGKf0APMaO/+a9hNzL4E+6JThKEu9TfhUu N4KhwDIcSGWhjGZ6o75EmIT9D0k4Q5KOTBkozrnB1ebp8IBhxqAIqUIEXHtt5YEYPqi9 boNipxF/SY3q/2cMYW8bCKLBmRfnRDU+KR6ptmGyfqyn1E2kmd8yQFFOg9P+GpokfaWK 3f5EYNCuO3mE5urB89ZUkWJW8hC9TB5pZol0rrRXVmeKwKKK2SpoggGe6qGLNkg4RpkL HF42VDKsv4tD4oQgHbcrPb4lFpifA16mk+Jl+5slTXrsBT50g5ruAxqazeEBwReDrfhF o+uQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SGOpv71I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 34/51] target/nios2: Enable unaligned traps for system mode Date: Wed, 16 Mar 2022 22:05:21 -0700 Message-Id: <20220317050538.924111-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Unaligned traps are optional, but required with an mmu. Turn them on always, because the fallback behaviour is not documented (though presumably it discards low bits). Enable alignment checks in the config file. Unwind the guest pc properly from do_unaligned_access. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/helper.c | 4 ++-- configs/targets/nios2-softmmu.mak | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 460032adc0..bf40cff779 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -264,8 +264,8 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr, CPUNios2State *env = &cpu->env; env->ctrl[CR_BADADDR] = addr; - env->ctrl[CR_EXCEPTION] = FIELD_DP32(0, CR_EXCEPTION, CAUSE, EXCP_UNALIGN); - helper_raise_exception(env, EXCP_UNALIGN); + cs->exception_index = EXCP_UNALIGN; + cpu_loop_exit_restore(cs, retaddr); } bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/configs/targets/nios2-softmmu.mak b/configs/targets/nios2-softmmu.mak index 9a372f0717..1e93b54cd1 100644 --- a/configs/targets/nios2-softmmu.mak +++ b/configs/targets/nios2-softmmu.mak @@ -1 +1,2 @@ TARGET_ARCH=nios2 +TARGET_ALIGNED_ONLY=y From patchwork Thu Mar 17 05:05:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552234 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp883408mag; Wed, 16 Mar 2022 22:31:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyv0tathqR+C91oNe27qUmYqH/uE5OR16vYf2Zu1P8F3/V8doPtDRNvnbtmBPWgMMzx/Qhl X-Received: by 2002:ad4:5f06:0:b0:440:c617:b9ae with SMTP id fo6-20020ad45f06000000b00440c617b9aemr2241662qvb.127.1647495068077; Wed, 16 Mar 2022 22:31:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647495068; cv=none; d=google.com; s=arc-20160816; b=HuDWIpp6Oifzl39w1obwibh5aO9FiHvF9YZQx7ZI8o5dbxwagXnOesuzWr1o9ZedOj 1K4spbBYzZW+xWQPDEHTSsz92zYbkdhWbAYn3xm/nSAr26lj7W0VCwBIJGQdozGLGiUV LSXECmIx8vZmkpvjIxjVDW/BkDzTcJlI2O5mHnWLMfj1vtSkOkJHwb7TS7d4zbkF1/tq 5h9yFp8MPMZLYebUwHfie1LnOQMYdZgU7pGRaWdgGifjaGOE2S5EXYXBybr9yfMR3C5y hBW86SOupW42O2yms3J62SpTjnspfoLZ9InCrn7vTMCRo2qINXyn385IUQdh/wd3mwX5 62AQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=a0Y1+UOzMYE465JAg/1XZp8FHRvlzNh9RDhixInPs2c=; b=kiY0/k6JdKLBIZKTO93Po4312bOTGWjY7HOidRxFT2yVwy6P9OAfW8PyzhH0a+9cuq ENtUlylYjCdtdL7QIXMA85B4wVsf0NKxzBruDXDnb7RMYGWjymlrUvfRmvmPbwAJ9kgi OWd91r4J8fROQde46Brk6JkQLbzm20tqMhVXSdT76s3o0S6E7OyzX6EX/0+B+PuFXXj1 r7BZhbbMzcC2ROtV2dN5oXCltea64HMpXaXJ+0hHP5Y9Wj810zrpVmssBZ4NjmtMu5SZ 3QnA3BbVfn2DQAXZoG/G8q8KYm4I6K4wA8ALCQMEeyyNgpDtIiV7XJO/90IzOYZtbk56 K6CQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PliBKBi9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 35/51] target/nios2: Create gen_jumpr Date: Wed, 16 Mar 2022 22:05:22 -0700 Message-Id: <20220317050538.924111-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out a function to perform an indirect branch. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index d5f2e98de9..f61ba92052 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -36,7 +36,6 @@ #include "semihosting/semihost.h" /* is_jmp field values */ -#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ #define INSTRUCTION_FLG(func, flags) { (func), (flags) } @@ -168,6 +167,16 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest) } } +static void gen_jumpr(DisasContext *dc, int regno, bool is_call) +{ + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, regno)); + if (is_call) { + tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); + } + tcg_gen_exit_tb(NULL, 0); + dc->base.is_jmp = DISAS_NORETURN; +} + static void gen_excp(DisasContext *dc, uint32_t code, uint32_t flags) { t_gen_helper_raise_exception(dc, flags); @@ -387,8 +396,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) /* PC <- ra */ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_pc, load_gpr(dc, R_RA)); - dc->base.is_jmp = DISAS_JUMP; + gen_jumpr(dc, R_RA, false); } /* @@ -418,8 +426,7 @@ static void jmp(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); - dc->base.is_jmp = DISAS_JUMP; + gen_jumpr(dc, instr.a, false); } /* rC <- PC + 4 */ @@ -438,10 +445,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); - tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); - - dc->base.is_jmp = DISAS_JUMP; + gen_jumpr(dc, instr.a, true); } /* rC <- ctlN */ @@ -838,11 +842,6 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) tcg_gen_exit_tb(NULL, 0); break; - case DISAS_JUMP: - /* The jump will already have updated the PC register */ - tcg_gen_exit_tb(NULL, 0); - break; - case DISAS_NORETURN: /* nothing more to generate */ break; From patchwork Thu Mar 17 05:05:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552240 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp886610mag; Wed, 16 Mar 2022 22:37:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwM/YCW/xYHDUqJin9PNYKQiyU+FTRhBf0cRhBk80cuR3l6aat//1V9YkrG4xtN+0cwo7W9 X-Received: by 2002:a05:620a:783:b0:67d:4c9d:d103 with SMTP id 3-20020a05620a078300b0067d4c9dd103mr1828471qka.250.1647495433327; Wed, 16 Mar 2022 22:37:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647495433; cv=none; d=google.com; s=arc-20160816; b=TWVp0g6eip8vaAr7mRCaqJJbcn2n2ptGQlMNXih6qsuzc9bFDUUGCOMxA5thTVyKzc EUEmYbL45tee00wf2u1UxbhlfSNwDqF4ZmSd+qWkEMQJOsRA4fJGb3ffSD45CI1l2tB3 wYObH+aJkw7NH7rNJrfmkzZWc4RH9Nt8Yzjg3Fdw5Yu0lQ6TtF2Y2CTsNA/FIT2myCzQ H3S+ZcGuGd8ABL3l5D/9CTT/spY+19mtagf/3Jzsu83uNUG6cxyQpGGm00d5W+GKuRsP S+1dLP1VULWSnAbxPNyTipWlcF2iz8a/4WOdG46+1BAI1Ko7Ca06yXvmKaLIDmfFG1np 9/vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PHMXz9q73HVjYaAorTgnEhJkrDs42cYUdRyVosZEm/k=; b=Aozy7To7Iw73OBHzGrAmO56STz9jxJNYS4WAkNebSd3spZtFdSPz0NeyJSFTZwHc3D cRssdp8n5tDU8x1t3eyhwryCPVKlAnzNuO44bHmy+4qNA2xgjMU2jDJ6yDloUOONdNy0 tgxNCwRYJwgSbkmQbsDNqtL/Tz525fOcKJ6fNI9RbGrCNdkQtwMoYNnrrmwLv8uRD1qh gIIXOHNgKQYxrCneyUPqzNM5gocfYIREi/sFSOqayzFMN7nq93WUjW+r+b4b8EB4PhUU QoPUkRHznmudplaVqfq5/9Pv9yFPIV4TL1tG6X4qs+Ue0PbJvv90u1hZye38k+qGU7Iy 6LLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yjy7i+vQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 36/51] target/nios2: Hoist set of is_jmp into gen_goto_tb Date: Wed, 16 Mar 2022 22:05:23 -0700 Message-Id: <20220317050538.924111-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than force all callers to set this, do it within the subroutine. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index f61ba92052..51907586ab 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -165,6 +165,7 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest) tcg_gen_movi_tl(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } + dc->base.is_jmp = DISAS_NORETURN; } static void gen_jumpr(DisasContext *dc, int regno, bool is_call) @@ -208,7 +209,6 @@ static void jmpi(DisasContext *dc, uint32_t code, uint32_t flags) { J_TYPE(instr, code); gen_goto_tb(dc, 0, (dc->pc & 0xF0000000) | (instr.imm26 << 2)); - dc->base.is_jmp = DISAS_NORETURN; } static void call(DisasContext *dc, uint32_t code, uint32_t flags) @@ -251,7 +251,6 @@ static void br(DisasContext *dc, uint32_t code, uint32_t flags) I_TYPE(instr, code); gen_goto_tb(dc, 0, dc->base.pc_next + (instr.imm16.s & -4)); - dc->base.is_jmp = DISAS_NORETURN; } static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags) @@ -263,7 +262,6 @@ static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags) gen_goto_tb(dc, 0, dc->base.pc_next); gen_set_label(l1); gen_goto_tb(dc, 1, dc->base.pc_next + (instr.imm16.s & -4)); - dc->base.is_jmp = DISAS_NORETURN; } /* Comparison instructions */ From patchwork Thu Mar 17 05:05:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552243 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp889550mag; Wed, 16 Mar 2022 22:43:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwMnPc+dXVIYyqy+m33wfKuogFs4Dax7yJPHGEYKbO+3Ai8X88hYfiaaHapazV+nriSuU+A X-Received: by 2002:a05:622a:13cb:b0:2e1:e14e:5b1f with SMTP id p11-20020a05622a13cb00b002e1e14e5b1fmr2399286qtk.317.1647495809111; Wed, 16 Mar 2022 22:43:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647495809; cv=none; d=google.com; s=arc-20160816; b=UJTuTIj9qATYz2Hd1HGqLG9E8tBeNSo+mL8VAsBkJHnQqyXohLlVjmHg1Hck2kMLSZ nI15lWyUvx0f2udnFe634TizJJVMYqJh1guYM5/XJgE4GJV8PBPSlWp2cPa4bBhzrf/I Hj4YeV+H1f57apG28CQ2ujzViNXLMAwCkctdIntu3bpUtrgsEQWHm2sQ5/kBInMoeq3Q 9zR/0njzOIJ0ocxQjbHR0R2bK1MQNb6rhhGkek2xZvICIChW7DLuexU5yxJYr/zmy/Y+ sPlOhoGcCWCvWxovZhR7mHakiAKUw3D5XoVOrGYm+TFiL7GScXs/q4TFdVhFHJXY+j+P G9RQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3YCeMoFSIPOtuFxyHW9qCFQJFQUeLRVbZvCIxi8q4XE=; b=nqWuLd/kWUiFk/Mw6bInzpkPgKl9DQIbdnXWPvwolCQ2bndcmvnCAhBqz7Zvw9uOGT CaZtb8rn4R4zOcVu2xQTdD60MsypEH7Itje3nXIU19/CF0+542sQ8Iuuvp7Qx3yQgfaw ZVpCxOWHx/NH4aSZfMsMG4rmkrLFCu4HboZ6K7XGzlfl1YzqDPwUoaq+5UeLeRKMZv7i xd9YaL50zyzxZPyVrF+zUDF8baeJ3dNltDeQpXEhYVOi18VhvsAV70YXU1ipmtAUd2wS UiCK96BxbQ0xyIKQZq+JYNoUZE2wwzzkBqOxzmlbHVJAbZ1mviLhhLvy7NaX89kLcug/ OvdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Z3mfbAng; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 37/51] target/nios2: Use gen_goto_tb for DISAS_TOO_MANY Date: Wed, 16 Mar 2022 22:05:24 -0700 Message-Id: <20220317050538.924111-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Depending on the reason for ending the TB, we can chain to the next TB because the PC is constant. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 51907586ab..6f31b6cc50 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -834,8 +834,11 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) /* Indicate where the next block should start */ switch (dc->base.is_jmp) { case DISAS_TOO_MANY: + gen_goto_tb(dc, 0, dc->base.pc_next); + break; + case DISAS_UPDATE: - /* Save the current PC back into the CPU register */ + /* Save the current PC, and return to the main loop. */ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); tcg_gen_exit_tb(NULL, 0); break; From patchwork Thu Mar 17 05:05:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552231 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp882901mag; Wed, 16 Mar 2022 22:30:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx5yd7yuxCk252nUzUGttpBuXIm0/8zDjzhFbyX/+urjt56o2qJb8i2Yf6reL0fPVjy8O26 X-Received: by 2002:a05:620a:22f9:b0:67d:1561:f4f4 with SMTP id p25-20020a05620a22f900b0067d1561f4f4mr1785336qki.217.1647495003273; Wed, 16 Mar 2022 22:30:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647495003; cv=none; d=google.com; s=arc-20160816; b=CkfP1VZ2b6wfe9kTVuQkt1VwsAZHBdwZDD5Qk+EFQqCh6hCxjrxapMa3xI55/uXILw X62lEM7gY3S6UQdqs0W0x6MMs6RqKjr9okwWCjRW+557VAABkWwDYSQYyuFW83Ltzuzo HgtnxMw6NOr4TARV0t1g60D67HGo//YX4uKsuuMSStutVlpRd4emxUMuh1X78EadsPLw i/fKyBqZAU+A+TCJnp7sV0oP7nsg3ok2tm622gjr6PIsMjVBj3pi4SpF5lZ/DBtwCC3b TfK3lPvj4TvlnllETmA/LH0J3BoA8PKdxjPDEnBEqQ9JFfn8hx4Q7ziyuSSsQKs2qkge 4WAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QMOimEYkivNn0EOtJQFRq+oOiueoNqaCGaU7AEWQQss=; b=HXlzC8/iFaB0ujqh53vCD6SzksWshT55USJymIGhlugWQMKhJaQzI58is3/7mncH1e vT7f2NFGcJPulphC9uu/XOhVFROJfyc8kfQRXwfFJmku8q0LdOQRg+9Hp9jzB82FMxTO rbxerlhELU8Q0BdJ5Jk7oA0sB8VPSXcevVOGF3+q0HtRsN0iJq7e7XBcgMWwujaVPXpo q/Tr40XjoLs3yB9kwKAABxkOIiva/EPwSH6DwM6ObEid83DAZiKTdujwiKeoCQc5o6nR y6/BcPV9Jz0OG5VhlN8aH6nXHikbQVjVi1xWSW5B25DtqvsqK1nTem4ZiokgK48JUrYK Py1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=w8cHfXuZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 38/51] target/nios2: Use tcg_gen_lookup_and_goto_ptr Date: Wed, 16 Mar 2022 22:05:25 -0700 Message-Id: <20220317050538.924111-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::431 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use lookup_and_goto_ptr for indirect chaining between TBs. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 6f31b6cc50..f7bab0908b 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -163,7 +163,7 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest) tcg_gen_exit_tb(tb, n); } else { tcg_gen_movi_tl(cpu_pc, dest); - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } dc->base.is_jmp = DISAS_NORETURN; } @@ -174,7 +174,7 @@ static void gen_jumpr(DisasContext *dc, int regno, bool is_call) if (is_call) { tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); } - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); dc->base.is_jmp = DISAS_NORETURN; } From patchwork Thu Mar 17 05:05:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552238 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp885310mag; Wed, 16 Mar 2022 22:34:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwc1qm1OQRAI7fYxxwvG5L2d6VhyPq4ADma9ePXrbEMU5RiRlUW4fFTyWyXGYCt6hv1U8NR X-Received: by 2002:a37:674c:0:b0:47b:8dc5:df77 with SMTP id b73-20020a37674c000000b0047b8dc5df77mr1910883qkc.95.1647495271522; Wed, 16 Mar 2022 22:34:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647495271; cv=none; d=google.com; s=arc-20160816; b=Odu4xPojdK6sDDvKj3zBl6LZNBEzqSXVvZMFib5Y8/zek8xZySDM2YlVpZfDt7SGZV U9VwVPk2ojTSBIAmN8Hszsd8FBrrnaGYxwreicGxeD6b0uSB4nZoeBWzpl2JNhR4d3So sB5Y86OkPqkPbIIVq8KBoZ2/RA93TibJTznpSky9htUz0Hfv0KK0Bto0wtg3bJhqLM0p jDgDWa2P0Z6F60Zb+tov8Iljz+3DKhvBEk+GMGMaK0ZX8Ic9ParrgEq/GX0XrmHWYgS4 huz+B+K0fHDvrLNQawGYwJA9FPazyLcV6Qr9Fe5KJ87tRQRoxb3mYEH7DDsfxor/evDH dYPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LTuw5YwD7AAqbGDKsXNMlzx47tIusaHPWNHDAjQuUEg=; b=HOisY09hWUit/NiqsZJfJQFwyguY16aYHsQLBPRI5anVNFavp0Zs8b1oAg357Hg9nx iCGoT7lcHzqioijSAQJojsf8TLLseICzOam9lIUTzfS2xgEUK6FserXtZCLigQBkfdxC b9BOnORVqSxtA90AcqspgQ8MvGX33kiXvQJv7tzx8Hjd2x9NcKKZXc2qgbWBnzjK5vLD 1eTEqg1CWDADGfeT6a12rWTvt3w92+jCRVJZqf4aJJzyduPHUfQnejzRc+mmzMVQC3aQ JEjZA5zJIjgR8jmjy7Mj/a7xQT3R/mfcFvoGlqahuYyDJsMPDgTBGf0gebE4z4fLdOCl Ioow== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NPqF158v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id h22-20020a056a001a5600b004f7c17b291asm5101357pfv.87.2022.03.16.22.06.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:06:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 39/51] target/nios2: Implement Misaligned destination exception Date: Wed, 16 Mar 2022 22:05:26 -0700 Message-Id: <20220317050538.924111-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Indirect branches, plus eret and bret optionally raise an exception when branching to a misaligned address. The exception is required when an mmu is enabled, but enable it always because the fallback behaviour is not documented (though presumably it discards low bits). For the purposes of the linux-user cpu loop, if EXCP_UNALIGN (misaligned data) were to arrive, it would be treated the same as EXCP_UNALIGND (misaligned destination). See the !defined(CONFIG_NIOS2_ALIGNMENT_TRAP) block in kernel/traps.c. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/nios2/cpu_loop.c | 6 ++++++ target/nios2/op_helper.c | 9 ++++++++- target/nios2/translate.c | 15 ++++++++++++++- 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index ea364b7d1f..67220128aa 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -43,6 +43,12 @@ void cpu_loop(CPUNios2State *env) force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); break; + case EXCP_UNALIGN: + case EXCP_UNALIGND: + force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, + env->ctrl[CR_BADADDR]); + break; + case EXCP_TRAP: switch (env->error_code) { case 0: diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index c93b66c9aa..849867becd 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -64,6 +64,13 @@ uint32_t helper_divu(CPUNios2State *env, uint32_t num, uint32_t den) void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) { Nios2CPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); + + if (unlikely(new_pc & 3)) { + env->ctrl[CR_BADADDR] = new_pc; + cs->exception_index = EXCP_UNALIGND; + cpu_loop_exit_restore(cs, GETPC()); + } /* * Both estatus and bstatus have no constraints on write; @@ -74,6 +81,6 @@ void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) env->ctrl[CR_STATUS] = new_status; env->pc = new_pc; - cpu_loop_exit(env_cpu(env)); + cpu_loop_exit(cs); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/translate.c b/target/nios2/translate.c index f7bab0908b..1e784c8a37 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -170,11 +170,24 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest) static void gen_jumpr(DisasContext *dc, int regno, bool is_call) { - tcg_gen_mov_tl(cpu_pc, load_gpr(dc, regno)); + TCGLabel *l = gen_new_label(); + TCGv test = tcg_temp_new(); + TCGv dest = load_gpr(dc, regno); + + tcg_gen_andi_tl(test, dest, 3); + tcg_gen_brcondi_tl(TCG_COND_NE, test, 0, l); + tcg_temp_free(test); + + tcg_gen_mov_tl(cpu_pc, dest); if (is_call) { tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); } tcg_gen_lookup_and_goto_ptr(); + + gen_set_label(l); + tcg_gen_st_tl(dest, cpu_env, offsetof(CPUNios2State, ctrl[CR_BADADDR])); + t_gen_helper_raise_exception(dc, EXCP_UNALIGND); + dc->base.is_jmp = DISAS_NORETURN; } From patchwork Thu Mar 17 05:05:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552235 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp884824mag; Wed, 16 Mar 2022 22:33:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzSVLI9rCys9zBS7aXu22FezP3zz7WmKUl7HWb86Hq3K/au1ilXbYeHrQQ/wRBozyiux5BV X-Received: by 2002:ad4:5743:0:b0:437:b554:1e19 with SMTP id q3-20020ad45743000000b00437b5541e19mr1929928qvx.114.1647495212173; Wed, 16 Mar 2022 22:33:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647495212; cv=none; d=google.com; s=arc-20160816; b=kDEIE6oW5tqX3FpWEQr1909pVj6pdBmU3xK90MpYryC1kOlBh6OwgzkxyKSlvDoUcD PY9eDUN+HrIlPtF5hDi6KD6hv74ETLLE9BBM1NbJ5fRgc7LMo3IJUZtBnb68qif19KE8 8hvOLBdrzbqa2JdCViIJRUbExRnLgi5+qo4BQO/w29OrwxleoXAsarfwVYZsD58FN+57 sXiGjw8kCjdR8OQTatczUVMKv23IXZb0cLzhsUDc9AXOjKu0iSLvBm2hxwcpeXWDwImw e5vxBWTYZQjax4kvcF3JSsT2nNmH0OmDW2PMs5jvCcleeb9Fb0PlylFVKYpLaiitpPzH lWuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aUIv8mPilapal9RFUm8fJDHj8xhqXeKP3105ESvQPFk=; b=XVShROArtoRprXTZBGZxjoZPu3+aGMPBQ+3miSi+Qw6woZt1MJVwrOMTioROesn4fH Ve/NdJRtxIV91yUp9YY0kyUWD4uHPgpHHNf8H0GroHzqoVq9G3hGJmBx7x7loyy1iS0T NUFApPs+6tf/7LYPZCxvE3RQxo1gegYC7MIGIJKV8+CLEy/k1c1NoHR84BRTT9CJNzy7 +TIob5e3Bnutw0SqtIk3y71a2LfUoFlnbyZhdT6G0tHpXp8Y6mQHKEd/PKDTg3Gc4cR2 jad1HsNN2T1H8fUVuPIYvmXW6v+9p8sufboMd86ljuIjLIgOxPN8/zWaJWKS0FPK0wQU tzPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MuWBDkil; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id d10-20020a63360a000000b0037947abe4bbsm4217493pga.34.2022.03.16.22.09.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:09:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 40/51] linux-user/nios2: Handle various SIGILL exceptions Date: Wed, 16 Mar 2022 22:05:27 -0700 Message-Id: <20220317050538.924111-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We missed out on a couple of exception types that may legitimately be raised by a userland program. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/nios2/cpu_loop.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 67220128aa..f223238275 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -49,6 +49,14 @@ void cpu_loop(CPUNios2State *env) env->ctrl[CR_BADADDR]); break; + case EXCP_ILLEGAL: + case EXCP_UNIMPL: + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc); + break; + case EXCP_SUPERI: + force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->pc); + break; + case EXCP_TRAP: switch (env->error_code) { case 0: From patchwork Thu Mar 17 05:05:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552239 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp886207mag; Wed, 16 Mar 2022 22:36:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyEQEtijd9oPQ94seI8sGqu+q0Z6M1dnz/oigkg3yAWOYCyMgqbnb1C31Ly6s6m6yHDXPLt X-Received: by 2002:ac8:5907:0:b0:2e1:ef6f:9535 with SMTP id 7-20020ac85907000000b002e1ef6f9535mr1362574qty.49.1647495372722; Wed, 16 Mar 2022 22:36:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647495372; cv=none; d=google.com; s=arc-20160816; b=PLWGvfGjCBaqPbfB0aDpbV1HpL0tFWwXih2Z8+H+q8iSGGSNZgpyB2BawCG74Wwpb/ fq7ITcv3YMQNw6aZE5b0GGq8xas/SJSwDx6JEArgyKlrr8Pa3FZNM+ZSHmcmjI/+FgvK cpxpdVdESBAW0zfG1rfPglzw4NkbiSHoEUH9narWZ8Sq4z+rrRdjjhLKXrGiFlU7/nEg LLlXpoVx/jkpZB3mW8qdIjcLKodX/i9uavo7MUNJoVmhHLomX3sq761UmUzPEFsPRVhd fdm9V8fcmbL7WXyUB9mD/MZIY1TuR8N4rWRtF0b7BAWmU8Q9Q5t1DliexAjKVXtNGM7c Rnlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KmEvw6sHv9r/CRo1vY+We54ynBSJSjNDjmxvHPXOPAE=; b=EctOl8k0N8kqoQAYCQoAGprAx+YPbAi8PrJjFVJPHpLuw/IdLEVTuXOX/KSBG/roup PXTuWk7BwmL31eZAVK8mixPyIXi6fgDkbaijmrrXh97Xiq6qbYUG+qwbpvNni55JughE sNWltEs06qZFZVDSdtBIDgLsU6e1isKsG0Y2dveBb55IHrutOggBweDlAQrKoR93O3Gc YDTUzjBiRXgqc6jQKg1yQ8J7anPJxBbcbsXqChARXvrQAlS542/8i8Z1+VzalBzYUAq0 1IXW6qmmjRiacdWTJeBxXHPsHm1HynSAGEvRhH+tLo1MqhTUQiMBr6/JpJjIzNmXwGbg ZxQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jQC59tjg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id d10-20020a63360a000000b0037947abe4bbsm4217493pga.34.2022.03.16.22.09.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:09:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 41/51] target/nios2: Introduce shadow register sets Date: Wed, 16 Mar 2022 22:05:28 -0700 Message-Id: <20220317050538.924111-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not actually enable them so far, but add all of the plumbing to address them. Do not enable them for user-only. Add an env->regs pointer that handles the indirection to the current register set. The naming of the pointer hides the difference between old and new, user-only and sysemu. >From the notes on wrprs, which states that r0 must be initialized before use in shadow register sets, infer that R_ZERO is *not* hardwired to zero in shadow register sets. Adjust load_gpr and dest_gpr to reflect this. At the same time we might as well special case crs == 0 to avoid the indirection through env->regs during translation as well. Given that this is intended to be the most common case for non-interrupt handlers. Init env->regs at reset. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 24 +++++++++++++++++ target/nios2/cpu.c | 4 ++- target/nios2/translate.c | 58 +++++++++++++++++++++++++++++++--------- 3 files changed, 72 insertions(+), 14 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index d5255e9e76..e32bebe9b7 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -60,6 +60,11 @@ struct Nios2CPUClass { #define NUM_GP_REGS 32 #define NUM_CR_REGS 32 +#ifndef CONFIG_USER_ONLY +/* 63 shadow register sets; index 0 is the primary register set. */ +#define NUM_REG_SETS 64 +#endif + /* General purpose register aliases */ enum { R_ZERO = 0, @@ -178,7 +183,13 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define EXCP_MPUD 17 struct CPUArchState { +#ifdef CONFIG_USER_ONLY uint32_t regs[NUM_GP_REGS]; +#else + uint32_t shadow_regs[NUM_REG_SETS][NUM_GP_REGS]; + /* Pointer into shadow_regs for the current register set. */ + uint32_t *regs; +#endif uint32_t ctrl[NUM_CR_REGS]; uint32_t pc; @@ -229,6 +240,14 @@ static inline bool nios2_cr_reserved(const ControlRegState *s) return (s->writable | s->readonly) == 0; } +static inline void nios2_update_crs(CPUNios2State *env) +{ +#ifndef CONFIG_USER_ONLY + unsigned crs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS); + env->regs = env->shadow_regs[crs]; +#endif +} + void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); void dump_mmu(CPUNios2State *env); @@ -271,12 +290,17 @@ typedef Nios2CPU ArchCPU; #include "exec/cpu-all.h" +FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS == 0. */ +FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ + static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { *pc = env->pc; *cs_base = 0; *flags = env->ctrl[CR_STATUS] & CR_STATUS_U; + *flags |= (env->ctrl[CR_STATUS] & R_CR_STATUS_CRS_MASK + ? 0 : R_TBFLAGS_CRS0_MASK); } #endif /* NIOS2_CPU_H */ diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 07306efc35..7545abc68e 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -53,15 +53,17 @@ static void nios2_cpu_reset(DeviceState *dev) ncc->parent_reset(dev); - memset(env->regs, 0, sizeof(env->regs)); memset(env->ctrl, 0, sizeof(env->ctrl)); env->pc = cpu->reset_addr; #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ env->ctrl[CR_STATUS] = CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE; + memset(env->regs, 0, sizeof(env->regs)); #else env->ctrl[CR_STATUS] = CR_STATUS_RSIE; + nios2_update_crs(env); + memset(env->shadow_regs, 0, sizeof(env->shadow_regs)); #endif } diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 1e784c8a37..525df7b023 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -100,12 +100,16 @@ typedef struct DisasContext { DisasContextBase base; target_ulong pc; int mem_idx; + bool crs0; TCGv sink; const ControlRegState *cr_state; } DisasContext; static TCGv cpu_R[NUM_GP_REGS]; static TCGv cpu_pc; +#ifndef CONFIG_USER_ONLY +static TCGv cpu_crs_R[NUM_GP_REGS]; +#endif typedef struct Nios2Instruction { void (*handler)(DisasContext *dc, uint32_t code, uint32_t flags); @@ -127,22 +131,36 @@ static uint8_t get_opxcode(uint32_t code) static TCGv load_gpr(DisasContext *dc, unsigned reg) { assert(reg < NUM_GP_REGS); - if (unlikely(reg == R_ZERO)) { - return tcg_constant_tl(0); + if (dc->crs0) { + if (unlikely(reg == R_ZERO)) { + return tcg_constant_tl(0); + } + return cpu_R[reg]; } - return cpu_R[reg]; +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + return cpu_crs_R[reg]; +#endif } static TCGv dest_gpr(DisasContext *dc, unsigned reg) { assert(reg < NUM_GP_REGS); - if (unlikely(reg == R_ZERO)) { - if (dc->sink == NULL) { - dc->sink = tcg_temp_new(); + if (dc->crs0) { + if (unlikely(reg == R_ZERO)) { + if (dc->sink == NULL) { + dc->sink = tcg_temp_new(); + } + return dc->sink; } - return dc->sink; + return cpu_R[reg]; } - return cpu_R[reg]; +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + return cpu_crs_R[reg]; +#endif } static void t_gen_helper_raise_exception(DisasContext *dc, @@ -198,7 +216,7 @@ static void gen_excp(DisasContext *dc, uint32_t code, uint32_t flags) static bool gen_check_supervisor(DisasContext *dc) { - if (dc->base.tb->flags & CR_STATUS_U) { + if (dc->base.tb->flags & R_TBFLAGS_U_MASK) { /* CPU in user mode, privileged instruction called, stop. */ t_gen_helper_raise_exception(dc, EXCP_SUPERI); return false; @@ -794,6 +812,7 @@ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->mem_idx = cpu_mmu_index(env, false); dc->cr_state = cpu->cr_state; + dc->crs0 = FIELD_EX32(dc->base.tb->flags, TBFLAGS, CRS0); /* Bound the number of insns to execute to those left on the page. */ page_insns = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; @@ -927,13 +946,26 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) void nios2_tcg_init(void) { - int i; +#ifndef CONFIG_USER_ONLY + TCGv_ptr crs = tcg_global_mem_new_ptr(cpu_env, + offsetof(CPUNios2State, regs), "crs"); - for (i = 0; i < NUM_GP_REGS; i++) { - cpu_R[i] = tcg_global_mem_new(cpu_env, - offsetof(CPUNios2State, regs[i]), + for (int i = 0; i < NUM_GP_REGS; i++) { + cpu_crs_R[i] = tcg_global_mem_new(crs, 4 * i, gr_regnames[i]); + } + +#define offsetof_regs0(N) offsetof(CPUNios2State, shadow_regs[0][N]) +#else +#define offsetof_regs0(N) offsetof(CPUNios2State, regs[N]) +#endif + + for (int i = 0; i < NUM_GP_REGS; i++) { + cpu_R[i] = tcg_global_mem_new(cpu_env, offsetof_regs0(i), gr_regnames[i]); } + +#undef offsetof_regs0 + cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, pc), "pc"); } From patchwork Thu Mar 17 05:05:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552249 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp894761mag; Wed, 16 Mar 2022 22:54:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwxT2j1U3vTmain/hYcf3wka9JQQaCbxHrcVPm57MXdCNHq2SkmTgjM7mddOzWlV6At5fpF X-Received: by 2002:a05:622a:58f:b0:2e1:eb89:60b5 with SMTP id c15-20020a05622a058f00b002e1eb8960b5mr2482999qtb.166.1647496461480; Wed, 16 Mar 2022 22:54:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647496461; cv=none; d=google.com; s=arc-20160816; b=Gn5aduJuMStMBbGmoCll9+LHnk7bmRG3djdbD2ONc1UpSklDwUnIYzHLRxoAFDLJ16 9fua7UyEj06skHC4RyY+TTbBWOxhgZzytqEB56kWHYEu9Eqkrj1+i0jNq24slzC2GMue wdZGBeTFLKuNmFmXB9nrrTIkNORcaDg4smPvOINt3AKIEPQ69ej7TNVjBiC0JzLMUY+n 0kqjkn6XS1Nphb9VYCER4h8KmSkjA3/FmMMGeamDDNAVVGFJPQrW9osDdp/HTN8Lx1ab VLjcbDO983K7LdmEDiuH8PeYld3TTAseANpuTX4TVeW+YSsrP7CE2/PpAyt5ji6MVvSU AX7g== ARC-Message-Signature: i=1; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id d10-20020a63360a000000b0037947abe4bbsm4217493pga.34.2022.03.16.22.09.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:09:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 42/51] target/nios2: Implement rdprs, wrprs Date: Wed, 16 Mar 2022 22:05:29 -0700 Message-Id: <20220317050538.924111-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement these out of line, so that tcg global temps (aka the architectural registers) are synced back to tcg storage as required. This makes sure that we get the proper results when status.PRS == status.CRS. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 1 + target/nios2/helper.h | 2 ++ target/nios2/op_helper.c | 12 ++++++++++ target/nios2/translate.c | 47 ++++++++++++++++++++++++++++++++++++++-- 4 files changed, 60 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index e32bebe9b7..26d4dcfe12 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -220,6 +220,7 @@ struct ArchCPU { bool diverr_present; bool mmu_present; + bool eic_present; uint32_t pid_num_bits; uint32_t tlb_num_ways; diff --git a/target/nios2/helper.h b/target/nios2/helper.h index 6f5ec60b0d..1648d76ade 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -24,6 +24,8 @@ DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) #if !defined(CONFIG_USER_ONLY) DEF_HELPER_3(eret, noreturn, env, i32, i32) +DEF_HELPER_FLAGS_2(rdprs, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_3(wrprs, void, env, i32, i32) DEF_HELPER_2(mmu_write_tlbacc, void, env, i32) DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32) DEF_HELPER_2(mmu_write_pteaddr, void, env, i32) diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 849867becd..e5e70268da 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -83,4 +83,16 @@ void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) env->pc = new_pc; cpu_loop_exit(cs); } + +uint32_t helper_rdprs(CPUNios2State *env, uint32_t regno) +{ + unsigned prs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, PRS); + return env->shadow_regs[prs][regno]; +} + +void helper_wrprs(CPUNios2State *env, uint32_t regno, uint32_t val) +{ + unsigned prs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, PRS); + env->shadow_regs[prs][regno] = val; +} #endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 525df7b023..2b2f528e00 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -103,6 +103,7 @@ typedef struct DisasContext { bool crs0; TCGv sink; const ControlRegState *cr_state; + bool eic_present; } DisasContext; static TCGv cpu_R[NUM_GP_REGS]; @@ -326,6 +327,27 @@ gen_i_math_logic(andhi, andi, 0, instr.imm16.u << 16) gen_i_math_logic(orhi , ori, 1, instr.imm16.u << 16) gen_i_math_logic(xorhi, xori, 1, instr.imm16.u << 16) +/* rB <- prs.rA + sigma(IMM16) */ +static void rdprs(DisasContext *dc, uint32_t code, uint32_t flags) +{ + if (!dc->eic_present) { + t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); + return; + } + if (!gen_check_supervisor(dc)) { + return; + } + +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + I_TYPE(instr, code); + TCGv dest = dest_gpr(dc, instr.b); + gen_helper_rdprs(dest, cpu_env, tcg_constant_i32(instr.a)); + tcg_gen_addi_tl(dest, dest, instr.imm16.s); +#endif +} + /* Prototype only, defined below */ static void handle_r_type_instr(DisasContext *dc, uint32_t code, uint32_t flags); @@ -387,7 +409,7 @@ static const Nios2Instruction i_type_instructions[] = { INSTRUCTION_FLG(gen_stx, MO_SL), /* stwio */ INSTRUCTION_FLG(gen_bxx, TCG_COND_LTU), /* bltu */ INSTRUCTION_FLG(gen_ldx, MO_UL), /* ldwio */ - INSTRUCTION_UNIMPLEMENTED(), /* rdprs */ + INSTRUCTION(rdprs), /* rdprs */ INSTRUCTION_ILLEGAL(), INSTRUCTION_FLG(handle_r_type_instr, 0), /* R-Type */ INSTRUCTION_NOP(), /* flushd */ @@ -587,6 +609,26 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) #endif } +/* prs.rC <- rA */ +static void wrprs(DisasContext *dc, uint32_t code, uint32_t flags) +{ + if (!dc->eic_present) { + t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); + return; + } + if (!gen_check_supervisor(dc)) { + return; + } + +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + R_TYPE(instr, code); + gen_helper_wrprs(cpu_env, tcg_constant_i32(instr.c), + load_gpr(dc, instr.a)); +#endif +} + /* Comparison instructions */ static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags) { @@ -711,7 +753,7 @@ static const Nios2Instruction r_type_instructions[] = { INSTRUCTION_ILLEGAL(), INSTRUCTION(slli), /* slli */ INSTRUCTION(sll), /* sll */ - INSTRUCTION_UNIMPLEMENTED(), /* wrprs */ + INSTRUCTION(wrprs), /* wrprs */ INSTRUCTION_ILLEGAL(), INSTRUCTION(or), /* or */ INSTRUCTION(mulxsu), /* mulxsu */ @@ -812,6 +854,7 @@ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->mem_idx = cpu_mmu_index(env, false); dc->cr_state = cpu->cr_state; + dc->eic_present = cpu->eic_present; dc->crs0 = FIELD_EX32(dc->base.tb->flags, TBFLAGS, CRS0); /* Bound the number of insns to execute to those left on the page. */ From patchwork Thu Mar 17 05:05:30 2022 Content-Type: text/plain; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id d10-20020a63360a000000b0037947abe4bbsm4217493pga.34.2022.03.16.22.09.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:09:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 43/51] target/nios2: Update helper_eret for shadow registers Date: Wed, 16 Mar 2022 22:05:30 -0700 Message-Id: <20220317050538.924111-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::636 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When CRS = 0, we restore from estatus; otherwise from sstatus. Update for the new CRS. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 1 + target/nios2/op_helper.c | 3 ++- target/nios2/translate.c | 13 ++++++++----- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 26d4dcfe12..62a73c7b32 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -82,6 +82,7 @@ enum { R_FP = 28, R_EA = 29, R_BA = 30, + R_SSTATUS = 30, R_RA = 31, }; diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index e5e70268da..2eac957f68 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -73,7 +73,7 @@ void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) } /* - * Both estatus and bstatus have no constraints on write; + * None of estatus, bstatus, or sstatus have constraints on write; * do not allow reserved fields in status to be set. */ new_status &= (cpu->cr_state[CR_STATUS].writable | @@ -81,6 +81,7 @@ void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) env->ctrl[CR_STATUS] = new_status; env->pc = new_pc; + nios2_update_crs(env); cpu_loop_exit(cs); } diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 2b2f528e00..7a25c864e2 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -435,11 +435,14 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv tmp = tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS])); - gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA)); - tcg_temp_free(tmp); - + if (dc->crs0) { + TCGv tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS])); + gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA)); + tcg_temp_free(tmp); + } else { + gen_helper_eret(cpu_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_EA)); + } dc->base.is_jmp = DISAS_NORETURN; #endif } From patchwork Thu Mar 17 05:05:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552245 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp892958mag; Wed, 16 Mar 2022 22:50:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxkhAAaW3hcA6q7yVqKXfgBQYko9uJAmjkbJM1ulLMOsMKMHrVODWZz1q20YFgc6p7ojtea X-Received: by 2002:ad4:5bc1:0:b0:42d:758c:f694 with SMTP id t1-20020ad45bc1000000b0042d758cf694mr2260140qvt.99.1647496215878; Wed, 16 Mar 2022 22:50:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647496215; cv=none; d=google.com; s=arc-20160816; b=Rx+3djbhcfJyErJ2HlAQl9GdFHusPAlCwq3YDSdpVgFCzAsAyLEzCs77uB0SxOfzfq Tof+rvmAmj+mQDHoUksJaAUuf7qavxggc/72izAydk1jbqF+x8VOG5bkDdDqaSY2bm9j R/szrjt3lzG/JPzG0zftdATGusOdG5nsKu8lrCeb8lYmSbLVVrWSHJfy0IPvHBzX1/ss AlzhH4yw69060iu8jI+PmCCcvCo66DLBf7HguO7TyIz79L6FgARLyiJdAtZkYdN3oQWQ 0ThV8z03+GNeJ/rvX+mPIuP1WSDHUUPHkEMFtT380Q2Tk6uLkR6lN1ZCgWvX5t30tJko Fh1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5oLnRnm4EXgcmf7Z/uhBKSqjfHRtAYxv5izl3E4FWUM=; b=OwySoZxJBp5KIY3QSVN96I4AOF/kHzozpvDKrD3o6B5Oys+GBOM5k+dVQAtVJr2bJk PTZ2Ymg/gDRjmJaPHUeNBCnz3ncjx9GZj/GqeJDSLLdYO7dKsj5I8a2TFUG1a8HcfMqx GaQ59hPu39sVdG0bUiQsqsWTZbuxRamiuUhn8f0HusasAne6XdLaqPUqrWX4uinsHyr1 KR0/OVTv7ksWmBhD9YsHxcE0Q4VlVhA/29ZHoFFE8uRDkroUoJBs3cnP2MAhYEYT7fXV agIlef1caIEjBWiAiS3ohMyCKAg3jylbAnD1V9P7duL3XeJoNaQbnQlAcp7gVPqc8Eri wbyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dzxVhNzQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id d10-20020a63360a000000b0037947abe4bbsm4217493pga.34.2022.03.16.22.09.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:09:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 44/51] target/nios2: Implement EIC interrupt processing Date: Wed, 16 Mar 2022 22:05:31 -0700 Message-Id: <20220317050538.924111-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::432 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the cpu side of the operation. Register one irq line, called EIC. Split out the rather different processing to a separate function. Delay initialization of gpio irqs until realize. We need to provide a window after init in which the board can set eic_present. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 8 ++++ target/nios2/cpu.c | 92 +++++++++++++++++++++++++++++++++---------- target/nios2/helper.c | 47 ++++++++++++++++++++-- 3 files changed, 123 insertions(+), 24 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 62a73c7b32..c9356416e2 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -114,6 +114,7 @@ FIELD(CR_STATUS, CRS, 10, 6) FIELD(CR_STATUS, PRS, 16, 6) FIELD(CR_STATUS, NMI, 22, 1) FIELD(CR_STATUS, RSIE, 23, 1) +FIELD(CR_STATUS, SRS, 31, 1) /* only in sstatus */ #define CR_STATUS_PIE R_CR_STATUS_PIE_MASK #define CR_STATUS_U R_CR_STATUS_U_MASK @@ -121,6 +122,7 @@ FIELD(CR_STATUS, RSIE, 23, 1) #define CR_STATUS_IH R_CR_STATUS_IH_MASK #define CR_STATUS_NMI R_CR_STATUS_NMI_MASK #define CR_STATUS_RSIE R_CR_STATUS_RSIE_MASK +#define CR_STATUS_SRS R_CR_STATUS_SRS_MASK FIELD(CR_EXCEPTION, CAUSE, 2, 5) FIELD(CR_EXCEPTION, ECCFTL, 31, 1) @@ -234,6 +236,12 @@ struct ArchCPU { /* Bits within each control register which are reserved or readonly. */ ControlRegState cr_state[NUM_CR_REGS]; + + /* External Interrupt Controller Interface */ + uint32_t rha; /* Requested handler address */ + uint32_t ril; /* Requested interrupt level */ + uint32_t rrs; /* Requested register set */ + bool rnmi; /* Requested nonmaskable interrupt */ }; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 7545abc68e..ed1e842269 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -68,7 +68,19 @@ static void nios2_cpu_reset(DeviceState *dev) } #ifndef CONFIG_USER_ONLY -static void nios2_cpu_set_irq(void *opaque, int irq, int level) +static void eic_set_irq(void *opaque, int irq, int level) +{ + Nios2CPU *cpu = opaque; + CPUState *cs = CPU(cpu); + + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + +static void iic_set_irq(void *opaque, int irq, int level) { Nios2CPU *cpu = opaque; CPUNios2State *env = &cpu->env; @@ -92,15 +104,6 @@ static void nios2_cpu_initfn(Object *obj) #if !defined(CONFIG_USER_ONLY) mmu_init(&cpu->env); - - /* - * These interrupt lines model the IIC (internal interrupt - * controller). QEMU does not currently support the EIC - * (external interrupt controller) -- if we did it would be - * a separate device in hw/intc with a custom interface to - * the CPU, and boards using it would not wire up these IRQ lines. - */ - qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32); #endif } @@ -133,10 +136,18 @@ static void realize_cr_status(CPUState *cs) RO_REG(CR_EXCEPTION); WR_REG(CR_BADADDR); - /* TODO: These control registers are not present with the EIC. */ - RO_FIELD(CR_STATUS, RSIE); - WR_REG(CR_IENABLE); - RO_REG(CR_IPENDING); + if (cpu->eic_present) { + WR_FIELD(CR_STATUS, RSIE); + RO_FIELD(CR_STATUS, NMI); + WR_FIELD(CR_STATUS, PRS); + RO_FIELD(CR_STATUS, CRS); + WR_FIELD(CR_STATUS, IL); + WR_FIELD(CR_STATUS, IH); + } else { + RO_FIELD(CR_STATUS, RSIE); + WR_REG(CR_IENABLE); + RO_REG(CR_IPENDING); + } if (cpu->mmu_present) { WR_FIELD(CR_STATUS, U); @@ -175,6 +186,14 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev); Error *local_err = NULL; +#ifndef CONFIG_USER_ONLY + if (cpu->eic_present) { + qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1); + } else { + qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32); + } +#endif + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); @@ -192,17 +211,48 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) } #ifndef CONFIG_USER_ONLY +static bool eic_take_interrupt(Nios2CPU *cpu) +{ + CPUNios2State *env = &cpu->env; + const uint32_t status = env->ctrl[CR_STATUS]; + + if (cpu->rnmi) { + return !(status & CR_STATUS_NMI); + } + if (!(status & CR_STATUS_PIE)) { + return false; + } + if (cpu->ril <= FIELD_EX32(status, CR_STATUS, IL)) { + return false; + } + if (cpu->rrs != FIELD_EX32(status, CR_STATUS, CRS)) { + return true; + } + return status & CR_STATUS_RSIE; +} + +static bool iic_take_interrupt(Nios2CPU *cpu) +{ + CPUNios2State *env = &cpu->env; + + if (!(env->ctrl[CR_STATUS] & CR_STATUS_PIE)) { + return false; + } + return env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE]; +} + static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; - if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->ctrl[CR_STATUS] & CR_STATUS_PIE) && - (env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE])) { - cs->exception_index = EXCP_IRQ; - nios2_cpu_do_interrupt(cs); - return true; + if (interrupt_request & CPU_INTERRUPT_HARD) { + if (cpu->eic_present + ? eic_take_interrupt(cpu) + : iic_take_interrupt(cpu)) { + cs->exception_index = EXCP_IRQ; + nios2_cpu_do_interrupt(cs); + return true; + } } return false; } diff --git a/target/nios2/helper.c b/target/nios2/helper.c index bf40cff779..00f27165d9 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -57,6 +57,9 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, uint32_t old_status = env->ctrl[CR_STATUS]; uint32_t new_status = old_status; + /* With shadow regs, exceptions are always taken into CRS 0. */ + new_status &= ~R_CR_STATUS_CRS_MASK; + if ((old_status & CR_STATUS_EH) == 0) { int r_ea = R_EA, cr_es = CR_ESTATUS; @@ -65,7 +68,7 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, cr_es = CR_BSTATUS; } env->ctrl[cr_es] = old_status; - env->regs[r_ea] = env->pc + 4; + env->shadow_regs[0][r_ea] = env->pc + 4; if (cpu->mmu_present) { new_status |= CR_STATUS_EH; @@ -83,8 +86,9 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, } new_status &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_STATUS] = new_status; + nios2_update_crs(env); + if (!is_break) { env->ctrl[CR_EXCEPTION] = FIELD_DP32(0, CR_EXCEPTION, CAUSE, cs->exception_index); @@ -97,6 +101,39 @@ static void do_iic_irq(Nios2CPU *cpu) do_exception(cpu, cpu->exception_addr, 0, false); } +static void do_eic_irq(Nios2CPU *cpu) +{ + CPUNios2State *env = &cpu->env; + uint32_t old_status = env->ctrl[CR_STATUS]; + uint32_t new_status = old_status; + uint32_t old_rs = FIELD_EX32(old_status, CR_STATUS, CRS); + uint32_t new_rs = cpu->rrs; + + new_status = FIELD_DP32(new_status, CR_STATUS, CRS, new_rs); + new_status = FIELD_DP32(new_status, CR_STATUS, IL, cpu->ril); + new_status = FIELD_DP32(new_status, CR_STATUS, NMI, cpu->rnmi); + new_status &= ~(CR_STATUS_RSIE | CR_STATUS_U); + new_status |= CR_STATUS_IH; + + if (!(new_status & CR_STATUS_EH)) { + new_status = FIELD_DP32(new_status, CR_STATUS, PRS, old_rs); + if (new_rs == 0) { + env->ctrl[CR_ESTATUS] = old_status; + } else { + if (new_rs != old_rs) { + old_status |= CR_STATUS_SRS; + } + env->shadow_regs[new_rs][R_SSTATUS] = old_status; + } + env->shadow_regs[new_rs][R_EA] = env->pc + 4; + } + + env->ctrl[CR_STATUS] = new_status; + nios2_update_crs(env); + + env->pc = cpu->rha; +} + void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu = NIOS2_CPU(cs); @@ -162,7 +199,11 @@ void nios2_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_IRQ: - do_iic_irq(cpu); + if (cpu->eic_present) { + do_eic_irq(cpu); + } else { + do_iic_irq(cpu); + } break; case EXCP_TLB_D: From patchwork Thu Mar 17 05:05:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552242 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp886646mag; Wed, 16 Mar 2022 22:37:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzqjEKtT8jc3E3yOSoxv9mgO7ZYh+8eDgWza0AMlp/myIJekELvwdihjX/10eQq+DyZDsrr X-Received: by 2002:a05:6214:5088:b0:43f:326f:2ad3 with SMTP id kk8-20020a056214508800b0043f326f2ad3mr2246014qvb.108.1647495438794; Wed, 16 Mar 2022 22:37:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647495438; cv=none; d=google.com; s=arc-20160816; b=RxeFyeLa4HW9QK1ybVHKeSFHliHgtWZLYCZMZNgW61nHtOP2wJUGe5OFKfKFriVbz6 SZGF+wCCeWfEfsuKNBMKqjwDQqeX1jny0Wp7RSDJZgEqyO5hLM4R++JD2sluB+5ABlwk gigeW24Tb/ehj8hqWV2tkxaSq0BW/l41cfOYzRiBtGSf/mhhisUcsCHFsAb9y2gN23Y2 i+oNEKo1JR3/HFQoct1iCSwrNDh4uHBmGlFoLhabK3tEZvseTu0qQuDDs5VFxBFHj7Gv ABFIXbH3n3FEIK21ipa97AXWYEIgf9QgpvyV9sEPqoq5GaoH6LdAuc2vjvNOgnQtPhOk qSUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Oq3+WovLC1U0SsWCHamcVpyHHoEeCG/N4mUqpqq0Etc=; b=Rv9VUvdXt65ePYcy9myUxDaefMJm99suRCCyhCxQBoJaMyMf0hZflx2pYk2YgOtTaz xg8vCQHXfmvTsFjeYRj1unzCxglLk+m4nxgwUOz67I5Qn33yfpUJRxDREfL00Cp32nQy 8fLg76b8gdBRo1c3fiHsk1uL4NK5BoYb8Jaytebr2oOhLh5TRM5FPhQ/T0KMQyXF/DQc 21F5X/C6taBsUe8Za8xnr9QYYBhavf2olcTguCiSxlaUy7Kw4MI+BMojI4S47vQo/88l 8KUts9BJXuM2HTLP0agS0dY9Nsw/nIuT+S4cEHXXZWF/i3hybb3ey5Z4ng/tLo6g9Nlk 41Gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gRlO9TWS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id d10-20020a63360a000000b0037947abe4bbsm4217493pga.34.2022.03.16.22.09.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:09:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 45/51] hw/intc: Vectored Interrupt Controller (VIC) Date: Wed, 16 Mar 2022 22:05:32 -0700 Message-Id: <20220317050538.924111-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::633 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, Peter Maydell , amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Amir Gonnen Implement nios2 Vectored Interrupt Controller (VIC). VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi fields on Nios2CPU before raising an IRQ. For that purpose, VIC has a "cpu" property which should refer to the nios2 cpu and set by the board that connects VIC. Reviewed-by: Peter Maydell Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-5-amir.gonnen@neuroblade.ai> [rth: Split out nios2_vic.h] Signed-off-by: Richard Henderson --- include/hw/intc/nios2_vic.h | 64 ++++++++ hw/intc/nios2_vic.c | 313 ++++++++++++++++++++++++++++++++++++ hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + 4 files changed, 381 insertions(+) create mode 100644 include/hw/intc/nios2_vic.h create mode 100644 hw/intc/nios2_vic.c diff --git a/include/hw/intc/nios2_vic.h b/include/hw/intc/nios2_vic.h new file mode 100644 index 0000000000..af1517a967 --- /dev/null +++ b/include/hw/intc/nios2_vic.h @@ -0,0 +1,64 @@ +/* + * Vectored Interrupt Controller for nios2 processor + * + * Copyright (c) 2022 Neuroblade + * + * Interface: + * QOM property "cpu": link to the Nios2 CPU (must be set) + * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines + * IRQ should be connected to nios2 IRQ0. + * + * Reference: "Embedded Peripherals IP User Guide + * for Intel® Quartus® Prime Design Suite: 21.4" + * Chapter 38 "Vectored Interrupt Controller Core" + * See: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_INTC_NIOS2_VIC +#define HW_INTC_NIOS2_VIC + +#define TYPE_NIOS2_VIC "nios2-vic" +OBJECT_DECLARE_SIMPLE_TYPE(Nios2VIC, NIOS2_VIC) + +#define NIOS2_VIC_MAX_IRQ 32 + +struct Nios2VIC { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + qemu_irq output_int; + + /* properties */ + CPUState *cpu; + MemoryRegion csr; + + uint32_t int_config[NIOS2_VIC_MAX_IRQ]; + uint32_t vic_config; + uint32_t int_raw_status; + uint32_t int_enable; + uint32_t sw_int; + uint32_t vic_status; + uint32_t vec_tbl_base; + uint32_t vec_tbl_addr; +}; + +#endif /* HW_INTC_NIOS2_VIC */ diff --git a/hw/intc/nios2_vic.c b/hw/intc/nios2_vic.c new file mode 100644 index 0000000000..cf63212a88 --- /dev/null +++ b/hw/intc/nios2_vic.c @@ -0,0 +1,313 @@ +/* + * Vectored Interrupt Controller for nios2 processor + * + * Copyright (c) 2022 Neuroblade + * + * Interface: + * QOM property "cpu": link to the Nios2 CPU (must be set) + * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines + * IRQ should be connected to nios2 IRQ0. + * + * Reference: "Embedded Peripherals IP User Guide + * for Intel® Quartus® Prime Design Suite: 21.4" + * Chapter 38 "Vectored Interrupt Controller Core" + * See: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" + +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "hw/intc/nios2_vic.h" +#include "cpu.h" + + +enum { + INT_CONFIG0 = 0, + INT_CONFIG31 = 31, + INT_ENABLE = 32, + INT_ENABLE_SET = 33, + INT_ENABLE_CLR = 34, + INT_PENDING = 35, + INT_RAW_STATUS = 36, + SW_INTERRUPT = 37, + SW_INTERRUPT_SET = 38, + SW_INTERRUPT_CLR = 39, + VIC_CONFIG = 40, + VIC_STATUS = 41, + VEC_TBL_BASE = 42, + VEC_TBL_ADDR = 43, + CSR_COUNT /* Last! */ +}; + +/* Requested interrupt level (INT_CONFIG[0:5]) */ +static inline uint32_t vic_int_config_ril(const Nios2VIC *vic, int irq_num) +{ + return extract32(vic->int_config[irq_num], 0, 6); +} + +/* Requested NMI (INT_CONFIG[6]) */ +static inline uint32_t vic_int_config_rnmi(const Nios2VIC *vic, int irq_num) +{ + return extract32(vic->int_config[irq_num], 6, 1); +} + +/* Requested register set (INT_CONFIG[7:12]) */ +static inline uint32_t vic_int_config_rrs(const Nios2VIC *vic, int irq_num) +{ + return extract32(vic->int_config[irq_num], 7, 6); +} + +static inline uint32_t vic_config_vec_size(const Nios2VIC *vic) +{ + return 1 << (2 + extract32(vic->vic_config, 0, 3)); +} + +static inline uint32_t vic_int_pending(const Nios2VIC *vic) +{ + return (vic->int_raw_status | vic->sw_int) & vic->int_enable; +} + +static void vic_update_irq(Nios2VIC *vic) +{ + Nios2CPU *cpu = NIOS2_CPU(vic->cpu); + uint32_t pending = vic_int_pending(vic); + int irq = -1; + int max_ril = 0; + /* Note that if RIL is 0 for an interrupt it is effectively disabled */ + + vic->vec_tbl_addr = 0; + vic->vic_status = 0; + + if (pending == 0) { + qemu_irq_lower(vic->output_int); + return; + } + + for (int i = 0; i < NIOS2_VIC_MAX_IRQ; i++) { + if (pending & BIT(i)) { + int ril = vic_int_config_ril(vic, i); + if (ril > max_ril) { + irq = i; + max_ril = ril; + } + } + } + + if (irq < 0) { + qemu_irq_lower(vic->output_int); + return; + } + + vic->vec_tbl_addr = irq * vic_config_vec_size(vic) + vic->vec_tbl_base; + vic->vic_status = irq | BIT(31); + + /* + * In hardware, the interface between the VIC and the CPU is via the + * External Interrupt Controller interface, where the interrupt controller + * presents the CPU with a packet of data containing: + * - Requested Handler Address (RHA): 32 bits + * - Requested Register Set (RRS) : 6 bits + * - Requested Interrupt Level (RIL) : 6 bits + * - Requested NMI flag (RNMI) : 1 bit + * In our emulation, we implement this by writing the data directly to + * fields in the CPU object and then raising the IRQ line to tell + * the CPU that we've done so. + */ + + cpu->rha = vic->vec_tbl_addr; + cpu->ril = max_ril; + cpu->rrs = vic_int_config_rrs(vic, irq); + cpu->rnmi = vic_int_config_rnmi(vic, irq); + + qemu_irq_raise(vic->output_int); +} + +static void vic_set_irq(void *opaque, int irq_num, int level) +{ + Nios2VIC *vic = opaque; + + vic->int_raw_status = deposit32(vic->int_raw_status, irq_num, 1, !!level); + vic_update_irq(vic); +} + +static void nios2_vic_reset(DeviceState *dev) +{ + Nios2VIC *vic = NIOS2_VIC(dev); + + memset(&vic->int_config, 0, sizeof(vic->int_config)); + vic->vic_config = 0; + vic->int_raw_status = 0; + vic->int_enable = 0; + vic->sw_int = 0; + vic->vic_status = 0; + vic->vec_tbl_base = 0; + vic->vec_tbl_addr = 0; +} + +static uint64_t nios2_vic_csr_read(void *opaque, hwaddr offset, unsigned size) +{ + Nios2VIC *vic = opaque; + int index = offset / 4; + + switch (index) { + case INT_CONFIG0 ... INT_CONFIG31: + return vic->int_config[index - INT_CONFIG0]; + case INT_ENABLE: + return vic->int_enable; + case INT_PENDING: + return vic_int_pending(vic); + case INT_RAW_STATUS: + return vic->int_raw_status; + case SW_INTERRUPT: + return vic->sw_int; + case VIC_CONFIG: + return vic->vic_config; + case VIC_STATUS: + return vic->vic_status; + case VEC_TBL_BASE: + return vic->vec_tbl_base; + case VEC_TBL_ADDR: + return vic->vec_tbl_addr; + default: + return 0; + } +} + +static void nios2_vic_csr_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + Nios2VIC *vic = opaque; + int index = offset / 4; + + switch (index) { + case INT_CONFIG0 ... INT_CONFIG31: + vic->int_config[index - INT_CONFIG0] = value; + break; + case INT_ENABLE: + vic->int_enable = value; + break; + case INT_ENABLE_SET: + vic->int_enable |= value; + break; + case INT_ENABLE_CLR: + vic->int_enable &= ~value; + break; + case SW_INTERRUPT: + vic->sw_int = value; + break; + case SW_INTERRUPT_SET: + vic->sw_int |= value; + break; + case SW_INTERRUPT_CLR: + vic->sw_int &= ~value; + break; + case VIC_CONFIG: + vic->vic_config = value; + break; + case VEC_TBL_BASE: + vic->vec_tbl_base = value; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "nios2-vic: write to invalid CSR address %#" + HWADDR_PRIx "\n", offset); + } + + vic_update_irq(vic); +} + +static const MemoryRegionOps nios2_vic_csr_ops = { + .read = nios2_vic_csr_read, + .write = nios2_vic_csr_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { .min_access_size = 4, .max_access_size = 4 } +}; + +static void nios2_vic_realize(DeviceState *dev, Error **errp) +{ + Nios2VIC *vic = NIOS2_VIC(dev); + + if (!vic->cpu) { + /* This is a programming error in the code using this device */ + error_setg(errp, "nios2-vic 'cpu' link property was not set"); + return; + } + + sysbus_init_irq(SYS_BUS_DEVICE(dev), &vic->output_int); + qdev_init_gpio_in(dev, vic_set_irq, NIOS2_VIC_MAX_IRQ); + + memory_region_init_io(&vic->csr, OBJECT(dev), &nios2_vic_csr_ops, vic, + "nios2.vic.csr", CSR_COUNT * sizeof(uint32_t)); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &vic->csr); +} + +static Property nios2_vic_properties[] = { + DEFINE_PROP_LINK("cpu", Nios2VIC, cpu, TYPE_CPU, CPUState *), + DEFINE_PROP_END_OF_LIST() +}; + +static const VMStateDescription nios2_vic_vmstate = { + .name = "nios2-vic", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]){ + VMSTATE_UINT32_ARRAY(int_config, Nios2VIC, 32), + VMSTATE_UINT32(vic_config, Nios2VIC), + VMSTATE_UINT32(int_raw_status, Nios2VIC), + VMSTATE_UINT32(int_enable, Nios2VIC), + VMSTATE_UINT32(sw_int, Nios2VIC), + VMSTATE_UINT32(vic_status, Nios2VIC), + VMSTATE_UINT32(vec_tbl_base, Nios2VIC), + VMSTATE_UINT32(vec_tbl_addr, Nios2VIC), + VMSTATE_END_OF_LIST() + }, +}; + +static void nios2_vic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = nios2_vic_reset; + dc->realize = nios2_vic_realize; + dc->vmsd = &nios2_vic_vmstate; + device_class_set_props(dc, nios2_vic_properties); +} + +static const TypeInfo nios2_vic_info = { + .name = TYPE_NIOS2_VIC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Nios2VIC), + .class_init = nios2_vic_class_init, +}; + +static void nios2_vic_register_types(void) +{ + type_register_static(&nios2_vic_info); +} + +type_init(nios2_vic_register_types); diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index ec8d4cec29..eeb2d6f428 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -84,3 +84,6 @@ config GOLDFISH_PIC config M68K_IRQC bool + +config NIOS2_VIC + bool diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 81ccdb0d78..167755ac64 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -62,3 +62,4 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c')) specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) +specific_ss.add(when: 'CONFIG_NIOS2_VIC', if_true: files('nios2_vic.c')) From patchwork Thu Mar 17 05:05:33 2022 Content-Type: text/plain; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id d10-20020a63360a000000b0037947abe4bbsm4217493pga.34.2022.03.16.22.09.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:09:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 46/51] hw/nios2: Introduce Nios2MachineState Date: Wed, 16 Mar 2022 22:05:33 -0700 Message-Id: <20220317050538.924111-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::635 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai, Mark Cave-Ayland Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We want to move data from the heap into Nios2MachineState, which is not possible with DEFINE_MACHINE. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- hw/nios2/10m50_devboard.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index 3d1205b8bd..bdc3ffd50d 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -36,6 +36,13 @@ #include "boot.h" +struct Nios2MachineState { + MachineState parent_obj; +}; + +#define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd") +OBJECT_DECLARE_TYPE(Nios2MachineState, MachineClass, NIOS2_MACHINE) + #define BINARY_DEVICE_TREE_FILE "10m50-devboard.dtb" static void nios2_10m50_ghrd_init(MachineState *machine) @@ -105,11 +112,24 @@ static void nios2_10m50_ghrd_init(MachineState *machine) BINARY_DEVICE_TREE_FILE, NULL); } -static void nios2_10m50_ghrd_machine_init(struct MachineClass *mc) +static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data) { + MachineClass *mc = MACHINE_CLASS(oc); + mc->desc = "Altera 10M50 GHRD Nios II design"; mc->init = nios2_10m50_ghrd_init; mc->is_default = true; } -DEFINE_MACHINE("10m50-ghrd", nios2_10m50_ghrd_machine_init); +static const TypeInfo nios2_10m50_ghrd_type_info = { + .name = TYPE_NIOS2_MACHINE, + .parent = TYPE_MACHINE, + .instance_size = sizeof(Nios2MachineState), + .class_init = nios2_10m50_ghrd_class_init, +}; + +static void nios2_10m50_ghrd_type_init(void) +{ + type_register_static(&nios2_10m50_ghrd_type_info); +} +type_init(nios2_10m50_ghrd_type_init); From patchwork Thu Mar 17 05:05:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552252 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp896697mag; Wed, 16 Mar 2022 22:58:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyzDWqbbe8hvIei/Q10gL8dHdJ0WROsEfAA/AB6UDpDBM7dlIcNYPVLh1BH9MYDolFAk5RP X-Received: by 2002:ac8:5743:0:b0:2e1:cee6:f15 with SMTP id 3-20020ac85743000000b002e1cee60f15mr2463510qtx.634.1647496735771; Wed, 16 Mar 2022 22:58:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647496735; cv=none; d=google.com; s=arc-20160816; b=RlxiPPWjorcDXSTG4kHuLrBwmZUXCxkfaGlGcQXZn/RPO/dCb9aTMqpCk+LLrNsp8X lbiGwz/MbCU7niPk+D+DmV8/GAH9ZsdR3c/6Hd6NwxOIA83rfE6M3q8YsVK8z8nX8KuO 1kz84XWAyOcspdJgczAmESZJASaBbZARS6xQJXCj3WvA0XMyXgcuM3nOW7uhbnAGI4yC H0gbyMPwomm2xyBHAyRk8X0H1/x/k6II19ofV4fFGKmeVjcjudU0ZhyE61xg5Y9dY+TJ tZBJ7KNxhQQhNQtssNILx+IOggqYeI5ZHBXL1gqoYyVRdXLVDHZ8XS1OEGLFZAXjPYWq kJCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=k4ozRW6iziM8OJ2TKPPCOH7wy/AQ7zg7VeU+iBKaQYA=; b=ZXZeg2tzD+J1Gg1N/BpfplnmhiTTqPS5mLRMLtFZoJjIIEmmHLHiZV4MG6bCga//e3 KzmfZrJ9fxW8Ol8rUZAiVO6ffk2wf5bVTigsTLFSEyCCxoN9uzssMiXdbF2B97xNxP7V kFXMIYiOY5sHqjbzlPFG5ePEvI6XNOe6FxHjafJm/mPoZZfD2dWdTBPjbgCEHJ9OhHMF hJfZPS6Jn6EknmKRxdY80PU7IcBTYlw0KLzO1DEnc9w906t8rETVf+J9FgulRTdEDz8e AMW6b4Zj2ZLQ6yYbCdgth73Pph//p8/vdDxdu7RCLt54oDcqqD9wVuvIqgIFiOQYfr9X Fqwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NnwZotdG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id d10-20020a63360a000000b0037947abe4bbsm4217493pga.34.2022.03.16.22.09.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:09:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 47/51] hw/nios2: Move memory regions into Nios2Machine Date: Wed, 16 Mar 2022 22:05:34 -0700 Message-Id: <20220317050538.924111-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai, Mark Cave-Ayland Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert to contiguous allocation, as much as possible so far. The two timer objects are not exposed for subobject allocation. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- hw/nios2/10m50_devboard.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index bdc3ffd50d..dda4ab2bf5 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -38,6 +38,11 @@ struct Nios2MachineState { MachineState parent_obj; + + MemoryRegion phys_tcm; + MemoryRegion phys_tcm_alias; + MemoryRegion phys_ram; + MemoryRegion phys_ram_alias; }; #define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd") @@ -47,13 +52,10 @@ OBJECT_DECLARE_TYPE(Nios2MachineState, MachineClass, NIOS2_MACHINE) static void nios2_10m50_ghrd_init(MachineState *machine) { + Nios2MachineState *nms = NIOS2_MACHINE(machine); Nios2CPU *cpu; DeviceState *dev; MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *phys_tcm = g_new(MemoryRegion, 1); - MemoryRegion *phys_tcm_alias = g_new(MemoryRegion, 1); - MemoryRegion *phys_ram = g_new(MemoryRegion, 1); - MemoryRegion *phys_ram_alias = g_new(MemoryRegion, 1); ram_addr_t tcm_base = 0x0; ram_addr_t tcm_size = 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */ ram_addr_t ram_base = 0x08000000; @@ -62,22 +64,22 @@ static void nios2_10m50_ghrd_init(MachineState *machine) int i; /* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */ - memory_region_init_ram(phys_tcm, NULL, "nios2.tcm", tcm_size, + memory_region_init_ram(&nms->phys_tcm, NULL, "nios2.tcm", tcm_size, &error_abort); - memory_region_init_alias(phys_tcm_alias, NULL, "nios2.tcm.alias", - phys_tcm, 0, tcm_size); - memory_region_add_subregion(address_space_mem, tcm_base, phys_tcm); + memory_region_init_alias(&nms->phys_tcm_alias, NULL, "nios2.tcm.alias", + &nms->phys_tcm, 0, tcm_size); + memory_region_add_subregion(address_space_mem, tcm_base, &nms->phys_tcm); memory_region_add_subregion(address_space_mem, 0xc0000000 + tcm_base, - phys_tcm_alias); + &nms->phys_tcm_alias); /* Physical DRAM with alias at 0xc0000000 */ - memory_region_init_ram(phys_ram, NULL, "nios2.ram", ram_size, + memory_region_init_ram(&nms->phys_ram, NULL, "nios2.ram", ram_size, &error_abort); - memory_region_init_alias(phys_ram_alias, NULL, "nios2.ram.alias", - phys_ram, 0, ram_size); - memory_region_add_subregion(address_space_mem, ram_base, phys_ram); + memory_region_init_alias(&nms->phys_ram_alias, NULL, "nios2.ram.alias", + &nms->phys_ram, 0, ram_size); + memory_region_add_subregion(address_space_mem, ram_base, &nms->phys_ram); memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base, - phys_ram_alias); + &nms->phys_ram_alias); /* Create CPU -- FIXME */ cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); From patchwork Thu Mar 17 05:05:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552253 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp897142mag; Wed, 16 Mar 2022 22:59:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzGkl1zlO5IYXEEOxKnDGL3Ta8rbjA4fq+vJUC4qqogQgweE18x3H9fk585ilfMjsgZ3cwL X-Received: by 2002:a05:620a:1084:b0:67b:2d99:8ac4 with SMTP id g4-20020a05620a108400b0067b2d998ac4mr1858135qkk.257.1647496797371; Wed, 16 Mar 2022 22:59:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647496797; cv=none; d=google.com; s=arc-20160816; b=ujNbVmQZBe9Gh+Oq8XhhBrrKvvpQlpB6KqB/2eM2Z9DsAHNhJj/VIMHQiNASKPIOA3 33xHGRAEmFToYWp14i+7o6qE8snVznrTruVcY+gqI817OKj4YhZj/W8Cpgqzb7x7g3EA WEufLwhwYGoJlINjNhfxCVOVLUnM2gGK60UImEsOeoqzVWYZ24Kq/1yv58mnA4eQjYZd fZDu6+8h2OBE3mGQxWAWCpM2bZUR/EET4Y72GZBDqUKxGwld83AHnzlMy7EY47JC8SzO zWR6ohiJmvHXQ79Ev3MttOgzpGfkXQYb/5rmaJwnSh8gdjoUBXHXjG7BnjwUgLdh9FGA lFlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hj1caAJ4c5FzLlx3YortGoGnXhKcBtSkJDGfqHCCy98=; b=wiaGpzrH6ZZYjpvNeeKZuhRZIyXX0ZN0fM/QuMqR89KKdNsbI6+81O3jmVb1banhYR 1YBlc9OoBG3ppVaynT0vpz1mQrf64p+CrBhp5bQsEGlKoSpitFNUt7WxPRt9kzS9DMUd 82gwl2cuilcYEAmtaJ5VGZ+MRJWEWYnwaof6kOaS22h1goR32avU3gMEMEwt/2GkzUUx U0/gWJze62Sr9N0AcdE2uJtC4gNY9s7YM3bPwCJc84XSFhK065toHpIjBNRXsVF5zT81 em67rdV2AeRMG17VTpCDrnX9H5jotVXuvxpOM6AJo18ikkIv9rsOvKxvKbTRxTXqX0TO JBsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uTUkKmda; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id d10-20020a63360a000000b0037947abe4bbsm4217493pga.34.2022.03.16.22.09.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:09:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 48/51] hw/nios2: Machine with a Vectored Interrupt Controller Date: Wed, 16 Mar 2022 22:05:35 -0700 Message-Id: <20220317050538.924111-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1030 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai, Mark Cave-Ayland Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Amir Gonnen Demonstrate how to use nios2 VIC on a machine. Introduce a new machine property to attach a VIC. When VIC is present, let the CPU know that it should use the External Interrupt Interface instead of the Internal Interrupt Interface. The devices on the machine are attached to the VIC and not directly to cpu. To allow VIC update EIC fields, we set the "cpu" property of the VIC with a reference to the nios2 cpu. Reviewed-by: Mark Cave-Ayland Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-6-amir.gonnen@neuroblade.ai> [rth: Put a property on the 10m50-ghrd machine, rather than create a new machine class.] Signed-off-by: Richard Henderson --- hw/nios2/10m50_devboard.c | 61 +++++++++++++++++++++++++++++++++------ hw/nios2/Kconfig | 1 + 2 files changed, 53 insertions(+), 9 deletions(-) diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index dda4ab2bf5..91383fb097 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -27,6 +27,7 @@ #include "hw/sysbus.h" #include "hw/char/serial.h" +#include "hw/intc/nios2_vic.h" #include "hw/qdev-properties.h" #include "sysemu/sysemu.h" #include "hw/boards.h" @@ -43,6 +44,8 @@ struct Nios2MachineState { MemoryRegion phys_tcm_alias; MemoryRegion phys_ram; MemoryRegion phys_ram_alias; + + bool vic; }; #define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd") @@ -81,10 +84,39 @@ static void nios2_10m50_ghrd_init(MachineState *machine) memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base, &nms->phys_ram_alias); - /* Create CPU -- FIXME */ - cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); - for (i = 0; i < 32; i++) { - irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); + /* Create CPU. We need to set eic_present between init and realize. */ + cpu = NIOS2_CPU(object_new(TYPE_NIOS2_CPU)); + + /* Enable the External Interrupt Controller within the CPU. */ + cpu->eic_present = nms->vic; + + /* Configure new exception vectors. */ + cpu->reset_addr = 0xd4000000; + cpu->exception_addr = 0xc8000120; + cpu->fast_tlb_miss_addr = 0xc0000100; + + qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); + + if (nms->vic) { + DeviceState *dev = qdev_new(TYPE_NIOS2_VIC); + MemoryRegion *dev_mr; + qemu_irq cpu_irq; + + object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + cpu_irq = qdev_get_gpio_in_named(DEVICE(cpu), "EIC", 0); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq); + for (int i = 0; i < 32; i++) { + irq[i] = qdev_get_gpio_in(dev, i); + } + + dev_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(address_space_mem, 0x18002000, dev_mr); + } else { + for (i = 0; i < 32; i++) { + irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); + } } /* Register: Altera 16550 UART */ @@ -105,15 +137,22 @@ static void nios2_10m50_ghrd_init(MachineState *machine) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]); - /* Configure new exception vectors and reset CPU for it to take effect. */ - cpu->reset_addr = 0xd4000000; - cpu->exception_addr = 0xc8000120; - cpu->fast_tlb_miss_addr = 0xc0000100; - nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename, BINARY_DEVICE_TREE_FILE, NULL); } +static bool get_vic(Object *obj, Error **errp) +{ + Nios2MachineState *nms = NIOS2_MACHINE(obj); + return nms->vic; +} + +static void set_vic(Object *obj, bool value, Error **errp) +{ + Nios2MachineState *nms = NIOS2_MACHINE(obj); + nms->vic = value; +} + static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -121,6 +160,10 @@ static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data) mc->desc = "Altera 10M50 GHRD Nios II design"; mc->init = nios2_10m50_ghrd_init; mc->is_default = true; + + object_class_property_add_bool(oc, "vic", get_vic, set_vic); + object_class_property_set_description(oc, "vic", + "Set on/off to enable/disable the Vectored Interrupt Controller"); } static const TypeInfo nios2_10m50_ghrd_type_info = { diff --git a/hw/nios2/Kconfig b/hw/nios2/Kconfig index b10ea640da..4748ae27b6 100644 --- a/hw/nios2/Kconfig +++ b/hw/nios2/Kconfig @@ -3,6 +3,7 @@ config NIOS2_10M50 select NIOS2 select SERIAL select ALTERA_TIMER + select NIOS2_VIC config NIOS2_GENERIC_NOMMU bool From patchwork Thu Mar 17 05:05:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552254 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp898265mag; Wed, 16 Mar 2022 23:01:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzCCTJbPQ/DQ7rmtSJ4fr+cxL2JtMgwrmDEkvL1NxC05xXehf5ddvKHeKeOMafbUfhyBNXz X-Received: by 2002:a0c:be89:0:b0:42c:4194:6adb with SMTP id n9-20020a0cbe89000000b0042c41946adbmr2006776qvi.6.1647496904666; Wed, 16 Mar 2022 23:01:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647496904; cv=none; d=google.com; s=arc-20160816; b=phMNg1sSyiV60ZOxX238P0wYmh1uv339TL9sDktvbodkatJ1xi8mtnnxc7XqWVIZXU BWacmzPuWMQ+Yg0rFEgjQQv9B4Irm9UH+9mr/+TpDozh05LMsa0WGG9iMd4Sk7klMCU+ t8oxZMUJ0RlzfJn5DBslAIOQIgZs+PEZhBCVVFxTzrFUj7iOw76uI+AyzppyOWma/NbV NkiD6K7eBMOtBg3+PwR+YHln6U8LP+QDBBS5NdyWUzhRbxexdZhjYvsAqKKk6tFHEWYi s+l9iyC7Qe0kegGdDXGrBr7bxXtU/E/0Kpo1yertLd7oKfIbkg2LKixGPFLpunI5MBun S8QA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7rlZYzlv15UW77j9fostPaSd5V7tg5ruWK95qVptaMo=; b=mjTJPIzmjzbsu/4nLshehY7gnrWmiRI48gam72/a4E1JbksBTMb/KD2SxWKBZWmd2f 77Y0MmP5hWDl/P9JOObfVPPKoA32DIbnwbiqH2q9hnTHanbIzIjvXrEvW72QCWftf87S JdALhQ2XwKS90er42+TqByAZKzvOCYJgAjkuKMS5Oq3G+ORLsF0U6ADFL23A+4GANeTt SUCujiN5KyyYpwK/QKVGfAsb5mB5YUYfjuyeAtBUQqUL9VXgrBz5q3oQCGo0O7YrJE5d zthUGIsecAP9tMpApqhveknUCetP7Ka/zk0WbcH6rMA9uW8EPdpXpVBIoIYdOpTyTZqr NbaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dsN2bSRz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id d10-20020a63360a000000b0037947abe4bbsm4217493pga.34.2022.03.16.22.09.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:09:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 49/51] tests/tcg: Expose AR to test build environment if needed Date: Wed, 16 Mar 2022 22:05:36 -0700 Message-Id: <20220317050538.924111-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The runtime we build for Nios2 requires building a static archive, so supply the ar tool for that case. Cc: Alex Bennée Signed-off-by: Richard Henderson --- tests/tcg/Makefile.qemu | 7 +++++++ tests/tcg/configure.sh | 14 ++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/tests/tcg/Makefile.qemu b/tests/tcg/Makefile.qemu index 84c8543878..00b043c702 100644 --- a/tests/tcg/Makefile.qemu +++ b/tests/tcg/Makefile.qemu @@ -24,6 +24,7 @@ quiet-command = $(quiet-@)$(call quiet-command-run,$1,$2,$3) CROSS_CC_GUEST:= CROSS_AS_GUEST:= CROSS_LD_GUEST:= +CROSS_AR_GUEST:= DOCKER_IMAGE:= -include tests/tcg/config-$(TARGET).mak @@ -46,6 +47,7 @@ cross-build-guest-tests: $(MAKE) -f $(TCG_MAKE) TARGET="$(TARGET)" CC="$(CROSS_CC_GUEST)" \ $(if $(CROSS_AS_GUEST),AS="$(CROSS_AS_GUEST)") \ $(if $(CROSS_LD_GUEST),LD="$(CROSS_LD_GUEST)") \ + $(if $(CROSS_AR_GUEST),AR="$(CROSS_AR_GUEST)") \ SRC_PATH="$(SRC_PATH)" BUILD_STATIC=$(CROSS_CC_GUEST_STATIC) \ EXTRA_CFLAGS="$(CROSS_CC_GUEST_CFLAGS)"), \ "BUILD","$(TARGET) guest-tests with $(CROSS_CC_GUEST)") @@ -73,6 +75,10 @@ DOCKER_LD_CMD=$(if $(DOCKER_CROSS_LD_GUEST),"$(DOCKER_SCRIPT) cc \ -i qemu/$(DOCKER_IMAGE) \ -s $(SRC_PATH) -- ") +DOCKER_AR_CMD=$(if $(DOCKER_CROSS_AR_GUEST),"$(DOCKER_SCRIPT) cc \ + --cc $(DOCKER_CROSS_AR_GUEST) \ + -i qemu/$(DOCKER_IMAGE) \ + -s $(SRC_PATH) -- ") .PHONY: docker-build-guest-tests docker-build-guest-tests: docker-image-$(DOCKER_IMAGE) @@ -81,6 +87,7 @@ docker-build-guest-tests: docker-image-$(DOCKER_IMAGE) $(MAKE) -f $(TCG_MAKE) TARGET="$(TARGET)" CC=$(DOCKER_COMPILE_CMD) \ $(if $(DOCKER_AS_CMD),AS=$(DOCKER_AS_CMD)) \ $(if $(DOCKER_LD_CMD),LD=$(DOCKER_LD_CMD)) \ + $(if $(DOCKER_AR_CMD),AR=$(DOCKER_AR_CMD)) \ SRC_PATH="$(SRC_PATH)" BUILD_STATIC=y \ EXTRA_CFLAGS="$(CROSS_CC_GUEST_CFLAGS)"), \ "BUILD","$(TARGET) guest-tests with docker qemu/$(DOCKER_IMAGE)") diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index ed4b5ccb1f..0b829f4f05 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -80,6 +80,9 @@ fi : ${cross_as_tricore="tricore-as"} : ${cross_ld_tricore="tricore-ld"} +# nios2 is special as it requires ar +: ${cross_ar_nios2="nios2-linux-gnu-ar"} + for target in $target_list; do arch=${target%%-*} @@ -89,6 +92,7 @@ for target in $target_list; do container_cross_cc= container_cross_as= container_cross_ld= + container_cross_ar= # suppress clang supress_clang= @@ -166,6 +170,7 @@ for target in $target_list; do container_hosts=x86_64 container_image=debian-nios2-cross container_cross_cc=nios2-linux-gnu-gcc + container_cross_ar=nios2-linux-gnu-ar ;; ppc-*) container_hosts=x86_64 @@ -285,6 +290,11 @@ for target in $target_list; do ;; esac fi + + eval "target_ar=\"\${cross_ar_$arch}\"" + if has $target_ar; then + echo "CROSS_AR_GUEST=$target_ar" >> $config_target_mak + fi fi if test $got_cross_cc = yes; then @@ -344,6 +354,10 @@ for target in $target_list; do echo "DOCKER_CROSS_LD_GUEST=$container_cross_ld" >> \ $config_target_mak fi + if test -n "$container_cross_ar"; then + echo "DOCKER_CROSS_AR_GUEST=$container_cross_ar" >> \ + $config_target_mak + fi fi done fi From patchwork Thu Mar 17 05:05:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552247 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp893960mag; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id d10-20020a63360a000000b0037947abe4bbsm4217493pga.34.2022.03.16.22.09.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:09:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 50/51] test/tcg/nios2: Add semihosting multiarch tests Date: Wed, 16 Mar 2022 22:05:37 -0700 Message-Id: <20220317050538.924111-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1033 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add runtime supporting the nios2-semi.c interface. Execute the hello and memory multiarch tests. Cc: Alex Bennée Signed-off-by: Richard Henderson --- tests/tcg/nios2/semicall.h | 25 +++++++ tests/tcg/nios2/10m50-ghrd.ld | 59 +++++++++++++++++ tests/tcg/nios2/Makefile.softmmu-target | 32 +++++++++ tests/tcg/nios2/ml-ftm.S | 20 ++++++ tests/tcg/nios2/ml-intr.S | 21 ++++++ tests/tcg/nios2/ml-memcpy.S | 68 +++++++++++++++++++ tests/tcg/nios2/ml-memset.S | 88 +++++++++++++++++++++++++ tests/tcg/nios2/ml-outc.S | 31 +++++++++ tests/tcg/nios2/ml-start.S | 46 +++++++++++++ 9 files changed, 390 insertions(+) create mode 100644 tests/tcg/nios2/semicall.h create mode 100644 tests/tcg/nios2/10m50-ghrd.ld create mode 100644 tests/tcg/nios2/Makefile.softmmu-target create mode 100644 tests/tcg/nios2/ml-ftm.S create mode 100644 tests/tcg/nios2/ml-intr.S create mode 100644 tests/tcg/nios2/ml-memcpy.S create mode 100644 tests/tcg/nios2/ml-memset.S create mode 100644 tests/tcg/nios2/ml-outc.S create mode 100644 tests/tcg/nios2/ml-start.S diff --git a/tests/tcg/nios2/semicall.h b/tests/tcg/nios2/semicall.h new file mode 100644 index 0000000000..d7acf665e1 --- /dev/null +++ b/tests/tcg/nios2/semicall.h @@ -0,0 +1,25 @@ +/* + * Nios2 semihosting interface. + */ + +#ifndef SEMICALL_H +#define SEMICALL_H + +#define HOSTED_EXIT 0 +#define HOSTED_INIT_SIM 1 +#define HOSTED_OPEN 2 +#define HOSTED_CLOSE 3 +#define HOSTED_READ 4 +#define HOSTED_WRITE 5 +#define HOSTED_LSEEK 6 +#define HOSTED_RENAME 7 +#define HOSTED_UNLINK 8 +#define HOSTED_STAT 9 +#define HOSTED_FSTAT 10 +#define HOSTED_GETTIMEOFDAY 11 +#define HOSTED_ISATTY 12 +#define HOSTED_SYSTEM 13 + +#define semihosting_call break 1 + +#endif /* SEMICALL_H */ diff --git a/tests/tcg/nios2/10m50-ghrd.ld b/tests/tcg/nios2/10m50-ghrd.ld new file mode 100644 index 0000000000..d83e136267 --- /dev/null +++ b/tests/tcg/nios2/10m50-ghrd.ld @@ -0,0 +1,59 @@ +MEMORY +{ + tpf (rx) : ORIGIN = 0xc0000000, LENGTH = 1K + ram (rwx) : ORIGIN = 0xc8000000, LENGTH = 128M +} + +PHDRS +{ + RAM PT_LOAD; +} + +ENTRY(_start) +EXTERN(_start) +EXTERN(_interrupt) +EXTERN(_fast_tlb_miss) + +SECTIONS +{ + /* Begin at the (hardcoded) _interrupt entry point. */ + .text 0xc8000120 : { + *(.text.intr) + *(.text .text.* .gnu.linkonce.t.*) + } >ram :RAM + + .rodata : ALIGN(4) { + *(.rodata .rodata.* .gnu.linkonce.r.*) + } > ram :RAM + + .eh_frame_hdr : ALIGN (4) { + KEEP (*(.eh_frame_hdr)) + *(.eh_frame_entry .eh_frame_entry.*) + } >ram :RAM + .eh_frame : ALIGN (4) { + KEEP (*(.eh_frame)) *(.eh_frame.*) + } >ram :RAM + + .data : ALIGN(4) { + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN(4); + _gp = ABSOLUTE(. + 0x8000); + *(.got.plt) *(.got) + *(.lit8) + *(.lit4) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } >ram :RAM + + .bss : ALIGN(4) { + __bss_start = ABSOLUTE(.); + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + __bss_end = ABSOLUTE(.); + } >ram :RAM + + __stack = ORIGIN(ram) + LENGTH(ram); +} diff --git a/tests/tcg/nios2/Makefile.softmmu-target b/tests/tcg/nios2/Makefile.softmmu-target new file mode 100644 index 0000000000..20d8d143c6 --- /dev/null +++ b/tests/tcg/nios2/Makefile.softmmu-target @@ -0,0 +1,32 @@ +# +# Nios2 system tests +# + +NIOS2_SYSTEM_SRC = $(SRC_PATH)/tests/tcg/nios2 +VPATH += $(NIOS2_SYSTEM_SRC) + +# These objects provide the basic boot code and helper functions for all tests +CRT_OBJS = minilib.a +LINK_SCRIPT = $(NIOS2_SYSTEM_SRC)/10m50-ghrd.ld + +CFLAGS += -nostdlib -g -O0 $(MINILIB_INC) +LDFLAGS += -Wl,-T$(LINK_SCRIPT) -static -nostdlib $(CRT_OBJS) -lgcc + +%.o: %.S + $(call quiet-command, $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -x assembler-with-cpp -c $< -o $@, AS, $@) + +%.o: %.c + $(call quiet-command, $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@, CC, $@) + +minilib.a: ml-intr.o ml-start.o ml-ftm.o ml-outc.o ml-memcpy.o ml-memset.o $(MINILIB_OBJS) + $(call quiet-command, $(AR) cqs $@ $^, AR, $@) + +# Build and link the tests +%: %.o $(LINK_SCRIPT) $(CRT_OBJS) + $(call quiet-command, $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS), LD, $@) + +# FIXME: nios2 semihosting writes to stdout, not a chardev +QEMU_OPTS = -M 10m50-ghrd,vic=on -semihosting >$@.out -kernel + +memory: CFLAGS+=-DCHECK_UNALIGNED=0 +TESTS += $(MULTIARCH_TESTS) diff --git a/tests/tcg/nios2/ml-ftm.S b/tests/tcg/nios2/ml-ftm.S new file mode 100644 index 0000000000..e21da45be5 --- /dev/null +++ b/tests/tcg/nios2/ml-ftm.S @@ -0,0 +1,20 @@ +/* + * Minimal Nios2 system boot code. + * + * Copyright Linaro Ltd 2022 + * + * Using semihosting for serial output and exit functions. + */ + +#include "semicall.h" + + .text + .global _fast_tlb_miss + .type _fast_tlb_miss, @function + +_fast_tlb_miss: + movi r5, 32 + movi r4, HOSTED_EXIT + semihosting_call + + .size _fast_tlb_miss, . - _fast_tlb_miss diff --git a/tests/tcg/nios2/ml-intr.S b/tests/tcg/nios2/ml-intr.S new file mode 100644 index 0000000000..b5a56c686c --- /dev/null +++ b/tests/tcg/nios2/ml-intr.S @@ -0,0 +1,21 @@ +/* + * Minimal Nios2 system boot code. + * + * Copyright Linaro Ltd 2022 + * + * Using semihosting for serial output and exit functions. + */ + +#include "semicall.h" + + .section .text.intr, "ax" + .global _interrupt + .type _interrupt, @function + +_interrupt: + rdctl r5, exception /* extract exception.CAUSE */ + srli r5, r5, 2 + movi r4, HOSTED_EXIT + semihosting_call + + .size _interrupt, . - _interrupt diff --git a/tests/tcg/nios2/ml-memcpy.S b/tests/tcg/nios2/ml-memcpy.S new file mode 100644 index 0000000000..8bdd934503 --- /dev/null +++ b/tests/tcg/nios2/ml-memcpy.S @@ -0,0 +1,68 @@ +/* + * Minimal Nios2 system minilib code: memcpy + * Copyright Linaro Ltd 2022 + */ + + .set noat + + .text + .global memcpy + .type memcpy, @function + +#define dst r4 +#define src r5 +#define len r6 + +memcpy: + /* Store return value right away, per API */ + mov r2, dst + + /* Check for both dst and src aligned. */ + or at, dst, src + andi at, at, 3 + bne at, zero, .L_test1 + + /* Copy blocks of 8. */ + + movi at, 8 + bltu len, at, .L_test4 + +.L_loop8: + ldw r8, 0(src) + ldw r9, 4(src) + addi src, src, 8 + addi dst, dst, 8 + subi len, len, 8 + stw r8, -8(dst) + stw r9, -4(dst) + bgeu len, at, .L_loop8 + + /* Copy final aligned block of 4. */ + +.L_test4: + movi at, 4 + bltu len, at, .L_test1 + + ldw r8, 0(src) + addi src, src, 4 + addi dst, dst, 4 + subi len, len, 4 + stw r8, -4(dst) + + /* Copy single bytes to finish. */ + +.L_test1: + beq len, zero, .L_done + +.L_loop1: + ldb r8, 0(src) + addi src, src, 1 + addi dst, dst, 1 + subi len, len, 1 + stb r8, -1(dst) + bne len, zero, .L_loop1 + +.L_done: + ret + + .size memcpy, . - memcpy diff --git a/tests/tcg/nios2/ml-memset.S b/tests/tcg/nios2/ml-memset.S new file mode 100644 index 0000000000..5c9bdde3e0 --- /dev/null +++ b/tests/tcg/nios2/ml-memset.S @@ -0,0 +1,88 @@ +/* + * Minimal Nios2 system minilib code: memset + * Copyright Linaro Ltd 2022 + */ + + .set noat + + .text + .global memset + .type memset, @function + +#define dst r4 +#define val r5 +#define len r6 + +memset: + /* Store return value right away, per API */ + mov r2, dst + + /* Check for small blocks; fall back to bytewise. */ + movi r3, 8 + bltu len, r3, .L_test1 + + /* Replicate the byte across the word. */ + andi val, val, 0xff + slli at, val, 8 + or val, val, at + slli at, val, 16 + or val, val, at + + /* Check for destination alignment; realign if needed. */ + andi at, dst, 3 + bne at, zero, .L_align + + /* Set blocks of 8. */ + +.L_loop8: + stw val, 0(dst) + stw val, 4(dst) + addi dst, dst, 8 + subi len, len, 8 + bgeu len, r3, .L_loop8 + + /* Set final aligned block of 4. */ + +.L_test4: + movi at, 4 + bltu len, at, .L_test1 + + stw r8, 0(dst) + addi dst, dst, 4 + subi len, len, 4 + stw r8, -4(dst) + + /* Set single bytes to finish. */ + +.L_test1: + beq len, zero, .L_done + +.L_loop1: + stb r8, 0(dst) + addi dst, dst, 1 + subi len, len, 1 + bne len, zero, .L_loop1 + +.L_done: + ret + + /* Realign for a large block, len >= 8. */ +.L_align: + andi at, dst, 1 + beq at, zero, 2f + + stb val, 0(dst) + addi dst, dst, 1 + subi len, len, 1 + +2: andi at, dst, 2 + beq at, zero, 4f + + sth val, 0(dst) + addi dst, dst, 2 + subi len, len, 2 + +4: bgeu len, r3, .L_loop8 + br .L_test4 + + .size memset, . - memset diff --git a/tests/tcg/nios2/ml-outc.S b/tests/tcg/nios2/ml-outc.S new file mode 100644 index 0000000000..e13f0f2581 --- /dev/null +++ b/tests/tcg/nios2/ml-outc.S @@ -0,0 +1,31 @@ +/* + * Minimal Nios2 system minilib code: __sys_outc + * Copyright Linaro Ltd 2022 + */ + +#include "semicall.h" + + .text + .global __sys_outc + .type __sys_outc, @function + .set noat + +/* + * void __sys_outc(char c); + */ +__sys_outc: + subi sp, sp, 16 + stb r4, 0(sp) /* buffer[0] = c */ + movi at, 1 + stw at, 4(sp) /* STDOUT_FILENO */ + stw sp, 8(sp) /* buffer */ + stw at, 12(sp) /* len */ + + movi r4, HOSTED_WRITE + addi r5, sp, 4 + semihosting_call + + addi sp, sp, 16 + ret + + .size __sys_outc, . - __sys_outc diff --git a/tests/tcg/nios2/ml-start.S b/tests/tcg/nios2/ml-start.S new file mode 100644 index 0000000000..68b612d70b --- /dev/null +++ b/tests/tcg/nios2/ml-start.S @@ -0,0 +1,46 @@ +/* + * Minimal Nios2 system boot code. + * Copyright Linaro Ltd 2022 + */ + +#include "semicall.h" + + .text + .set noat + +_start: + /* Linker script defines stack at end of ram. */ + movia sp, __stack + + /* Install trampoline to _fast_tlb_miss at hardcoded vector. */ + movia r4, 0xc0000100 + movia r5, _ftm_tramp + movi r6, .L__ftm_end - _ftm_tramp + call memcpy + + /* Zero the bss to satisfy C. */ + movia r4, __bss_start + movia r6, __bss_end + sub r6, r6, r4 + movi r5, 0 + call memset + + /* Test! */ + call main + + /* Exit with main's return value. */ + movi r4, HOSTED_EXIT + mov r5, r2 + semihosting_call + + .globl _start + .type _start, @function + .size _start, . - _start + +_ftm_tramp: + movia et, _fast_tlb_miss + jmp et +.L__ftm_end: + + .type _ftm_tramp, @function + .size _ftm_tramp, . - _ftm_tramp From patchwork Thu Mar 17 05:05:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 552255 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp898865mag; Wed, 16 Mar 2022 23:02:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzev21jvhMLex9ZkerhQtSkcqognf2C8NHbDN3T7Fh+9uPnFNZ9qCtEIyqW5/EeZNnx60s6 X-Received: by 2002:a05:620a:11:b0:508:7199:40ef with SMTP id j17-20020a05620a001100b00508719940efmr1891864qki.62.1647496970775; Wed, 16 Mar 2022 23:02:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647496970; cv=none; d=google.com; s=arc-20160816; b=T6gq71VjHRCGZuUAtR+vzQ6p5FhxfbhxBzVoMMru/gSjYUpIzCIQvhs9Bo01UwRTIx u8+8CPmPwFvtCk3UFJO1p/0+hqz5J1yO75UWRoNr71UGmjka83ZVaD7UUAfsKGaTNCCb YAsz/vLP6ZYvfbH/iq9H4y5NxZkdRoc/uD5PnPNffcnyG5STYOCgq6kWpSfLicXppGSf sXeGLU68a1yBqpNVeRH0QW6LPMxKg8T0aB5VBnPJ5cmpBzohXCwhx6A2d66202AWlEDW z3n3KCmgyWXVltWDBAIizhbZGmZQFBAfZoNvaiKgkejHgp2l8x7Dc/OMXR6Pk3MWbjH/ F4lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IvBEhqppOoPljEvawEk60xBsH14k/3nhv0YU5DA6zfM=; b=mKRdSCL2W5GDBKppDtLKqEZu4ykgW6Onw/Sk0LTMN+kqHMfWI1MXUfHSGb7WcteMUh sELxOckvwEpgZ6DCq4QkUWDiVz3ckfJmUthtDZYoohrrpJp2+82Ju+wuw8J5/5meAYd5 SNuLDQP8qiAZiye0stEpYdvlKMHjy+FeOT+FmIERFNux6OzLiT7Wy55ghF6MjuDxX7AX UWF+pdhLDCB0KQCw7UhBuK0DzCY9Eyla5sSl0sgwKNPBkb+yuELCv3sG/JlLRfkbN1OD Nw8crYpo/WP4y5HICx4hvviWnQOvWBrE8mSSYKffCAZRG3haCF78IYLYxPDIvrV6h4Gz T7wA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VIXuo5Vn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id d10-20020a63360a000000b0037947abe4bbsm4217493pga.34.2022.03.16.22.09.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:09:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-7.1 v6 51/51] tests/tcg/nios2: Add test-shadow-1 Date: Wed, 16 Mar 2022 22:05:38 -0700 Message-Id: <20220317050538.924111-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org> References: <20220317050538.924111-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a regression test for tcg indirect global lowering. This appeared with nios2, with cps != 0, so that we use indirection into the shadow register set. An indirect call verifies alignment of rA. The use of rA was live across the brcond leading to a tcg_debug_assert failure. Cc: Alex Bennée Signed-off-by: Richard Henderson --- tests/tcg/nios2/Makefile.softmmu-target | 1 + tests/tcg/nios2/test-shadow-1.S | 37 +++++++++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 tests/tcg/nios2/test-shadow-1.S diff --git a/tests/tcg/nios2/Makefile.softmmu-target b/tests/tcg/nios2/Makefile.softmmu-target index 20d8d143c6..48863549c9 100644 --- a/tests/tcg/nios2/Makefile.softmmu-target +++ b/tests/tcg/nios2/Makefile.softmmu-target @@ -30,3 +30,4 @@ QEMU_OPTS = -M 10m50-ghrd,vic=on -semihosting >$@.out -kernel memory: CFLAGS+=-DCHECK_UNALIGNED=0 TESTS += $(MULTIARCH_TESTS) +TESTS += test-shadow-1 diff --git a/tests/tcg/nios2/test-shadow-1.S b/tests/tcg/nios2/test-shadow-1.S new file mode 100644 index 0000000000..33076ddf59 --- /dev/null +++ b/tests/tcg/nios2/test-shadow-1.S @@ -0,0 +1,37 @@ +/* + * Regresion test for TCG indirect global lowering. + */ + +#include "semicall.h" + + .text + .set noat + .align 2 + .globl main + .type main, @function + +main: + /* Initialize r0 in shadow register set 1. */ + movhi at, 1 /* PRS=1, CRS=0, RSIE=0, PIE=0 */ + wrctl status, at + wrprs zero, zero + + /* Change current register set to 1. */ + movi at, 1 << 10 /* PRS=0, CRS=1, RSIE=0, PIE=0 */ + wrctl estatus, at + movia ea, 1f + eret + + /* Load address for callr, then end TB. */ +1: movia at, 3f + br 2f + + /* Test case! TCG abort on indirect lowering across brcond. */ +2: callr at + + /* exit(0) */ +3: movi r4, HOSTED_EXIT + movi r5, 0 + semihosting_call + + .size main, . - main