From patchwork Tue Mar 15 06:10:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 552029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2810C433EF for ; Tue, 15 Mar 2022 06:11:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345166AbiCOGM5 (ORCPT ); Tue, 15 Mar 2022 02:12:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345188AbiCOGMx (ORCPT ); Tue, 15 Mar 2022 02:12:53 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D78849FA2; Mon, 14 Mar 2022 23:11:41 -0700 (PDT) X-UUID: d9b996eea0854495aecfde7b79bc38f2-20220315 X-UUID: d9b996eea0854495aecfde7b79bc38f2-20220315 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 753537765; Tue, 15 Mar 2022 14:11:27 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 15 Mar 2022 14:11:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Mar 2022 14:11:25 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Hans Verkuil , Jernej Skrabec CC: Chun-Kuang Hu , Geert Uytterhoeven , Rob Landley , Laurent Pinchart , , , , , , Alexandre Courbot , , , , , AngeloGioacchino Del Regno , Maoguang Meng , daoyuan huang , Ping-Hsun Wu , , , , , , , , , , Subject: [PATCH v13 1/6] soc: mediatek: mutex: add common interface to accommodate multiple modules operationg MUTEX Date: Tue, 15 Mar 2022 14:10:26 +0800 Message-ID: <20220315061031.21642-2-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220315061031.21642-1-moudy.ho@mediatek.com> References: <20220315061031.21642-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In order to allow multiple modules to operate MUTEX hardware through a common interfrace, a flexible index "mtk_mutex_table_index" needs to be added to replace original component ID so that like DDP and MDP can add their own MUTEX table settings independently. In addition, 4 generic interface "mtk_mutex_set_mod", "mtk_mutex_set_sof", "mtk_mutex_clear_mod" and "mtk_mutex_clear_sof" have been added, which is expected to replace the "mtk_mutex_add_comp" and "mtk_mutex_remove_comp" pair originally dedicated to DDP in the future. Signed-off-by: Moudy Ho --- drivers/soc/mediatek/mtk-mutex.c | 122 +++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-mutex.h | 33 +++++++ 2 files changed, 155 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index aaf8fc1abb43..778b01ce9e8f 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -156,6 +156,7 @@ struct mtk_mutex_data { const unsigned int *mutex_sof; const unsigned int mutex_mod_reg; const unsigned int mutex_sof_reg; + const unsigned long long *mutex_table_mod; const bool no_clk; }; @@ -445,6 +446,84 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, } EXPORT_SYMBOL_GPL(mtk_mutex_add_comp); +void mtk_mutex_set_mod(struct mtk_mutex *mutex, + enum mtk_mutex_table_index idx) +{ + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + unsigned int reg; + unsigned int offset; + + WARN_ON(&mtx->mutex[mutex->id] != mutex); + + if (idx == MUTEX_TABLE_IDX_NONE || + idx >= MUTEX_TABLE_IDX_MAX) + return; + + if (mtx->data->mutex_table_mod[idx] <= BIT(31)) { + offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, + mutex->id); + reg = readl_relaxed(mtx->regs + offset); + reg |= mtx->data->mutex_table_mod[idx]; + writel_relaxed(reg, mtx->regs + offset); + } else { + offset = DISP_REG_MUTEX_MOD2(mutex->id); + reg = readl_relaxed(mtx->regs + offset); + reg |= (mtx->data->mutex_table_mod[idx] >> 32); + writel_relaxed(reg, mtx->regs + offset); + } +} +EXPORT_SYMBOL_GPL(mtk_mutex_set_mod); + +void mtk_mutex_set_sof(struct mtk_mutex *mutex, + enum mtk_mutex_table_index idx) +{ + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + unsigned int sof_id; + + WARN_ON(&mtx->mutex[mutex->id] != mutex); + + if (idx == MUTEX_TABLE_IDX_NONE || + idx >= MUTEX_TABLE_IDX_MAX) + return; + + switch (idx) { + case MUTEX_TABLE_IDX_DDP_DSI0: + sof_id = MUTEX_SOF_DSI0; + break; + case MUTEX_TABLE_IDX_DDP_DSI1: + sof_id = MUTEX_SOF_DSI0; + break; + case MUTEX_TABLE_IDX_DDP_DSI2: + sof_id = MUTEX_SOF_DSI2; + break; + case MUTEX_TABLE_IDX_DDP_DSI3: + sof_id = MUTEX_SOF_DSI3; + break; + case MUTEX_TABLE_IDX_DDP_DPI0: + sof_id = MUTEX_SOF_DPI0; + break; + case MUTEX_TABLE_IDX_DDP_DPI1: + sof_id = MUTEX_SOF_DPI1; + break; + case MUTEX_TABLE_IDX_DDP_DP_INTF0: + sof_id = MUTEX_SOF_DP_INTF0; + break; + case MUTEX_TABLE_IDX_DDP_DP_INTF1: + sof_id = MUTEX_SOF_DP_INTF1; + break; + default: + sof_id = MUTEX_SOF_SINGLE_MODE; + break; + } + + writel_relaxed(mtx->data->mutex_sof[sof_id], + mtx->regs + + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); +} +EXPORT_SYMBOL_GPL(mtk_mutex_set_sof); + void mtk_mutex_remove_comp(struct mtk_mutex *mutex, enum mtk_ddp_comp_id id) { @@ -485,6 +564,49 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex, } EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp); +void mtk_mutex_clear_mod(struct mtk_mutex *mutex, + enum mtk_mutex_table_index idx) +{ + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + unsigned int reg; + unsigned int offset; + + WARN_ON(&mtx->mutex[mutex->id] != mutex); + + if (idx == MUTEX_TABLE_IDX_NONE || + idx >= MUTEX_TABLE_IDX_MAX) + return; + + if (mtx->data->mutex_table_mod[idx] <= BIT(31)) { + offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, + mutex->id); + reg = readl_relaxed(mtx->regs + offset); + reg &= ~(mtx->data->mutex_table_mod[idx]); + writel_relaxed(reg, mtx->regs + offset); + } else { + offset = DISP_REG_MUTEX_MOD2(mutex->id); + reg = readl_relaxed(mtx->regs + offset); + reg &= ~(mtx->data->mutex_table_mod[idx] >> 32); + writel_relaxed(reg, mtx->regs + offset); + } +} +EXPORT_SYMBOL_GPL(mtk_mutex_clear_mod); + +void mtk_mutex_clear_sof(struct mtk_mutex *mutex) +{ + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + + WARN_ON(&mtx->mutex[mutex->id] != mutex); + + writel_relaxed(MUTEX_SOF_SINGLE_MODE, + mtx->regs + + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, + mutex->id)); +} +EXPORT_SYMBOL_GPL(mtk_mutex_clear_sof); + void mtk_mutex_enable(struct mtk_mutex *mutex) { struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h index 6fe4ffbde290..c8355bb0e6d6 100644 --- a/include/linux/soc/mediatek/mtk-mutex.h +++ b/include/linux/soc/mediatek/mtk-mutex.h @@ -10,14 +10,47 @@ struct regmap; struct device; struct mtk_mutex; +enum mtk_mutex_table_index { + MUTEX_TABLE_IDX_NONE = 0, /* Invalid engine */ + + /* MDP table index */ + MUTEX_TABLE_IDX_MDP_RDMA0, + MUTEX_TABLE_IDX_MDP_RSZ0, + MUTEX_TABLE_IDX_MDP_RSZ1, + MUTEX_TABLE_IDX_MDP_TDSHP0, + MUTEX_TABLE_IDX_MDP_WROT0, + MUTEX_TABLE_IDX_MDP_WDMA, + MUTEX_TABLE_IDX_MDP_AAL0, + MUTEX_TABLE_IDX_MDP_CCORR0, + + /* DDP table index */ + MUTEX_TABLE_IDX_DDP_DSI0, + MUTEX_TABLE_IDX_DDP_DSI1, + MUTEX_TABLE_IDX_DDP_DSI2, + MUTEX_TABLE_IDX_DDP_DSI3, + MUTEX_TABLE_IDX_DDP_DPI0, + MUTEX_TABLE_IDX_DDP_DPI1, + MUTEX_TABLE_IDX_DDP_DP_INTF0, + MUTEX_TABLE_IDX_DDP_DP_INTF1, + + MUTEX_TABLE_IDX_MAX /* ALWAYS keep at the end */ +}; + struct mtk_mutex *mtk_mutex_get(struct device *dev); int mtk_mutex_prepare(struct mtk_mutex *mutex); void mtk_mutex_add_comp(struct mtk_mutex *mutex, enum mtk_ddp_comp_id id); +void mtk_mutex_set_mod(struct mtk_mutex *mutex, + enum mtk_mutex_table_index idx); +void mtk_mutex_set_sof(struct mtk_mutex *mutex, + enum mtk_mutex_table_index idx); void mtk_mutex_enable(struct mtk_mutex *mutex); void mtk_mutex_disable(struct mtk_mutex *mutex); void mtk_mutex_remove_comp(struct mtk_mutex *mutex, enum mtk_ddp_comp_id id); +void mtk_mutex_clear_mod(struct mtk_mutex *mutex, + enum mtk_mutex_table_index idx); +void mtk_mutex_clear_sof(struct mtk_mutex *mutex); void mtk_mutex_unprepare(struct mtk_mutex *mutex); void mtk_mutex_put(struct mtk_mutex *mutex); void mtk_mutex_acquire(struct mtk_mutex *mutex); From patchwork Tue Mar 15 06:10:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 552031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B75DC4332F for ; Tue, 15 Mar 2022 06:11:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345195AbiCOGMy (ORCPT ); Tue, 15 Mar 2022 02:12:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345154AbiCOGMr (ORCPT ); Tue, 15 Mar 2022 02:12:47 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8279749FA2; Mon, 14 Mar 2022 23:11:35 -0700 (PDT) X-UUID: 6b258d2215b341d7a07080197e73bbce-20220315 X-UUID: 6b258d2215b341d7a07080197e73bbce-20220315 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 517029489; Tue, 15 Mar 2022 14:11:28 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Mar 2022 14:11:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Mar 2022 14:11:26 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Hans Verkuil , Jernej Skrabec CC: Chun-Kuang Hu , Geert Uytterhoeven , Rob Landley , Laurent Pinchart , , , , , , Alexandre Courbot , , , , , AngeloGioacchino Del Regno , Maoguang Meng , daoyuan huang , Ping-Hsun Wu , , , , , , , , , , Subject: [PATCH v13 2/6] soc: mediatek: mutex: add 8183 MUTEX MOD settings for MDP Date: Tue, 15 Mar 2022 14:10:27 +0800 Message-ID: <20220315061031.21642-3-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220315061031.21642-1-moudy.ho@mediatek.com> References: <20220315061031.21642-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For the purpose of module independence, related settings should be moved from MDP to the corresponding driver. This patch adds 8183 MUTEX MOD settings for MDP. Signed-off-by: Moudy Ho --- drivers/soc/mediatek/mtk-mutex.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 778b01ce9e8f..88fb4fc8f216 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -80,6 +80,15 @@ #define MT8183_MUTEX_MOD_DISP_GAMMA0 16 #define MT8183_MUTEX_MOD_DISP_DITHER0 17 +#define MT8183_MUTEX_MOD_MDP_RDMA0 BIT(2) +#define MT8183_MUTEX_MOD_MDP_RSZ0 BIT(4) +#define MT8183_MUTEX_MOD_MDP_RSZ1 BIT(5) +#define MT8183_MUTEX_MOD_MDP_TDSHP0 BIT(6) +#define MT8183_MUTEX_MOD_MDP_WROT0 BIT(7) +#define MT8183_MUTEX_MOD_MDP_WDMA BIT(8) +#define MT8183_MUTEX_MOD_MDP_AAL0 BIT(23) +#define MT8183_MUTEX_MOD_MDP_CCORR0 BIT(24) + #define MT8173_MUTEX_MOD_DISP_OVL0 11 #define MT8173_MUTEX_MOD_DISP_OVL1 12 #define MT8173_MUTEX_MOD_DISP_RDMA0 13 @@ -244,6 +253,17 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, }; +static const unsigned long long mt8183_mutex_table_mod[MUTEX_TABLE_IDX_MAX] = { + [MUTEX_TABLE_IDX_MDP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0, + [MUTEX_TABLE_IDX_MDP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0, + [MUTEX_TABLE_IDX_MDP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1, + [MUTEX_TABLE_IDX_MDP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0, + [MUTEX_TABLE_IDX_MDP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0, + [MUTEX_TABLE_IDX_MDP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA, + [MUTEX_TABLE_IDX_MDP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0, + [MUTEX_TABLE_IDX_MDP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0, +}; + static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0, @@ -335,6 +355,7 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = { .mutex_sof = mt8183_mutex_sof, .mutex_mod_reg = MT8183_MUTEX0_MOD0, .mutex_sof_reg = MT8183_MUTEX0_SOF0, + .mutex_table_mod = mt8183_mutex_table_mod, .no_clk = true, }; From patchwork Tue Mar 15 06:10:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 552030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCE09C43219 for ; Tue, 15 Mar 2022 06:11:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345146AbiCOGMz (ORCPT ); Tue, 15 Mar 2022 02:12:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345163AbiCOGMt (ORCPT ); Tue, 15 Mar 2022 02:12:49 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82AFA49FA2; Mon, 14 Mar 2022 23:11:37 -0700 (PDT) X-UUID: 9020a1ddc9f14415a324b4876df77003-20220315 X-UUID: 9020a1ddc9f14415a324b4876df77003-20220315 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 104757173; Tue, 15 Mar 2022 14:11:28 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Tue, 15 Mar 2022 14:11:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Mar 2022 14:11:26 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Hans Verkuil , Jernej Skrabec CC: Chun-Kuang Hu , Geert Uytterhoeven , Rob Landley , Laurent Pinchart , , , , , , Alexandre Courbot , , , , , AngeloGioacchino Del Regno , Maoguang Meng , daoyuan huang , Ping-Hsun Wu , , , , , , , , , , Subject: [PATCH v13 5/6] dts: arm64: mt8183: add GCE client property for Mediatek MUTEX Date: Tue, 15 Mar 2022 14:10:30 +0800 Message-ID: <20220315061031.21642-6-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220315061031.21642-1-moudy.ho@mediatek.com> References: <20220315061031.21642-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In order to allow modules with latency requirements such as MDP3 to set registers through CMDQ, add the relevant dts property. Signed-off-by: Moudy Ho --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 4b08691ed39e..fc6ac2a46324 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1514,6 +1514,7 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; mediatek,gce-events = , ; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; }; larb0: larb@14017000 {