From patchwork Tue Mar 15 21:19:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 551484 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AFF0C433EF for ; Tue, 15 Mar 2022 21:20:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351934AbiCOVWD (ORCPT ); Tue, 15 Mar 2022 17:22:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239608AbiCOVWC (ORCPT ); Tue, 15 Mar 2022 17:22:02 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B86F5B3F3; Tue, 15 Mar 2022 14:20:49 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 0FC1B1F42BBB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647379248; bh=tQqfNRntYK0gQYFiWjGgyBq66FzjlHnza9MyAlo7SoY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hBQpOiLZ7B6v9RyVoB7nXjXGpkZ25gXuYbYIgCqlkpm+xRAMCF6EfeLPONjrYSBF6 3BPu2Y5f6SdfnPt0+7opbJv0GCM404MYieMopv/UJW3wmll+MTLbUAppDR1sxw9bhS r7loE7VPvhDZscgTbBdVii6WyV0natSXJ9UJRDkI98IvKP3kPIbFL7r8s5q86rL1qC dNZU2vOiIEcNWUtohsZ3pnRnX/AvAPj9NXGBqrF+ssRixJLjMV7ZmNq4qiuKA2YMN3 ccHfr8ADDwySkzeFUtE4C54Ovk7FP03d7N/hFawan7LYrhHRDMlC1rzQe1x/xEIFlR DC8Ktt8DI239w== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Linus Walleij , Rob Herring Cc: kernel@collabora.com, AngeloGioacchino Del Regno , =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Matthias Brugger , Sean Wang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 1/4] dt-bindings: pinctrl: mt8192: Add wrapping node for pin configurations Date: Tue, 15 Mar 2022 17:19:33 -0400 Message-Id: <20220315211936.442708-2-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220315211936.442708-1-nfraprado@collabora.com> References: <20220315211936.442708-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On mt8192, the pinctrl node has pinctrl groups to group pin configurations. Each pinctrl group contains one or more pinmux subnodes to list needed pins and their configurations. By supporting multiple subnodes, we can configure different pin characteristics (driving/pull-up/pull-down/etc.) in a pinctrl group. Update the mt8192 pinctrl dt-binding to add the missing pinctrl group node that wraps the pinmux subnodes and update the example at the end. While at it, also remove the example embedded in the description since it is redundant to the already supplied example at the end. This same change was done for mt8195 in commit 79dcd4e840cc ("dt-bindings: pinctrl: mt8195: add wrapping node of pin configurations"). Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/pinctrl/pinctrl-mt8192.yaml | 92 ++++++++++--------- 1 file changed, 47 insertions(+), 45 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml index 3c84676a167d..d63e23d9ed16 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml @@ -51,62 +51,55 @@ properties: #PIN CONFIGURATION NODES patternProperties: - '^pins': + '-pins$': type: object - description: | - A pinctrl node should contain at least one subnodes representing the - pinctrl groups available on the machine. Each subnode will list the - pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. - An example of using macro: - pincontroller { - /* GPIO0 set as multifunction GPIO0 */ - state_0_node_a { - pinmux = ; - }; - /* GPIO1 set as multifunction PWM */ - state_0_node_b { - pinmux = ; - }; - }; - $ref: "pinmux-node.yaml" - - properties: - pinmux: + additionalProperties: false + patternProperties: + '^pins': + type: object description: | - Integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are defined - as macros in dt-bindings/pinctrl/-pinfunc.h directly. + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and + input schmitt. + $ref: "pinmux-node.yaml" - drive-strength: - description: | - It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See - dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192. - enum: [2, 4, 6, 8, 10, 12, 14, 16] + properties: + pinmux: + description: | + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in dt-bindings/pinctrl/-pinfunc.h directly. - bias-pull-down: true + drive-strength: + description: | + It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See + dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192. + enum: [2, 4, 6, 8, 10, 12, 14, 16] - bias-pull-up: true + bias-pull-down: true - bias-disable: true + bias-pull-up: true - output-high: true + bias-disable: true - output-low: true + output-high: true - input-enable: true + output-low: true - input-disable: true + input-enable: true - input-schmitt-enable: true + input-disable: true - input-schmitt-disable: true + input-schmitt-enable: true - required: - - pinmux + input-schmitt-disable: true - additionalProperties: false + required: + - pinmux + + additionalProperties: false allOf: - $ref: "pinctrl.yaml#" @@ -151,8 +144,17 @@ examples: interrupts = ; #interrupt-cells = <2>; - pins { - pinmux = ; - output-low; + spi1-default-pins { + pins-cs-mosi-clk { + pinmux = , + , + ; + bias-disable; + }; + + pins-miso { + pinmux = ; + bias-pull-down; + }; }; }; From patchwork Tue Mar 15 21:19:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 552002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF026C43217 for ; Tue, 15 Mar 2022 21:20:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351944AbiCOVWD (ORCPT ); Tue, 15 Mar 2022 17:22:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351938AbiCOVWD (ORCPT ); Tue, 15 Mar 2022 17:22:03 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDBF15BD13; Tue, 15 Mar 2022 14:20:50 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 880151F42BBE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647379249; bh=3ckuvqWLQ1qmzoI6HPHe+BcexrvaTRmXFylbDp1AC3I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fiIGSmRYBQRNzj3mgKPV/UTBh7RiXSNivNo34MoxKqEfCQDberhKZkx5V3hpbATJ3 hX2IB1KUOeNwc/jmKawertc+hsCDJhhTWmNvTwM6yHM2umYnoOUqjCcpevWSxUegjK sJydYSemDm5kuiyd7mqxabk6lpX943D6a/l2YoFUMpRJvn+46Oz6CE36MxuGzkWQjS S/ZbGXyvLMNBCwfcFcl0haRTEU1JgebWwVluVARlQu9Ps72xPRUTjy6SECtEK0FUfy vez6cjtUaOU/VEsiVD8JUv3hOOZRItzn+FXUjHBSlPzTTYypNBZ4lt4pWnNeUZBvOg IjUrPQllOg00w== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Linus Walleij , Rob Herring Cc: kernel@collabora.com, AngeloGioacchino Del Regno , =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Matthias Brugger , Sean Wang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 2/4] dt-bindings: pinctrl: mt8192: Add mediatek,drive-strength-adv property Date: Tue, 15 Mar 2022 17:19:34 -0400 Message-Id: <20220315211936.442708-3-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220315211936.442708-1-nfraprado@collabora.com> References: <20220315211936.442708-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the mediatek,drive-strength-adv property to the pinctrl-mt8192 dt-binding to allow further drive current adjustments for I2C nodes on MT8192. It is the same as in mt8183-pinctrl. Signed-off-by: Nícolas F. R. A. Prado --- .../bindings/pinctrl/pinctrl-mt8192.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml index d63e23d9ed16..b52d8d0eb2d0 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml @@ -78,6 +78,32 @@ patternProperties: dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192. enum: [2, 4, 6, 8, 10, 12, 14, 16] + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only support + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) = (0, 0, 0) + 1: (E1, E0, EN) = (0, 0, 1) + 2: (E1, E0, EN) = (0, 1, 0) + 3: (E1, E0, EN) = (0, 1, 1) + 4: (E1, E0, EN) = (1, 0, 0) + 5: (E1, E0, EN) = (1, 0, 1) + 6: (E1, E0, EN) = (1, 1, 0) + 7: (E1, E0, EN) = (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + bias-pull-down: true bias-pull-up: true From patchwork Tue Mar 15 21:19:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 551483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C815C433EF for ; Tue, 15 Mar 2022 21:20:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351947AbiCOVWH (ORCPT ); Tue, 15 Mar 2022 17:22:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351940AbiCOVWE (ORCPT ); Tue, 15 Mar 2022 17:22:04 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 547AA5B3F3; Tue, 15 Mar 2022 14:20:52 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 0EB771F42BBC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647379251; bh=vZXGUjEOoQ/hDl1/0up+a55Pw8LwwlkZJAbKDK6p7ZU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OQ3dUMDo+U38x8tXlkVy+aOoIfivhouBoK4rUd5hAnnxlR8uqiJWObLdl/sPOAgnB 0j1ZIdnPKux6r9hJLHbeSAWJZqA/g84oY+awqqGSBDJ7CNkjGewTCR05cngdJA6pex AztOP3wqTQPHp8dyhteUJMZGu5oA+IJKX0Q4j0veVaUGnL1Z92XLcmxpc/TlCH37Gh D4uBgW6dmpNib6Y9Z7raDIvnJjpYo75WoM3rI1uXFI8VMTwq9GLJswdV4oUd68Z35k Vni+s1kR0ivvrWpRpUT9sL5pFxq36AAyZk7D2k/uwWkEQqvg1YCFQs83YQsvi77Tvx J13eM8VJBZc9Q== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Linus Walleij , Rob Herring Cc: kernel@collabora.com, AngeloGioacchino Del Regno , =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Matthias Brugger , Sean Wang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 3/4] dt-bindings: pinctrl: mt8192: Add mediatek, pull-up-adv property Date: Tue, 15 Mar 2022 17:19:35 -0400 Message-Id: <20220315211936.442708-4-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220315211936.442708-1-nfraprado@collabora.com> References: <20220315211936.442708-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the mediatek,pull-up-adv property to the pinctrl-mt8192 dt-binding to allow configuring pull-up resistors on the pins of MT8192. It is the same as in mt8183-pinctrl. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/pinctrl/pinctrl-mt8192.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml index b52d8d0eb2d0..e27cbcc6e8f9 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml @@ -104,6 +104,17 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3, 4, 5, 6, 7] + mediatek,pull-up-adv: + description: | + Pull up settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + bias-pull-down: true bias-pull-up: true From patchwork Tue Mar 15 21:19:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 552001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07D74C43217 for ; Tue, 15 Mar 2022 21:20:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351957AbiCOVWI (ORCPT ); Tue, 15 Mar 2022 17:22:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351948AbiCOVWG (ORCPT ); Tue, 15 Mar 2022 17:22:06 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC7AE5BD16; Tue, 15 Mar 2022 14:20:53 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 964461F42BCE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647379252; bh=qdT4s8k2Bmbtq4iZ3iouM38/nzELTwmnPF7JPOifUkI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OeBy4qNcs6/B0BhypiDX7M6VKWZ9LYikZyrsTiRYSNdH6Ou81r1jD2cYiYodtoJJ9 v2XcSQM7mOtFu4qOVidIn9vS9KcgzHpDuawizS7APeT6ljIaef+nhag2WBiPfQ9nFS 3XRxMphMmITsidT0LgpJpUvCHGHl+PA1VZXjYjrgWAJ+yg5RSexvcW0OtF3FmVWMMS orDB5m2HXdey+2Lugil7KoZdE0DcjgzTEXn3/EgCAZuW2agf2wG3flmPAkl1dxQlNw S1D5lCWJPbPiV2VWBkz4MQK7QjlxQhzrt77274K6tT8ohIADkopHJF82N/iZZ8tUyR FrjC1ikDul7jQ== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Linus Walleij , Rob Herring Cc: kernel@collabora.com, AngeloGioacchino Del Regno , =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Matthias Brugger , Sean Wang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 4/4] dt-bindings: pinctrl: mt8192: Add gpio-line-names property Date: Tue, 15 Mar 2022 17:19:36 -0400 Message-Id: <20220315211936.442708-5-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220315211936.442708-1-nfraprado@collabora.com> References: <20220315211936.442708-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the gpio-line-names optional property to the pinctrl-mt8192 binding to prevent dt_binding_check warnings when it is present in the pinctrl node in the Devicetree. Signed-off-by: Nícolas F. R. A. Prado --- Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml index e27cbcc6e8f9..c90a132fbc79 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml @@ -29,6 +29,8 @@ properties: description: gpio valid number range. maxItems: 1 + gpio-line-names: true + reg: description: | Physical address base for gpio base registers. There are 11 GPIO