From patchwork Tue Mar 15 22:05:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 551998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40478C4332F for ; Tue, 15 Mar 2022 22:05:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352124AbiCOWHJ (ORCPT ); Tue, 15 Mar 2022 18:07:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352117AbiCOWHI (ORCPT ); Tue, 15 Mar 2022 18:07:08 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 807265C361 for ; Tue, 15 Mar 2022 15:05:54 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id A900B2C0ACC; Tue, 15 Mar 2022 22:05:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1647381952; bh=aI3QLwybL+R3Ug9pWHEKAZLgHlnzepQBa1pvlTSVses=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eMyQx1mIIYFHu6gkbosx638jI6UaI3yMlYEXriyzeynkx7Q1t0feys6kyJmURA9kM kT5QVenxH3NAthXBLxujvCgZRvx/NO+4F72KvXw42k2uV2DqBWRStp1sbwH2RqvTj8 cxoB2qISm8N+HQ9iieXB5LS45+sGXp+WV5KMV2YT4d8gbDKRef1gmVO8WdEqgH1Wyc fQddECsy9Sgzkp8o3wFHMiZzsKAhrrsrYVuiPPm3cg4UNz6KkBR2KLJriMPmNeWlEt lQCeRwtGTDM0nxbcy8may6Tk7HDy5dvAryg6x6SLrxPtBBY/nawunj/hEilGk4Fczk N4bwQeYG6DxOg== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Wed, 16 Mar 2022 11:05:52 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 5984713EE37; Wed, 16 Mar 2022 11:05:52 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 416AC2A2677; Wed, 16 Mar 2022 11:05:51 +1300 (NZDT) From: Chris Packham To: huziji@marvell.com, ulf.hansson@linaro.org, robh+dt@kernel.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v3 1/2] dt-bindings: mmc: xenon: add AC5 compatible string Date: Wed, 16 Mar 2022 11:05:48 +1300 Message-Id: <20220315220549.2749328-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220315220549.2749328-1-chris.packham@alliedtelesis.co.nz> References: <20220315220549.2749328-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=TYgE4sUc-WweND1bkCEA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Import binding documentation from the Marvell SDK which adds marvell,ac5-sdhci compatible string and documents the requirements for the for the Xenon SDHCI controller on the 98DX2530. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn --- Notes: Changes in v3: - Split from larger series - Add review from Andrew Changes in v2: - New .../bindings/mmc/marvell,xenon-sdhci.txt | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt index c51a62d751dc..43df466f0cb3 100644 --- a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt @@ -14,6 +14,7 @@ Required Properties: - "marvell,armada-ap806-sdhci": For controllers on Armada AP806. - "marvell,armada-ap807-sdhci": For controllers on Armada AP807. - "marvell,armada-cp110-sdhci": For controllers on Armada CP110. + - "marvell,ac5-sdhci": For CnM on AC5, AC5X and derived. - clocks: Array of clocks required for SDHC. @@ -33,6 +34,13 @@ Required Properties: in below. Please also check property marvell,pad-type in below. + * For "marvell,ac5-sdhci", one or two register areas. + (reg-names "ctrl" & "decoder"). + The first one is mandatory for the Xenon IP registers. + The second one is for systems where DMA mapping is required and is the + related address decoder register (the value to configure is derived from + the parent "dma-ranges"). + * For other compatible strings, one register area for Xenon IP. Optional Properties: @@ -171,3 +179,47 @@ Example: marvell,pad-type = "sd"; }; + + +- For eMMC with compatible "marvell,ac5-sdhci" with one reg range (no dma): + sdhci0: sdhci@805c0000 { + compatible = "marvell,ac5-sdhci"; + reg = <0x0 0x805c0000 0x0 0x300>; + reg-names = "ctrl", "decoder"; + interrupts = ; + clocks = <&core_clock>; + clock-names = "core"; + status = "okay"; + bus-width = <8>; + /*marvell,xenon-phy-slow-mode;*/ + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + }; + +- For eMMC with compatible "marvell,ac5-sdhci" with two reg ranges (with dma): + mmc_dma: mmc-dma-peripherals@80500000 { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + dma-ranges = <0x2 0x0 0x2 0x80000000 0x1 0x0>; + dma-coherent; + + sdhci0: sdhci@805c0000 { + compatible = "marvell,ac5-sdhci", "marvell,armada-ap806-sdhci"; + reg = <0x0 0x805c0000 0x0 0x300>, <0x0 0x80440230 0x0 0x4>; + reg-names = "ctrl", "decoder"; + interrupts = ; + clocks = <&core_clock>; + clock-names = "core"; + status = "okay"; + bus-width = <8>; + /*marvell,xenon-phy-slow-mode;*/ + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + }; + }; From patchwork Tue Mar 15 22:05:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 551999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFD7DC433F5 for ; Tue, 15 Mar 2022 22:05:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352122AbiCOWHJ (ORCPT ); Tue, 15 Mar 2022 18:07:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234246AbiCOWHI (ORCPT ); Tue, 15 Mar 2022 18:07:08 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89A2D5C36A for ; Tue, 15 Mar 2022 15:05:54 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id A74172C0A8F; Tue, 15 Mar 2022 22:05:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1647381952; bh=shAvVAo4zZnFN8Y1h8zTgPxTI/jOM/JR1c6ANtqej8c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UBWQQe9L6SmpExPvcCXuHbeM73eij0pYLeWTuarC+eyQImOh7Od43h3s+ugVY+j9n qdDub/ZoJYgGDAUc7JIzAwrmpF5aiLnJyOxzSrcafYpjx0o9J5zY6VTG/uoq1s1P2N NZ8VXXOB96pUBdohPE+8A8mn2esQDzx1Zf+HVcbWV5mAjM8UZpteJ0xecx5hTmwyr5 Ez2NNLfBjFE5VL3DgtPEgxrPaX+fGweALYvRtY0Y1JUBHZ0QRwtg1j+ONa3tITeKAT da04wEBxBZwCSTZsLuAHTut+O0GEgfl4qvVnAMNTNjgm6MWdDTnXTKCtZU7kc/JbxX 7LJ0IqCDCMgPA== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Wed, 16 Mar 2022 11:05:52 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 5BD2613EE3F; Wed, 16 Mar 2022 11:05:52 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 4518D2A2677; Wed, 16 Mar 2022 11:05:51 +1300 (NZDT) From: Chris Packham To: huziji@marvell.com, ulf.hansson@linaro.org, robh+dt@kernel.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v3 2/2] mmc: xenon: add AC5 compatible string Date: Wed, 16 Mar 2022 11:05:49 +1300 Message-Id: <20220315220549.2749328-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220315220549.2749328-1-chris.packham@alliedtelesis.co.nz> References: <20220315220549.2749328-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=UvibhkeALEyMK9IFLgoA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add marvell,ac5-sdhci to the list of compatible strings for the Xenon SDHCI controller. Currently this is functionally no different to the ap806 but having the compatible string will allow handling any differences that arise from the controller being integrated in the 98DX2530 switch chips. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn --- Notes: Changes in v3: - Split from larger series - Add review from Andrew Changes in v2: - New drivers/mmc/host/sdhci-xenon.c | 1 + drivers/mmc/host/sdhci-xenon.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c index 666cee4c7f7c..ac95d16809c5 100644 --- a/drivers/mmc/host/sdhci-xenon.c +++ b/drivers/mmc/host/sdhci-xenon.c @@ -692,6 +692,7 @@ static const struct of_device_id sdhci_xenon_dt_ids[] = { { .compatible = "marvell,armada-ap807-sdhci", .data = (void *)XENON_AP807}, { .compatible = "marvell,armada-cp110-sdhci", .data = (void *)XENON_CP110}, { .compatible = "marvell,armada-3700-sdhci", .data = (void *)XENON_A3700}, + { .compatible = "marvell,ac5-sdhci", .data = (void *)XENON_AC5}, {} }; MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids); diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h index 3e9c6c908a79..451b41dd3447 100644 --- a/drivers/mmc/host/sdhci-xenon.h +++ b/drivers/mmc/host/sdhci-xenon.h @@ -57,7 +57,8 @@ enum xenon_variant { XENON_A3700, XENON_AP806, XENON_AP807, - XENON_CP110 + XENON_CP110, + XENON_AC5, }; struct xenon_priv {