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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id g24-20020a17090a579800b001c60f919656sm113847pji.18.2022.03.14.10.36.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 10:36:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 1/4] tcg/s390x: Fix tcg_out_dupi_vec vs VGM Date: Mon, 14 Mar 2022 10:36:04 -0700 Message-Id: <20220314173607.145630-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220314173607.145630-1-richard.henderson@linaro.org> References: <20220314173607.145630-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1034 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The immediate operands to VGM were in the wrong order, producing an inverse mask. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 6e65828c09..508f1bccc7 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2715,7 +2715,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, msb = clz32(val); lsb = 31 - ctz32(val); } - tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_32); + tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32); return; } } else { @@ -2729,7 +2729,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, msb = clz64(val); lsb = 63 - ctz64(val); } - tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_64); + tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64); return; } } From patchwork Mon Mar 14 17:36:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 551080 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2791242mag; Mon, 14 Mar 2022 10:56:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxSGBCo75o1IdjbMHRlSranFI4q9sC4w3yYdj+gs2TSebObwrZBK5bqu/bSH+OmgfL8/KcZ X-Received: by 2002:a0d:cac2:0:b0:2db:fc7f:7dfa with SMTP id m185-20020a0dcac2000000b002dbfc7f7dfamr19641536ywd.362.1647280588449; Mon, 14 Mar 2022 10:56:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647280588; cv=none; d=google.com; s=arc-20160816; b=NKkKBvvqxklssnEaSbWSwqSIAoFktBqFgoYb90wUC26M8dSeHFmaGJUQGybwFXUUC8 dAMJUmSZIQxB/0Yp186q778ZDZmsUNu4/2bR9+cKFYeILOhY2IU5QoysZ0HTfTPiLhpe Yw6B2dleQNUBod8CqVg/p9eGxA726q5JYenhVXUUiGh/GUNWWI/uYZRpRrq6TBPg96cq 0rAsZMN79DJ4FbNkChFuggRf+HcL7arzZDOKwNdUxCz0qU/jDFTWdVxF+AnsKaWdqdA3 ZShOLhPT+D/bK6PmgCXBASXKZ06wWbWjoR6NKnXqmGbzMqhq+zbijhpZ5IlxSN3iAu44 NSgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zHlvdTeEJH0Ni+sNVrOIMRWUpHKHamH8lfo6vskTyp8=; b=HnA2bzvFeDwYWHVTD9pWAfe2KMvK3sWiXx6YJKkOHHQi/FdbMBW3cVMvMnFLa7/7rO R3/ylghQ4WEacQZn21dKKGeOokGVgdej55ra5XgYsf0eg0UibrhBXVfc81kl7JwliTZN gE3OlYiJ9TAFPbAB0BoQU+hP+XD0kn9M0hHafPk0He4Y1GCb/JUH01Ogq0ghXARE6tbT yMlnh+A2wG0mcdY1u1VU64u3ZP1dz93mINxw/JMgEU/Oy5Ok3ZF+/axo/RIFWilVIV3p WrgwAk/gmy5mjq0biVH8BJRRc3fWzLd+gjjh5XwzWzbXIyaV87NPwIARenwkAoRPmAZS CmTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eIznPaU6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id g24-20020a17090a579800b001c60f919656sm113847pji.18.2022.03.14.10.36.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 10:36:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 2/4] tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL Date: Mon, 14 Mar 2022 10:36:05 -0700 Message-Id: <20220314173607.145630-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220314173607.145630-1-richard.henderson@linaro.org> References: <20220314173607.145630-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Thomas Huth Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The operands are output in the wrong order: the tcg selector argument is first, whereas the s390x selector argument is last. Tested-by: Thomas Huth Resolves: https://gitlab.com/qemu-project/qemu/-/issues/898 Fixes: 9bca986df88 ("tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec") Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 508f1bccc7..3b185b3c96 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2868,7 +2868,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_bitsel_vec: - tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]); + tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1); break; case INDEX_op_cmp_vec: From patchwork Mon Mar 14 17:36:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 551078 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2782629mag; Mon, 14 Mar 2022 10:41:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwhV0LNtVtH4Ac/M1FBtumrVbEf4kl4r/LlKfBEUav30WKNJpCvp29KsKiJlvw13UTEiWl8 X-Received: by 2002:a81:ae4b:0:b0:2dc:4e3e:7268 with SMTP id g11-20020a81ae4b000000b002dc4e3e7268mr19591229ywk.406.1647279698071; Mon, 14 Mar 2022 10:41:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647279698; cv=none; d=google.com; s=arc-20160816; b=MadhsWs9k4lENciZLj9JxxgQ14WXbrxhA8ZSiU+vyN+fOZbIjeYplgXvlbfzB7MbSF NfJva/zez67pI4Kg+zhkcJZMaxVwGPQogg+JGCjyn9+jLK7JScXkWOlvIDWFqfCQozWq IQAyc0fc6JXVyEZtSUqdZdhQp0B8Yxyblzi9e+xd6pGYq5XyA5Crt2UNiYyLDX1ddlsZ u/vl9eAWG0+DIN4/LZTzH5RBW2mjOK9PK4E3nNtNE44Wc8/QO7TICKr+UgxKQ7vRhGSa mBW0wIHKX850c+ZQIHh7QPnZSc+f4zf1KcWuWvpBeJFwuJ8vn3QUE31XgsTW1LAiFRzA VR0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DPs3qyT+uZfNbgHJhAl1/at2oy1K0HPub76v6Xk9tE4=; b=ZZSsgKUdgAwnegZVQcZbcd7+rRL15ER7C+iYbGymFr71ub5rpw/kGoyOttIiaLqBQ6 59VeT96vPm29jisvgoCaOSloh+ekFAe+4z8bjFfli3WO7T1XUywEKpHkdiA8dP58iKbh l1tKjjbUz1eoAvR8xTLRDEr+1uAH/GrD5xfyZmXegzcfHmMtAJG/hUHNVgnl54shY0+q 5lu3gWiijOd0eJko9Ph0eVtWBvUxecmKTBbCfKBxGxPEkP5tkswkSB2TutMsLq8xMzqD WquSZ5EraiAjx9Il9vEH77HGUBj/JauR7Tup6WWjRnkslcr9S9Y+NrGEdilTu4WsBd8x S+CA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lT78N4Zy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id g24-20020a17090a579800b001c60f919656sm113847pji.18.2022.03.14.10.36.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 10:36:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 3/4] tcg/s390x: Fix tcg_out_dup_vec vs general registers Date: Mon, 14 Mar 2022 10:36:06 -0700 Message-Id: <20220314173607.145630-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220314173607.145630-1-richard.henderson@linaro.org> References: <20220314173607.145630-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We copied the data from the general register input to the vector register output, but have not yet replicated it. We intended to fall through into the vector-vector case, but failed to redirect the input register. This is caught by an assertion failure in tcg_out_insn_VRIc, which diagnosed the incorrect register class. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 3b185b3c96..33becd7694 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2675,6 +2675,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, if (vece == MO_64) { return true; } + src = dst; } /* From patchwork Mon Mar 14 17:36:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 551082 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2792733mag; Mon, 14 Mar 2022 10:59:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz64fSO4rBCLBB2Cg9HjoN9yNJsuexvbgl7gpslOX25ym0AWe0ed7WWDnCkI6BoIZEvc7Q7 X-Received: by 2002:a0d:d987:0:b0:2ca:287c:6bf4 with SMTP id b129-20020a0dd987000000b002ca287c6bf4mr19599132ywe.153.1647280740878; Mon, 14 Mar 2022 10:59:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647280740; cv=none; d=google.com; s=arc-20160816; b=QJfTceM79BCY3A/Azq5UsNKzqT4uWaOx3E6QyJsrplOmop/TiyDdDum1WOigqODObZ oU8rfC6IL2lQWL/zlKTpUvLOa2IpoDbQOlrUvX4zkZEUzJN6dyC44a2GYg2eYSKDpDUw 9f47TCrPdtU2aoBZ7NMnyAcZ5TVwo3m0LZTBIABPYl/8BCbwqPubb0bys0zUan39mQ2u M5/jGuJghej3+yHSnSlnATUkmYdDm7GX6EtCsAbEHmTNHhoGZxdCxc4ZszcZWsbnPzMz vdiJh1quq4AAgy3bmr0+K2LhjrhUmipxFwv6AGOIr41UHVAeOzo2nBhqKfyslOF0wi7x Noow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HBwan3ikRKwWJ4ff5ws0FdOZZkWoH5Z3Uy/j8VWWXqM=; b=jXkoLDNks5l+ltplrok2FwR8CmgbSH3RK6FPmVxX3/3J83XMKBlgijuWqHjoo+4BWB zsbrQDBBK4kM0r5BVGZ96UeJTrVhv2iaXbSLs/6qFoyw6tf30Y8Yw07fpTuG133TK9tt Qk3MIzdQM6VXdLGmyqf/3L5QE+0GvvFJILpu99ZO5CFO7tcyYO7Fk4tH0M+CrwO9FXCd 9BZkRh/5QCmzWTz6FVRjHW5GxBED8EWkBZCwXvhlEYmFpyRzbLFqWMBBNx/+xAFSaxZu NKfiym4TTCRrSsOusac9cmvo5yIL6z8ekP9YpRol9dMVANmgaCDbR+TMFsJnvpqY+evG 9ffQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ESjJ5Tfy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id g24-20020a17090a579800b001c60f919656sm113847pji.18.2022.03.14.10.36.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 10:36:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 4/4] tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1 Date: Mon, 14 Mar 2022 10:36:07 -0700 Message-Id: <20220314173607.145630-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220314173607.145630-1-richard.henderson@linaro.org> References: <20220314173607.145630-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The LDRD (register) instruction is UNPREDICTABLE if the Rm register is the same as either Rt or Rt+1 (the two registers being loaded to). We weren't making sure we avoided this, with the result that on some host CPUs like the Cortex-A7 we would get a SIGILL because the CPU chooses to UNDEF for this particular UNPREDICTABLE case. Since we've already checked that datalo is aligned, we can simplify the test vs the Rm operand by aligning it before comparison. Check for the two orderings before falling back to two ldr instructions. We don't bother to do anything similar for tcg_out_ldrd_rwb(), because it is only used in tcg_out_tlb_read() with a fixed set of registers which don't overlap. There is no equivalent UNPREDICTABLE case for STRD. Reviewed-by: Alex Bennée Resolves: https://gitlab.com/qemu-project/qemu/-/issues/896 Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index e1ea69669c..4bc0420f4d 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1689,8 +1689,21 @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, /* LDRD requires alignment; double-check that. */ if (get_alignment_bits(opc) >= MO_64 && (datalo & 1) == 0 && datahi == datalo + 1) { - tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend); - } else if (scratch_addend) { + /* + * Rm (the second address op) must not overlap Rt or Rt + 1. + * Since datalo is aligned, we can simplify the test via alignment. + * Flip the two address arguments if that works. + */ + if ((addend & ~1) != datalo) { + tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend); + break; + } + if ((addrlo & ~1) != datalo) { + tcg_out_ldrd_r(s, COND_AL, datalo, addend, addrlo); + break; + } + } + if (scratch_addend) { tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo); tcg_out_ld32_12(s, COND_AL, datahi, addend, 4); } else {