From patchwork Sun Mar 13 00:08:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 550968 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE49EC433EF for ; Sun, 13 Mar 2022 00:08:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233085AbiCMAJm (ORCPT ); Sat, 12 Mar 2022 19:09:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229983AbiCMAJk (ORCPT ); Sat, 12 Mar 2022 19:09:40 -0500 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2EDE27CFE for ; Sat, 12 Mar 2022 16:08:33 -0800 (PST) Received: by mail-lj1-x231.google.com with SMTP id u3so17083305ljd.0 for ; Sat, 12 Mar 2022 16:08:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=APUYBe0TqoLNb60yJh0EtkIi3YX9wceE9eYvJbV9UfA=; b=SlW0HqEkN1zYQnhxxR3IE91D6sz0cg+4HVyw6V5rbiIqEZ2CbmF1zct3K3QTZtRV8Q 3u9Q9gdDX54cpyKl61ldEVCR3anp30A00o/6RXDTGsoQ+nk4REekCHvlklO++C63aJ/E V9GcHd8YUMSKI4yAqE+JgjJUjM0Xbg2pJIQ5a0iaNTawMtkahUWD8Gc59l4gHCqffLc5 OHIG7XMUfzZ0898Q1FIxgFB/KWz2Vhl0Rx7GGSqQFTCoVL4hP8UM9AyFe5B8IF8eRw/Y mYtrfI5oKo4hrg2YiaprYgZ7t+IcCI4oIME0Phx3IxlA5sYUFDcor1NZOSHOQNZe96xD OzoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=APUYBe0TqoLNb60yJh0EtkIi3YX9wceE9eYvJbV9UfA=; b=4pC5h5K4E2ZLT7+5kjI61xg2sEWqnYaA3UhkNLID6ANKdiLAnjrtfia9h5MiFM1smQ m4nW3elLhYtyNTqF0nlP90PyKXKNNelFxNUP6M78Ar88tNVZf2QijadROpFcYbqJTNhh OIfW6iMnWKiyXjWArW5416/nV9Yhfg/HI6Yg82gyVEdxT+6SptgNt2GQ6ELx0pJDqzG1 w4OFRReu9hUENVr4+MhlXnRSQNllNmBF84yEU+ejwaAx+ENiB1WUY0XTza8R6yNjf3D9 IGiheTClnIsDSgwpQ1ghW5D31f0HWTqAQY0pVxMTQGPifGdVaaTrHYnlLkyV7hFt7Yjc a7CQ== X-Gm-Message-State: AOAM530nndCgCLTLzVVasAt5cKYeowz+JmOwdVNKfBX4kDru43pZR8sw wADuzAl1lhXL3o4Kd04FgTIidg== X-Google-Smtp-Source: ABdhPJybR54R0cNuQzQ9YRRjo/Xtdu0cp4IFcVpA/Isf+aIM6lLvHJVHLYVsXFaO8c0ZXKDOPNAd2w== X-Received: by 2002:a2e:bf04:0:b0:246:7ace:e157 with SMTP id c4-20020a2ebf04000000b002467acee157mr10227672ljr.241.1647130112241; Sat, 12 Mar 2022 16:08:32 -0800 (PST) Received: from eriador.lumag.spb.ru (pppoe.178-66-158-48.dynamic.avangarddsl.ru. [178.66.158.48]) by smtp.gmail.com with ESMTPSA id e7-20020a05651c038700b00247dbb3e476sm2776017ljp.40.2022.03.12.16.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Mar 2022 16:08:31 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas Cc: Prasad Malisetty , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pci@vger.kernel.org Subject: [RFC PATCH 1/5] clk: qcom: regmap-mux: add pipe clk implementation Date: Sun, 13 Mar 2022 03:08:20 +0300 Message-Id: <20220313000824.229405-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313000824.229405-1-dmitry.baryshkov@linaro.org> References: <20220313000824.229405-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PCIe PIPE clk (and some other clocks) must be parked to the "safe" source (bi_tcxo) when corresponding GDSC is turned off and on again. Currently this is handcoded in the PCIe driver, reparenting the gcc_pipe_N_clk_src clock. However the same code sequence should be applied in the pcie-qcom-ep, USB3 and UFS drivers. Rather than copying this sequence over and over again, follow the example of clk_rcg2_shared_ops and implement this parking in the enable() and disable() clock operations. As we are changing the parent behind the back of the clock framework, also implement custom set_parent() and get_parent() operations behaving accroding to the clock framework expectations (cache the new parent if the clock is in disabled state, return cached parent). Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-regmap-mux.c | 70 +++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-regmap-mux.h | 3 ++ 2 files changed, 73 insertions(+) diff --git a/drivers/clk/qcom/clk-regmap-mux.c b/drivers/clk/qcom/clk-regmap-mux.c index 45d9cca28064..024412b070c5 100644 --- a/drivers/clk/qcom/clk-regmap-mux.c +++ b/drivers/clk/qcom/clk-regmap-mux.c @@ -49,9 +49,79 @@ static int mux_set_parent(struct clk_hw *hw, u8 index) return regmap_update_bits(clkr->regmap, mux->reg, mask, val); } +static u8 mux_safe_get_parent(struct clk_hw *hw) +{ + struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); + unsigned int val; + + if (clk_hw_is_enabled(hw)) + return mux_get_parent(hw); + + val = mux->stored_parent; + + if (mux->parent_map) + return qcom_find_cfg_index(hw, mux->parent_map, val); + + return val; +} + +static int mux_safe_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); + + if (clk_hw_is_enabled(hw)) + return mux_set_parent(hw, index); + + if (mux->parent_map) + index = mux->parent_map[index].cfg; + + mux->stored_parent = index; + + return 0; +} + +static void mux_safe_disable(struct clk_hw *hw) +{ + struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); + struct clk_regmap *clkr = to_clk_regmap(hw); + unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); + unsigned int val; + + regmap_read(clkr->regmap, mux->reg, &val); + + mux->stored_parent = (val & mask) >> mux->shift; + + val = mux->safe_src_index; + val <<= mux->shift; + + regmap_update_bits(clkr->regmap, mux->reg, mask, val); +} + +static int mux_safe_enable(struct clk_hw *hw) +{ + struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); + struct clk_regmap *clkr = to_clk_regmap(hw); + unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); + unsigned int val; + + val = mux->stored_parent; + val <<= mux->shift; + + return regmap_update_bits(clkr->regmap, mux->reg, mask, val); +} + const struct clk_ops clk_regmap_mux_closest_ops = { .get_parent = mux_get_parent, .set_parent = mux_set_parent, .determine_rate = __clk_mux_determine_rate_closest, }; EXPORT_SYMBOL_GPL(clk_regmap_mux_closest_ops); + +const struct clk_ops clk_regmap_mux_safe_ops = { + .enable = mux_safe_enable, + .disable = mux_safe_disable, + .get_parent = mux_safe_get_parent, + .set_parent = mux_safe_set_parent, + .determine_rate = __clk_mux_determine_rate_closest, +}; +EXPORT_SYMBOL_GPL(clk_regmap_mux_safe_ops); diff --git a/drivers/clk/qcom/clk-regmap-mux.h b/drivers/clk/qcom/clk-regmap-mux.h index db6f4cdd9586..ab8ab25d79bd 100644 --- a/drivers/clk/qcom/clk-regmap-mux.h +++ b/drivers/clk/qcom/clk-regmap-mux.h @@ -14,10 +14,13 @@ struct clk_regmap_mux { u32 reg; u32 shift; u32 width; + u8 safe_src_index; + u8 stored_parent; const struct parent_map *parent_map; struct clk_regmap clkr; }; extern const struct clk_ops clk_regmap_mux_closest_ops; +extern const struct clk_ops clk_regmap_mux_safe_ops; #endif From patchwork Sun Mar 13 00:08:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 550967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CD1EC4167E for ; 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[178.66.158.48]) by smtp.gmail.com with ESMTPSA id e7-20020a05651c038700b00247dbb3e476sm2776017ljp.40.2022.03.12.16.08.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Mar 2022 16:08:33 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas Cc: Prasad Malisetty , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pci@vger.kernel.org Subject: [RFC PATCH 3/5] clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks Date: Sun, 13 Mar 2022 03:08:22 +0300 Message-Id: <20220313000824.229405-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313000824.229405-1-dmitry.baryshkov@linaro.org> References: <20220313000824.229405-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use newly defined clk_regmap_mux_safe_ops for PCIe pipe clocks to let the clock framework automatically park the clock when the clock is switched off and restore the parent when the clock is switched on. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-sc7280.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 423627d49719..69887e45d02f 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -373,13 +373,14 @@ static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x6b054, .shift = 0, .width = 2, + .safe_src_index = 2, .parent_map = gcc_parent_map_6, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk_src", .parent_data = gcc_parent_data_6, .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_regmap_mux_closest_ops, + .ops = &clk_regmap_mux_safe_ops, }, }, }; @@ -388,13 +389,14 @@ static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { .reg = 0x8d054, .shift = 0, .width = 2, + .safe_src_index = 2, .parent_map = gcc_parent_map_7, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk_src", .parent_data = gcc_parent_data_7, .num_parents = ARRAY_SIZE(gcc_parent_data_7), - .ops = &clk_regmap_mux_closest_ops, + .ops = &clk_regmap_mux_safe_ops, }, }, }; From patchwork Sun Mar 13 00:08:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 550966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3254AC43217 for ; Sun, 13 Mar 2022 00:08:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233132AbiCMAJu (ORCPT ); Sat, 12 Mar 2022 19:09:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231570AbiCMAJp (ORCPT ); Sat, 12 Mar 2022 19:09:45 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B519C286C3 for ; Sat, 12 Mar 2022 16:08:37 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id g17so21213577lfh.2 for ; Sat, 12 Mar 2022 16:08:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jte6feuN3TvbrHZNYXfdhblN5VSBHO8/wui51puHHcE=; b=elQrPP78TqHBSk0SUGucu1mFxbSGj2CfgkV8qLa3sNznJVy+K9IaqwHsXFUDbPyJUN urASSFJK/3W6VBUBb/V07TGtbSPGQLjnqpFwijAt9gMRxZjyoG32cPR5/lSAes0IRGHj UXyXQTmUuS/AP5ikayqGudxC/0LPadZwgGfzS/iBH8GhsKgEWSS4a7tFgMQovK1sTnLu ocQAvA/t1PK9F0Ov/fUsdlcVCYmjOt7e+XJOr+6dJGFZrwTg9OcAWfCDtZM1c2ENyaMw vnqVaFK54N68e86bYKCjX5r3jJs1F2MEMfAodCxogz42haTNq+5FFWb0Yg2SOnoq9rCd 4ybA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jte6feuN3TvbrHZNYXfdhblN5VSBHO8/wui51puHHcE=; b=JUAfOcv0FRkw5xRg1DlGSx0oS8YpgDXDqQeVSzGb0GiKvrQy20r333MXtLgW3O6fHR T0B5ECrDa82dIM+GMP+H+aitZfz0iUD0BlJxK2eO1CW0dhA7U9ZaZluw0Um1YV2ofKBw NArU1NSQE0J3Z+nncFx7IZSEdCEHPcusRojdWaHaNOaoS2/6BTRReL/iCIaa1N6oRrFz YDMt+HZF2ZEvmoqOTLZfOk1jdGZVZjn1opqXIEPkaBjIRRgQne7zF18cmorkPHBv3opf lmKaVQTWkbugAEQ3nLm26pT8pM16EmDFguL5RrJ5meO8ookrM8V+T2YvG/Y/kES/O1Zx SqSA== X-Gm-Message-State: AOAM532dMGzFCvEXATvVgDVAbf16z71trjTlg8U1h9eSbPHNAG+nez7d wg/iNAP7bEJ+GfrA4Fj66llwBA== X-Google-Smtp-Source: ABdhPJyZK/bgYtkMRR1o4kbQQmJ8dS/JFFQct0YpmbKyAJbyfK4EDLBEJhflYQbkUMRhoqp2UFNGnQ== X-Received: by 2002:ac2:42d4:0:b0:448:2fae:83c1 with SMTP id n20-20020ac242d4000000b004482fae83c1mr9764930lfl.637.1647130115999; Sat, 12 Mar 2022 16:08:35 -0800 (PST) Received: from eriador.lumag.spb.ru (pppoe.178-66-158-48.dynamic.avangarddsl.ru. [178.66.158.48]) by smtp.gmail.com with ESMTPSA id e7-20020a05651c038700b00247dbb3e476sm2776017ljp.40.2022.03.12.16.08.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Mar 2022 16:08:35 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas Cc: Prasad Malisetty , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pci@vger.kernel.org Subject: [RFC PATCH 5/5] PCI: qcom: Drop manual pipe_clk_src handling Date: Sun, 13 Mar 2022 03:08:24 +0300 Message-Id: <20220313000824.229405-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313000824.229405-1-dmitry.baryshkov@linaro.org> References: <20220313000824.229405-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Manual reparenting of pipe_clk_src is being replaced with the parking of the clock with clk_disable()/clk_enable(). Drop redundant code letting the pipe clock driver park the clock to the safe bi_tcxo parent automatically. Cc: Prasad Malisetty Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 39 +------------------------- 1 file changed, 1 insertion(+), 38 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a6becafb6a77..b48c899bcc97 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -164,9 +164,6 @@ struct qcom_pcie_resources_2_7_0 { int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; - struct clk *pipe_clk_src; - struct clk *phy_pipe_clk; - struct clk *ref_clk_src; }; union qcom_pcie_resources { @@ -192,7 +189,6 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; - unsigned int pipe_clk_need_muxing:1; unsigned int has_tbu_clk:1; unsigned int has_ddrss_sf_tbu_clk:1; unsigned int has_aggre0_clk:1; @@ -1158,20 +1154,6 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret < 0) return ret; - if (pcie->cfg->pipe_clk_need_muxing) { - res->pipe_clk_src = devm_clk_get(dev, "pipe_mux"); - if (IS_ERR(res->pipe_clk_src)) - return PTR_ERR(res->pipe_clk_src); - - res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe"); - if (IS_ERR(res->phy_pipe_clk)) - return PTR_ERR(res->phy_pipe_clk); - - res->ref_clk_src = devm_clk_get(dev, "ref"); - if (IS_ERR(res->ref_clk_src)) - return PTR_ERR(res->ref_clk_src); - } - return 0; } @@ -1189,10 +1171,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } - /* Set TCXO as clock source for pcie_pipe_clk_src */ - if (pcie->cfg->pipe_clk_need_muxing) - clk_set_parent(res->pipe_clk_src, res->ref_clk_src); - ret = clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret < 0) goto err_disable_regulators; @@ -1254,18 +1232,8 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; clk_bulk_disable_unprepare(res->num_clks, res->clks); - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); -} -static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - - /* Set pipe clock as clock source for pcie_pipe_clk_src */ - if (pcie->cfg->pipe_clk_need_muxing) - clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); - - return 0; + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } static int qcom_pcie_link_up(struct dw_pcie *pci) @@ -1441,7 +1409,6 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .post_init = qcom_pcie_post_init_2_7_0, }; /* Qcom IP rev.: 1.9.0 */ @@ -1450,7 +1417,6 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .post_init = qcom_pcie_post_init_2_7_0, .config_sid = qcom_pcie_config_sid_sm8250, }; @@ -1488,7 +1454,6 @@ static const struct qcom_pcie_cfg sm8250_cfg = { static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, - .pipe_clk_need_muxing = true, .has_aggre0_clk = true, .has_aggre1_clk = true, }; @@ -1496,14 +1461,12 @@ static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, - .pipe_clk_need_muxing = true, .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, .has_tbu_clk = true, - .pipe_clk_need_muxing = true, }; static const struct dw_pcie_ops dw_pcie_ops = {