From patchwork Thu Dec 6 00:02:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 152975 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp9903481ljp; Wed, 5 Dec 2018 16:02:46 -0800 (PST) X-Google-Smtp-Source: AFSGD/UkY+O4MxIB58icCVB2AdjsszavuaUpidJ3JUgfl7rkPRYMr14sgqWMt+jyu9nN+PfoufFW X-Received: by 2002:a63:9a52:: with SMTP id e18mr22065313pgo.14.1544054566464; Wed, 05 Dec 2018 16:02:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544054566; cv=none; d=google.com; s=arc-20160816; b=GSLvNeVHSabudDipAVtrDb5Ali92uERuG4mDv+uze2Hdx8cWXs8ZhlJ8z91Ps5MdsJ 7hc7M277GmcKNYL4FeKIOkXGZJkl3nIXkId9WiDsLT86Ps4IpHrJb7+pK1P9RPzgTwSo +erHMX0c7bRMWIk7arl4Dk6yI+4AgamWOqhk0NIJYXPTn/uxprh8t5ujRlcYVPKBRXNk GQF59cDdGFh89RCD3f3Z3bS7IZar5fWZraETXKrIsmqRgzXt4AuYLtGkB3blvGLzng8D tab6T7y0dSx1lIth3qzXpiKSP/fYFK2hOhkvNiF3Ejlmpmyn4d4gAMK75uLMTveMffc7 jemg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PNmL/AdZMFDm2CB5drDSBkoW5xhj23+00GAIyKewIVI=; b=fGRFNSwEfZIDEEckNqDsKy1nfGYv4P9ZGqX42UIRyijW29CXs6sISGuPwzyRszxtQ5 A+sTyAWCbamWiYhK2OITFdMiWwSMd63v37f86dcTVE3hWCzRUqsTKfey6sYuTn+x+Xvg LBf/pqC08LVtrBtWn+prMv3BlSuD2RxXtEWfE0x9SfQ0JtM6oTKdzhJORLyaps2eRxiZ rpEMep5Pfe3aXwQzTOaelR95PhLoYCwoLcBsBirfBvMnJuARQBiFYTWYKSFaKGmD3OVJ bi5xpV8X18LWsDOSss5tk5Vty+4EAXGv6Izk8scvMS6m3j9hOohIbIHmh+FZiLr9SqWr 1kyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VUPgnCIp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z22si22006398pfd.197.2018.12.05.16.02.46; Wed, 05 Dec 2018 16:02:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VUPgnCIp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728970AbeLFACj (ORCPT + 31 others); Wed, 5 Dec 2018 19:02:39 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:35842 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728895AbeLFACg (ORCPT ); Wed, 5 Dec 2018 19:02:36 -0500 Received: by mail-wr1-f68.google.com with SMTP id u3so21459139wrs.3 for ; Wed, 05 Dec 2018 16:02:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PNmL/AdZMFDm2CB5drDSBkoW5xhj23+00GAIyKewIVI=; b=VUPgnCIp6r7k5KBwRwMFL8puawcIoULPgPs+UA+EbBqAVd4TX8Ezif3EHUi19sFbaZ xaBLQbu9jsZkdKHy9cVsqNPfYmVOawXh/HmnLvC3k5hMe5IOVcfqLKQMODiZIslmqnaz MpR6a3HBqZ3aIXbna9ApQA6NT2/RdPsNslszo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PNmL/AdZMFDm2CB5drDSBkoW5xhj23+00GAIyKewIVI=; b=BHsOlfbpz0WG9Rwrbjmtz1p/KdaEy6nj1vglYJW3Nv+uiwUzOV/GGHqjRrRm0puYHV C3vTk4IfZ2Iz/VRwsbtb54y2c3AEBSAjbT57UvZ7oo+5uGbhpXzBCsV5BcE3ams1osPS SUNFRxPbM9HrATxwnHMVgJX0QfRfs988pTHp1wu0tgYNcu9zna+k994OoY2ObSZjFQ2N 1hrAaOprj4U/sll6pEXBzLer3Qo75dCypjKt9hdZIiDGzAHyDfBtViLsvz3+qGeDY1uG dkyaqOg07rj9WhsfHnL5lY2k/OlFxOz4GtN6FxBU40t6X8dAaUkmMC+z++rfDXeR12KU jMVw== X-Gm-Message-State: AA+aEWbN8aSc7EF/9hqDwHt9dnQuIUK13aoIZ98aUBNon4w2mEb6SCeH fcldV8nCuxwSLN2qP6TABa/zzQ== X-Received: by 2002:adf:8323:: with SMTP id 32mr22410873wrd.176.1544054553692; Wed, 05 Dec 2018 16:02:33 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:cf0e:17bd:f425:fac3]) by smtp.gmail.com with ESMTPSA id i9sm23241184wrs.34.2018.12.05.16.02.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 05 Dec 2018 16:02:32 -0800 (PST) From: Mike Leach To: mike.leach@linaro.org, linux@armlinux.org.uk, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com Subject: [PATCH v3 1/2] drivers: amba: Updates to component identification for driver matching. Date: Thu, 6 Dec 2018 00:02:25 +0000 Message-Id: <20181206000226.2507-2-mike.leach@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181206000226.2507-1-mike.leach@linaro.org> References: <20181206000226.2507-1-mike.leach@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components. The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID. Bits 15:12 of the CID are defined to be the device class. Class 0xF remains for PrimeCell and legacy components. Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support at present. Class 0x2-0x8,0xA and 0xD-0xD are presently reserved. The specification futher defines which classes of device use the standard CID/PID pair, and when additional ID registers are required. The patches provide an update of amba_device and matching code to handle the additional registers required for the Class 0x9 (CoreSight) UCI. The *data pointer in the amba_id is used by the driver to provide extended ID register values for matching. CoreSight components where PID/CID pair is currently sufficient for unique identification need not provide this additional information. Signed-off-by: Mike Leach --- drivers/amba/bus.c | 45 +++++++++++++++++++++++++++++++++------- include/linux/amba/bus.h | 32 ++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+), 8 deletions(-) -- 2.19.1 Reviewed-by: Mathieu Poirier diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index 41b706403ef7..524296a0eba0 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -26,19 +26,36 @@ #define to_amba_driver(d) container_of(d, struct amba_driver, drv) -static const struct amba_id * -amba_lookup(const struct amba_id *table, struct amba_device *dev) +/* called on periphid match and class 0x9 coresight device. */ +static int +amba_cs_uci_id_match(const struct amba_id *table, struct amba_device *dev) { int ret = 0; + struct amba_cs_uci_id *uci; + + uci = table->data; + /* no table data - return match on periphid */ + if (!uci) + return 1; + + /* test against read devtype and masked devarch value */ + ret = (dev->uci.devtype == uci->devtype) && + ((dev->uci.devarch & uci->devarch_mask) == uci->devarch); + return ret; +} + +static const struct amba_id * +amba_lookup(const struct amba_id *table, struct amba_device *dev) +{ while (table->mask) { - ret = (dev->periphid & table->mask) == table->id; - if (ret) - break; + if (((dev->periphid & table->mask) == table->id) && + ((dev->cid != CORESIGHT_CID) || + (amba_cs_uci_id_match(table, dev)))) + return table; table++; } - - return ret ? table : NULL; + return NULL; } static int amba_match(struct device *dev, struct device_driver *drv) @@ -399,10 +416,22 @@ static int amba_device_try_add(struct amba_device *dev, struct resource *parent) cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << (i * 8); + if (cid == CORESIGHT_CID) { + /* set the base to the start of the last 4k block */ + void __iomem *csbase = tmp + size - 4096; + + dev->uci.devarch = + readl(csbase + UCI_REG_DEVARCH_OFFSET); + dev->uci.devtype = + readl(csbase + UCI_REG_DEVTYPE_OFFSET) & 0xff; + } + amba_put_disable_pclk(dev); - if (cid == AMBA_CID || cid == CORESIGHT_CID) + if (cid == AMBA_CID || cid == CORESIGHT_CID) { dev->periphid = pid; + dev->cid = cid; + } if (!dev->periphid) ret = -ENODEV; diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index d143c13bed26..8c0f392e4da2 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -25,6 +25,36 @@ #define AMBA_CID 0xb105f00d #define CORESIGHT_CID 0xb105900d +/* + * CoreSight Architecture specification updates the ID specification + * for components on the AMBA bus. (ARM IHI 0029E) + * + * Bits 15:12 of the CID are the device class. + * + * Class 0xF remains for PrimeCell and legacy components. (AMBA_CID above) + * Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) + * Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support + * at present. + * Class 0x2-0x8,0xA and 0xD-0xD are presently reserved. + * + * Remaining CID bits stay as 0xb105-00d + */ + +/* + * Class 0x9 components use additional values to form a Unique Component + * Identifier (UCI), where peripheral ID values are identical for different + * components. Passed to the amba bus code from the component driver via + * the amba_id->data pointer. + */ +struct amba_cs_uci_id { + unsigned int devarch; + unsigned int devarch_mask; + unsigned int devtype; +}; + +#define UCI_REG_DEVTYPE_OFFSET 0xFCC +#define UCI_REG_DEVARCH_OFFSET 0xFBC + struct clk; struct amba_device { @@ -32,6 +62,8 @@ struct amba_device { struct resource res; struct clk *pclk; unsigned int periphid; + unsigned int cid; + struct amba_cs_uci_id uci; unsigned int irq[AMBA_NR_IRQS]; char *driver_override; }; From patchwork Thu Dec 6 00:02:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 152974 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp9903439ljp; Wed, 5 Dec 2018 16:02:43 -0800 (PST) X-Google-Smtp-Source: AFSGD/WQAU2LFu+03DhB7YF3AWl9w0XYLNPoASNfxPtLPSouRgB/sezKyUqErZPkbPlxJHjlAfsw X-Received: by 2002:a62:5884:: with SMTP id m126mr26275778pfb.177.1544054563725; Wed, 05 Dec 2018 16:02:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544054563; cv=none; d=google.com; s=arc-20160816; b=GyrY6S+EolZlW01yozwqfrDoCAZj7Ye4EowWrMlprz8A7H5+9WkpONli9ay//wIUdD jlx6M4ugbFglHFoIIvBRZneOCqVUuyFnsqn3qS8dVpycz8tmeb/4i/OhG7dCNEEpsUa9 oXj0VDbSWEtkZMzY0LP9Hxw48+3JgCacRKOi2cSBWs91ffOHh/BkvdRZ8P5HSTYYOdUW WO+rK8BgvzUcNJQwYjOaCi3pet05He4O5VOx54WP62c9kU6z633/IY1Q7YlKMqSkGSar YsAJfr2YCdRMN0rp9LjTj5Hj3VzgB3pmOdHyIg44bKinec3wfY4uetV8D5xPWwDo8o6+ B+Rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lGHDul39zNeZWBwTbhWQ3Y086neguPWhN09izxgMWVw=; b=evREUEXlIfS2BGuH1jXImRk5qVMcYJeO42rE2prCZb3Lna5oB4VxIrBld7zkVFngBo vIgC8FfFoF+C4fObxFttyGI6eaY5lOgfchkn7M98uter5EUHyGFL1CmqT14YiJCTQ0HL 0R269Ymjrn9iXtj+NTtvVjer4N/U0XsTkojduK+ahr2D/T/qB1DQ+Qvfkw0BoZvXtqU8 Ma1o8vgMybYXNDSnl850Ns02cUhr34nvPVQiMYhTv30zNEqus2hLjYCTVv9iYXRDFvCz b1q4JF5aWMQdpG9ofpHPPrHEB69a7HjhmZUrvvUXBC45EcxKferhofP6Oc0+/bHusIUJ 1DVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gG+UfqWj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z22si22006398pfd.197.2018.12.05.16.02.43; Wed, 05 Dec 2018 16:02:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gG+UfqWj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728596AbeLFACl (ORCPT + 31 others); Wed, 5 Dec 2018 19:02:41 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:46559 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728701AbeLFACg (ORCPT ); Wed, 5 Dec 2018 19:02:36 -0500 Received: by mail-wr1-f67.google.com with SMTP id l9so21469445wrt.13 for ; Wed, 05 Dec 2018 16:02:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lGHDul39zNeZWBwTbhWQ3Y086neguPWhN09izxgMWVw=; b=gG+UfqWju0f6a7nHRvauIN0ynw03rVtRJqbOTVvnkM2gZ8D6YJPN+U6K/nxVNwO/9s z3x6Gt2G2eUrSgEY6QG+98vGpgR6lP8XQX3EogJbssU+6MTZVT5Uo4wbwe3B1uUFu/FP VUSxhx01yjEKVdMZoiWvxGtjjmkbfb64rR4NY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lGHDul39zNeZWBwTbhWQ3Y086neguPWhN09izxgMWVw=; b=iIqrsr74kh3u4a2aSbf9Xs1kItAJM2Hfr/aEuo8CBe8gz0rCO5458BQTCEumW0tUyZ SbUkIpJitpFN1JKS/penaGTJsWxUniE9fM0XyT62rQiqdbNPFnPA+Q4Iz9pIDe1sNlWz 9OzP24rh/8SXnUfaEkO2OyQIwO/y/xUs9IJgMi5C72mLxdWSrArMGh4oKyBjtofbgeWm g5AgyXc46jP77k6ew/dxcrA8DnNTc5siLbIFfoe8ftZRyd5fs11OfYZNr38JSYrLoV+m 9lTzr/JMl9wAzrfnglNzw7QSOE6qQ0YSl7/rq9aNpDWwzd9REleVnm2uPzyEV0cpvwAQ m8FQ== X-Gm-Message-State: AA+aEWYUDF6u00kIxCZQuhBovZd8ynCWKzp0keErZoA9kZoI2xfw8YpC Qye4yLtbmrY75Z5ZF3zaP2Dv6A== X-Received: by 2002:adf:dfd1:: with SMTP id q17mr24530716wrn.27.1544054555123; Wed, 05 Dec 2018 16:02:35 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:cf0e:17bd:f425:fac3]) by smtp.gmail.com with ESMTPSA id i9sm23241184wrs.34.2018.12.05.16.02.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 05 Dec 2018 16:02:34 -0800 (PST) From: Mike Leach To: mike.leach@linaro.org, linux@armlinux.org.uk, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com Subject: [PATCH v3 2/2] coresight: etmv4: Update ID register table to add UCI support Date: Thu, 6 Dec 2018 00:02:26 +0000 Message-Id: <20181206000226.2507-3-mike.leach@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181206000226.2507-1-mike.leach@linaro.org> References: <20181206000226.2507-1-mike.leach@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Updates the ID register tables to contain a UCI entry for the A35 ETM device to allow correct matching of driver in the amba bus code. Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/coresight-etm4x.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) -- 2.19.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 53e2fb6e86f6..2fb8054e43ab 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1073,12 +1073,28 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) .mask = 0x000fffff, \ } +static struct amba_cs_uci_id uci_id_etm4[] = { + { + /* ETMv4 UCI data */ + .devarch = 0x47704a13, + .devarch_mask = 0xfff0ffff, + .devtype = 0x00000013, + } +}; + +#define ETM4x_AMBA_UCI_ID(pid) \ + { \ + .id = pid, \ + .mask = 0x000fffff, \ + .data = uci_id_etm4, \ + } + static const struct amba_id etm4_ids[] = { ETM4x_AMBA_ID(0x000bb95d), /* Cortex-A53 */ ETM4x_AMBA_ID(0x000bb95e), /* Cortex-A57 */ ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */ ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */ - ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */ + ETM4x_AMBA_UCI_ID(0x000bb9da), /* Cortex-A35 */ {}, };