From patchwork Fri Mar 11 09:45:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 550704 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0150C433FE for ; Fri, 11 Mar 2022 09:45:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347673AbiCKJqd (ORCPT ); Fri, 11 Mar 2022 04:46:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347649AbiCKJq2 (ORCPT ); Fri, 11 Mar 2022 04:46:28 -0500 Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D7141BE4D8; Fri, 11 Mar 2022 01:45:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1646991924; x=1678527924; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HGte/zaS5mfJUA4/Q4DGs8r+NCytaCeHNe8LA2QiASY=; b=m9KCbxlJCv+udCdeH0UTFeus96wzYIUKN9pTop2RX5Fd+luLE2vDpFCS 75nIXFKQ1aPgEzniLjIJjyhyL6Hr2C+mIVHCoV3dUx6IpXj2l3TWI8nxm 06H2TpVMb9BB4rP/QTku4d/wjowePuoO/LognOsU1hBP84UyCYFsQKyKx Feu0D9aleBLCk6wu444hdJZWndQk30LuazgSt60DE7oBGYbSEvpeuaEWE kv36kzXpL+QeK9vwLEoyFXnzwrrzfVl8t26hDeZGTH3IN9wUNuBkxPPHO ek7EH92HaYfi5fw2CMuE/r98uiEc+dtaYDhYadJQn0BswtPjWzBoDnBlG g==; From: Vincent Whitchurch To: , , CC: , Vincent Whitchurch , , , , , , , Subject: [PATCH v2 1/2] dt-bindings: serial: samsung: Add ARTPEC-8 UART Date: Fri, 11 Mar 2022 10:45:14 +0100 Message-ID: <20220311094515.3223023-2-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220311094515.3223023-1-vincent.whitchurch@axis.com> References: <20220311094515.3223023-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add a compatible for the UART on the ARTPEC-8 SoC. This hardware block is closely related to the variants used on the Exynos chips. The register layout is identical to Exynos850 et al but the fifo size is different (64 bytes in each direction for all instances). Signed-off-by: Vincent Whitchurch Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- Notes: v2: - Expand commit message. - Define required clocks. Documentation/devicetree/bindings/serial/samsung_uart.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index 2940afb874b3..c2423144a4d6 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -20,6 +20,7 @@ properties: items: - enum: - apple,s5l-uart + - axis,artpec8-uart - samsung,s3c2410-uart - samsung,s3c2412-uart - samsung,s3c2440-uart @@ -110,6 +111,7 @@ allOf: contains: enum: - apple,s5l-uart + - axis,artpec8-uart - samsung,exynos4210-uart then: properties: From patchwork Fri Mar 11 09:45:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 550703 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E0E5C4167B for ; Fri, 11 Mar 2022 09:45:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347685AbiCKJqe (ORCPT ); Fri, 11 Mar 2022 04:46:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238116AbiCKJqc (ORCPT ); Fri, 11 Mar 2022 04:46:32 -0500 Received: from smtp2.axis.com (smtp2.axis.com [195.60.68.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EE281BE4C9; Fri, 11 Mar 2022 01:45:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1646991929; x=1678527929; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QOMLzEesVg6HYaOAZ4KCgGOM/7fxz+rqf2h1kQQi9LY=; b=BNklQVJb0nsShtPM3oe2hhSmq3alWsefd/ByhcFCKALmM6GV3CYDmS4l HVVn47z4n7iRZ23+/k3sunyeBw9YMgSkBcNFL8Oo+YRirSRw52yYz3R51 mvZT3/GIRYtA/o9Xsv3OCdpkyoSj9K5mC+U3NUkz87qerkPPjU+L7Lw44 YlO/nncNZS4NsPNbhaBn6Dsq7yqmv5CTZpLypwmEGfv4ubPSOP0iUH+Rz nlSN3jMv4GBrMCsDRbkPEmM4+hACTUptAqwnf/L/8z3NxhfHZT2xThWaN tZHszSbEnikF6Aw5Mh8DVAIBEcs7Hj4OAzXuChhRgB6rBw3oFzbsoo+Gi Q==; From: Vincent Whitchurch To: , , CC: , Vincent Whitchurch , , , , , , , Subject: [PATCH v2 2/2] tty: serial: samsung: Add ARTPEC-8 support Date: Fri, 11 Mar 2022 10:45:15 +0100 Message-ID: <20220311094515.3223023-3-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220311094515.3223023-1-vincent.whitchurch@axis.com> References: <20220311094515.3223023-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add support for the UART block on the ARTPEC-8 SoC. This is closely related to the variants used on the Exynos chips. The register layout is identical to Exynos850 et al but the fifo size is different (64 bytes in each direction for all instances). Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vincent Whitchurch --- Notes: v2: - Added Krzysztof's Reviewed-by. - Expanded commit message - Fixed fifo size - Rebased on top of Krzysztof's "minor fixes/cleanups" series. This needed a couple of fixes for build errors. (I'm always unsure if Reviewed-by should be carried over or not if the fixes are minor. I apologize in advance if carring it over was the wrong thing to do in this case.) drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/samsung_tty.c | 37 ++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 0e5ccb25bdb1..bd46e35ded40 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -236,7 +236,7 @@ config SERIAL_CLPS711X_CONSOLE config SERIAL_SAMSUNG tristate "Samsung SoC serial support" - depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || ARCH_APPLE || COMPILE_TEST + depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || ARCH_APPLE || ARCH_ARTPEC || COMPILE_TEST select SERIAL_CORE help Support for the on-chip UARTs on the Samsung diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 74d466cc4152..7d011d3fa3a6 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2828,6 +2828,36 @@ static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = { #define S5L_SERIAL_DRV_DATA NULL #endif +#if defined(CONFIG_ARCH_ARTPEC) +static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = { + .info = { + .name = "Axis ARTPEC-8 UART", + .type = TYPE_S3C6400, + .port_type = PORT_S3C6400, + .fifosize = 64, + .has_divslot = 1, + .rx_fifomask = S5PV210_UFSTAT_RXMASK, + .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, + .rx_fifofull = S5PV210_UFSTAT_RXFULL, + .tx_fifofull = S5PV210_UFSTAT_TXFULL, + .tx_fifomask = S5PV210_UFSTAT_TXMASK, + .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, + .def_clk_sel = S3C2410_UCON_CLKSEL0, + .num_clks = 1, + .clksel_mask = 0, + .clksel_shift = 0, + }, + .def_cfg = { + .ucon = S5PV210_UCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + .has_fracval = 1, + } +}; +#define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data) +#else +#define ARTPEC8_SERIAL_DRV_DATA (NULL) +#endif + static const struct platform_device_id s3c24xx_serial_driver_ids[] = { { .name = "s3c2410-uart", @@ -2856,6 +2886,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = { }, { .name = "exynos850-uart", .driver_data = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA, + }, { + .name = "artpec8-uart", + .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, }, { }, }; @@ -2881,6 +2914,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { .data = S5L_SERIAL_DRV_DATA }, { .compatible = "samsung,exynos850-uart", .data = EXYNOS850_SERIAL_DRV_DATA }, + { .compatible = "axis,artpec8-uart", + .data = ARTPEC8_SERIAL_DRV_DATA }, {}, }; MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); @@ -3034,6 +3069,8 @@ OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart", s5pv210_early_console_setup); OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart", s5pv210_early_console_setup); +OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart", + s5pv210_early_console_setup); /* Apple S5L */ static int __init apple_s5l_early_console_setup(struct earlycon_device *device,