From patchwork Tue Mar 8 14:24:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 549443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73B56C41535 for ; Tue, 8 Mar 2022 14:24:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347429AbiCHOZZ (ORCPT ); Tue, 8 Mar 2022 09:25:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347353AbiCHOZX (ORCPT ); Tue, 8 Mar 2022 09:25:23 -0500 Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A236347AF5; Tue, 8 Mar 2022 06:24:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1646749467; x=1678285467; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6KwAXn4jvSph/kkMgeY9egBCzjFV3kNndn+PTRpZ548=; b=gKmdEYXwJY8KE9ZYdnBVVQtB70opXBFB+odyd2FHOGMCIoxFBwUyFEa1 XPgSZNVeLUtEGYmjhhBb625SYjZLOIx7otitfxn5691lBZzcoGl9+Z+0z WpbM0YIphiocp0362ZP4M0yVQtjWzFFpWlqQuE6qDox+Fi32ylZMvfEtD HvwH3vOuHoT9PfWHb5A7N68h7P7QlyRBeKtX7KerqdF3g/KoaBpGMiNk3 4/DMvuaBcbLJWGNA5OymjYGNy8iOG2+QUinBq3Qck+rPZ8Zj6BlPRvzaM Vx+4vhyt3IqIqkOJBOFs3EVozN4Frnjgw7wQ/hV0Jto63X/YMpbTQQlEx g==; From: Vincent Whitchurch To: , , CC: , , , , , , , Vincent Whitchurch Subject: [PATCH v2 2/4] dt-bindings: timer: exynos4210-mct: Support using only local timer Date: Tue, 8 Mar 2022 15:24:08 +0100 Message-ID: <20220308142410.3193729-3-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220308142410.3193729-1-vincent.whitchurch@axis.com> References: <20220308142410.3193729-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ARTPEC-8 SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which share one MCT with one global and eight local timers. The Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and therefore run two separate kernels. The Cortex-A53 boots first and starts the global FRC and also registers a clock events device using the global timer. (This global timer clock events is usually replaced by arch timer clock events for each of the cores.) When the A5 boots, we should not use the global timer interrupts or write to the global timer registers. This is because even if there are four global comparators, the control bits for all four are in the same registers, and we would need to synchronize between the cpus. Instead, the global timer FRC (already started by the A53) should be used as the clock source, and one of the local timers which are not used by the A53 can be used for clock events on the A5. To support this usecase, add a property to the binding to specify the first local timer index to be used. If this parameter is non-zero, the global timer interrupts will also not be used. Signed-off-by: Vincent Whitchurch --- Notes: v2: New. .../bindings/timer/samsung,exynos4210-mct.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index dce42f1f7574..46f466081836 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -47,6 +47,15 @@ properties: reg: maxItems: 1 + local-timer-index: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + maximum: 15 # Last local timer index + description: | + If present, sets the first local timer index to use. If this value is + set to a non-default value, the global timer will not be used for + interrupts. + interrupts: description: | Interrupts should be put in specific order. This is, the local timer From patchwork Tue Mar 8 14:24:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 549445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8033AC43217 for ; Tue, 8 Mar 2022 14:24:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344413AbiCHOZW (ORCPT ); Tue, 8 Mar 2022 09:25:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343682AbiCHOZU (ORCPT ); Tue, 8 Mar 2022 09:25:20 -0500 Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 439D84B849; Tue, 8 Mar 2022 06:24:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1646749463; x=1678285463; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gchs80jcH+/5TFd0a5Cy8wkt4l2VcoMbwk5kapLsbnY=; b=YecgrHTgaYodtEGv0gXOUJy10uw57FE8fGJKquWmmLk69aponOEHrFNa znlWt91z98sQSQ6pEML2n+Y76vFXDsqDONHbLrkTiUMo/RmNN32cJ3Z+5 y9Lm4VFzP2kgPzxArDiK4Aw9Ubhi2A7du40fyLqWX0eztSH2lgipU5q7U 9BcKFmwT62RJXQdSFTAL5ZOVbzKOLNyNLykaAl3LXTP5cAfY5JIg2XINC yBZQ5SWdCCxvgBgqpyWF+Gbg9VJq7bAt/zam0LdmypHoPEpJ6xpZgGitX AoVk8ylL62wVFShbZxohe0+TF+qrYKZIIBdBcKI9hIUFakXIOLyEGA04A Q==; From: Vincent Whitchurch To: , , CC: , , , , , , , Vincent Whitchurch Subject: [PATCH v2 4/4] clocksource/drivers/exynos_mct: Enable building on ARTPEC Date: Tue, 8 Mar 2022 15:24:10 +0100 Message-ID: <20220308142410.3193729-5-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220308142410.3193729-1-vincent.whitchurch@axis.com> References: <20220308142410.3193729-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This timer block is used on ARTPEC-8. Signed-off-by: Vincent Whitchurch --- Notes: v2: No changes. drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index ae95d06a4a8f..2ea981ef23af 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -419,7 +419,7 @@ config ATMEL_TCB_CLKSRC config CLKSRC_EXYNOS_MCT bool "Exynos multi core timer driver" if COMPILE_TEST depends on ARM || ARM64 - depends on ARCH_EXYNOS || COMPILE_TEST + depends on ARCH_ARTPEC || ARCH_EXYNOS || COMPILE_TEST help Support for Multi Core Timer controller on Exynos SoCs.