From patchwork Fri Feb 25 19:21:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 548337 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AD2EC433EF for ; Fri, 25 Feb 2022 19:22:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232909AbiBYTWd (ORCPT ); Fri, 25 Feb 2022 14:22:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231551AbiBYTWc (ORCPT ); Fri, 25 Feb 2022 14:22:32 -0500 Received: from so254-9.mailgun.net (so254-9.mailgun.net [198.61.254.9]) by lindbergh.monkeyblade.net (Postfix) with UTF8SMTPS id 745EB1AE671 for ; Fri, 25 Feb 2022 11:21:59 -0800 (PST) DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1645816919; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=XlQOgqUg+qM4j70seDDgBCK3GOdeY/KDt3HMzK3r7eU=; b=ZSQ0QdP4kZ/UPfvDzWOdWuonkBth4myWez+JsZ8F+12L3eE882/+by230AsICmbK8k8AtImZ 2QH0bgaaxF8HWl4ncxZpgFhOn0p+uJsYQpBx4/7AMIjSf9leh5kbRXmqcgi7qf7cVITZVe28 IC0mh4nFsmevCpGapbXSb1uXyuY= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n03.prod.us-east-1.postgun.com with SMTP id 62192c576f8d3f1389bd1e85 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 25 Feb 2022 19:21:59 GMT Sender: quic_akhilpo=quicinc.com@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 784F0C43616; Fri, 25 Feb 2022 19:21:58 +0000 (UTC) Received: from hyd-lnxbld559.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akhilpo) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2FC54C43618; Fri, 25 Feb 2022 19:21:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.codeaurora.org 2FC54C43618 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=quicinc.com From: Akhil P Oommen To: freedreno , dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS , Dmitry Baryshkov , Bjorn Andersson Cc: Abhinav Kumar , AngeloGioacchino Del Regno , =?utf-8?q?Christian_K=C3=B6nig?= , Daniel Vetter , David Airlie , Jonathan Marek , Jordan Crouse , Sean Paul , Stephen Boyd , Vladimir Lypak , Yangtao Li , linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] drm/msm/adreno: Generate name from chipid for 7c3 Date: Sat, 26 Feb 2022 00:51:29 +0530 Message-Id: <20220226005021.v2.2.I9436e0e300f76b2e6c34136a0b902e8cfd73e0d6@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1645816893-22815-1-git-send-email-quic_akhilpo@quicinc.com> References: <1645816893-22815-1-git-send-email-quic_akhilpo@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use a gpu name which is sprintf'ed from the chipid for 7c3 gpu instead of hardcoding one. This helps to avoid code churn in case of a gpu rename. Signed-off-by: Akhil P Oommen --- Changes in v2: - use devm_kasprintf() to generate gpu name (Rob) drivers/gpu/drm/msm/adreno/adreno_device.c | 1 - drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 +++++++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index fb26193..89cfd84 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -318,7 +318,6 @@ static const struct adreno_info gpulist[] = { .hwcg = a660_hwcg, }, { .rev = ADRENO_REV(6, 3, 5, ANY_ID), - .name = "Adreno 7c Gen 3", .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a660_gmu.bin", diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index f33cfa4..d9d0c13 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -929,12 +929,23 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_platform_config *config = dev->platform_data; struct msm_gpu_config adreno_gpu_config = { 0 }; struct msm_gpu *gpu = &adreno_gpu->base; + struct adreno_rev *rev = &config->rev; + const char *gpu_name; adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); adreno_gpu->gmem = adreno_gpu->info->gmem; adreno_gpu->revn = adreno_gpu->info->revn; - adreno_gpu->rev = config->rev; + adreno_gpu->rev = *rev; + + gpu_name = adreno_gpu->info->name; + if (!gpu_name) { + gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d", + rev->core, rev->major, rev->minor, + rev->patchid); + if (!gpu_name) + return -ENOMEM; + } adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; @@ -948,7 +959,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, pm_runtime_enable(dev); return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, - adreno_gpu->info->name, &adreno_gpu_config); + gpu_name, &adreno_gpu_config); } void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) From patchwork Fri Feb 25 19:21:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 548336 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 288F0C433F5 for ; Fri, 25 Feb 2022 19:22:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231551AbiBYTWp (ORCPT ); Fri, 25 Feb 2022 14:22:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234411AbiBYTWo (ORCPT ); Fri, 25 Feb 2022 14:22:44 -0500 Received: from m43-7.mailgun.net (m43-7.mailgun.net [69.72.43.7]) by lindbergh.monkeyblade.net (Postfix) with UTF8SMTPS id 3D2D21AE67F for ; Fri, 25 Feb 2022 11:22:11 -0800 (PST) DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1645816931; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=zwUj2HrkpS+nK6ojajWXOkTTihq6951vwdHqmJ0CDco=; b=rBlBdygRYt0ZQNnDqvqZOFuFWULudoMOvOvNvY5pq+QVzKSZqw3MDMbkYv2xaFpWCskRFY+I 21dW+lsxv8uAGal4yrAHMekZZMEyf3gw85DBEL1su82LNJkelBHpxnV+oMhlbBm/bUQOPViC 3OfL/hXlxsHfEajsYcAAUL7wRsw= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n05.prod.us-east-1.postgun.com with SMTP id 62192c6218892df15f9a999c (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 25 Feb 2022 19:22:10 GMT Sender: quic_akhilpo=quicinc.com@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id BFF02C4360D; Fri, 25 Feb 2022 19:22:09 +0000 (UTC) Received: from hyd-lnxbld559.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akhilpo) by smtp.codeaurora.org (Postfix) with ESMTPSA id 538AFC43617; Fri, 25 Feb 2022 19:22:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.codeaurora.org 538AFC43617 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=quicinc.com From: Akhil P Oommen To: freedreno , dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS , Dmitry Baryshkov , Bjorn Andersson Cc: Abhinav Kumar , =?utf-8?q?Christian_K=C3=B6ni?= =?utf-8?q?g?= , Daniel Vetter , David Airlie , Douglas Anderson , Jonathan Marek , Jordan Crouse , Sean Paul , Stephen Boyd , Vladimir Lypak , Yangtao Li , linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] drm/msm/adreno: Expose speedbin to userspace Date: Sat, 26 Feb 2022 00:51:31 +0530 Message-Id: <20220226005021.v2.4.I86c32730e08cba9e5c83f02ec17885124d45fa56@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1645816893-22815-1-git-send-email-quic_akhilpo@quicinc.com> References: <1645816893-22815-1-git-send-email-quic_akhilpo@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Expose speedbin through MSM_PARAM_CHIP_ID parameter to help userspace identify the sku. Signed-off-by: Akhil P Oommen --- (no changes since v1) drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +-- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 +++++++++++++++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++ 3 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index f308a3f..e2728be3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -10,7 +10,6 @@ #include #include -#include #include #define GPU_PAS_ID 13 @@ -1774,7 +1773,7 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) u32 speedbin; int ret; - ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", &speedbin); + ret = adreno_read_speedbin(dev, &speedbin); /* * -ENOENT means that the platform doesn't support speedbin which is * fine diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index d9d0c13..c593d13 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include "adreno_gpu.h" #include "a6xx_gpu.h" @@ -242,10 +243,12 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0; return 0; case MSM_PARAM_CHIP_ID: - *value = adreno_gpu->rev.patchid | - (adreno_gpu->rev.minor << 8) | - (adreno_gpu->rev.major << 16) | - (adreno_gpu->rev.core << 24); + *value = (uint64_t) adreno_gpu->rev.patchid | + (uint64_t) (adreno_gpu->rev.minor << 8) | + (uint64_t) (adreno_gpu->rev.major << 16) | + (uint64_t) (adreno_gpu->rev.core << 24); + if (!adreno_gpu->info->revn) + *value |= ((uint64_t) adreno_gpu->speedbin) << 32; return 0; case MSM_PARAM_MAX_FREQ: *value = adreno_gpu->base.fast_rate; @@ -921,6 +924,11 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) adreno_ocmem->hdl); } +int adreno_read_speedbin(struct device *dev, u32 *speedbin) +{ + return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); +} + int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs, int nr_rings) @@ -931,6 +939,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu *gpu = &adreno_gpu->base; struct adreno_rev *rev = &config->rev; const char *gpu_name; + u32 speedbin; adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); @@ -938,6 +947,10 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->revn = adreno_gpu->info->revn; adreno_gpu->rev = *rev; + if (adreno_read_speedbin(dev, &speedbin) || !speedbin) + speedbin = 0xffff; + adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); + gpu_name = adreno_gpu->info->name; if (!gpu_name) { gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d", diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index cffabe7..e2a7150 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -80,6 +80,7 @@ struct adreno_gpu { const struct adreno_info *info; uint32_t gmem; /* actual gmem size */ uint32_t revn; /* numeric revision name */ + uint16_t speedbin; const struct adreno_gpu_funcs *funcs; /* interesting register offsets to dump: */ @@ -324,6 +325,8 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu, void adreno_set_llc_attributes(struct iommu_domain *iommu); +int adreno_read_speedbin(struct device *dev, u32 *speedbin); + /* * For a5xx and a6xx targets load the zap shader that is used to pull the GPU * out of secure mode