From patchwork Thu Mar 3 08:08:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Polimera X-Patchwork-Id: 547894 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF12EC433FE for ; Thu, 3 Mar 2022 08:09:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231169AbiCCIJs (ORCPT ); Thu, 3 Mar 2022 03:09:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231136AbiCCIJ3 (ORCPT ); Thu, 3 Mar 2022 03:09:29 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 607A85FD2; Thu, 3 Mar 2022 00:08:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1646294924; x=1677830924; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=oEHygAuYx7ScDgeJr076Rg/5e143mby8KSvoAzMOeBE=; b=TzKbSJqOv7t1YFtg+e8u24576F6wqwGtktG5y/ixhenhkjKi4YwD3uq6 fooZQjhUKgUmqh9yR/pwQnP+JzIEbYZUB/jqCQ3p5Ar+/979qZ8wLXYwS lPa/+aCN9pnozOuBMooeGwozp2tt7WRpAn3mL9mhTmhLeHJqkqO9U3RYm 0=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 03 Mar 2022 00:08:44 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 03 Mar 2022 00:08:42 -0800 X-QCInternal: smtphost Received: from vpolimer-linux.qualcomm.com ([10.204.67.235]) by ironmsg02-blr.qualcomm.com with ESMTP; 03 Mar 2022 13:38:30 +0530 Received: by vpolimer-linux.qualcomm.com (Postfix, from userid 463814) id 10E274E1B; Thu, 3 Mar 2022 13:38:30 +0530 (IST) From: Vinod Polimera To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Vinod Polimera , linux-kernel@vger.kernel.org, robdclark@gmail.com, dianders@chromium.org, swboyd@chromium.org, quic_kalyant@quicinc.com Subject: [PATCH v3 1/3] arm64/dts/qcom/sc7280: remove assigned-clock-rate property for mdp clk Date: Thu, 3 Mar 2022 13:38:22 +0530 Message-Id: <1646294904-4753-2-git-send-email-quic_vpolimer@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1646294904-4753-1-git-send-email-quic_vpolimer@quicinc.com> References: <1646294904-4753-1-git-send-email-quic_vpolimer@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Kernel clock driver assumes that initial rate is the max rate for that clock and was not allowing it to scale beyond the assigned clock value. Drop the assigned clock rate property and vote on the mdp clock as per calculated value during the usecase. Changes in v2: - Remove assigned-clock-rate property and set mdp clk during resume sequence. - Add fixes tag. Changes in v3: - Remove extra line after fixes tag.(Stephen Boyd) - Add similar changes for sc7180, sdm845 which uses opp table for voting mdp clk.(Stephen Boyd) - Drop patch: "drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table" Fixes: 62fbdce91("arm64: dts: qcom: sc7280: add display dt nodes") Signed-off-by: Vinod Polimera --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index baf1653..408cf6c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2856,9 +2856,6 @@ "ahb", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = ; interrupt-controller; #interrupt-cells = <1>; @@ -2892,11 +2889,9 @@ "lut", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; - assigned-clock-rates = <300000000>, - <19200000>, + assigned-clock-rates = <19200000>, <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SC7280_CX>; From patchwork Thu Mar 3 08:08:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Polimera X-Patchwork-Id: 548194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28532C433FE for ; Thu, 3 Mar 2022 08:09:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231156AbiCCIJt (ORCPT ); Thu, 3 Mar 2022 03:09:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231140AbiCCIJc (ORCPT ); Thu, 3 Mar 2022 03:09:32 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01BB51704E9; Thu, 3 Mar 2022 00:08:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1646294926; x=1677830926; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=k18H4jQjqdXwe83FlKD0McInh52fikWbkf9CksAysLs=; b=bPltHlpXasyUc3rwgekRRUpGO1IqZotRGfnFlyGo8CBK0NaGbvqSxLCQ kpG8q11snss6KXaCrbcf7T3/oAZfMsNsNet8o3m0n5+NmtrLo+xknYwAj YVG+af/rJdBpjQbCvGSfVvTIq2McYO+stgTC6eZtyOaETvBO8yBRCtBwR c=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 03 Mar 2022 00:08:46 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 03 Mar 2022 00:08:44 -0800 X-QCInternal: smtphost Received: from vpolimer-linux.qualcomm.com ([10.204.67.235]) by ironmsg02-blr.qualcomm.com with ESMTP; 03 Mar 2022 13:38:31 +0530 Received: by vpolimer-linux.qualcomm.com (Postfix, from userid 463814) id 110D34E1C; Thu, 3 Mar 2022 13:38:31 +0530 (IST) From: Vinod Polimera To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Vinod Polimera , linux-kernel@vger.kernel.org, robdclark@gmail.com, dianders@chromium.org, swboyd@chromium.org, quic_kalyant@quicinc.com Subject: [PATCH v3 2/3] arm64/dts/qcom/sc7180: remove assigned-clock-rate property for mdp clk Date: Thu, 3 Mar 2022 13:38:23 +0530 Message-Id: <1646294904-4753-3-git-send-email-quic_vpolimer@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1646294904-4753-1-git-send-email-quic_vpolimer@quicinc.com> References: <1646294904-4753-1-git-send-email-quic_vpolimer@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Kernel clock driver assumes that initial rate is the max rate for that clock and was not allowing it to scale beyond the assigned clock value. Drop the assigned clock rate property and vote on the mdp clock as per calculated value during the usecase. Fixes: a3db7ad1af("arm64: dts: qcom: sc7180: add display dt nodes") Signed-off-by: Vinod Polimera --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index e1c46b8..eaab746 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2900,9 +2900,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "ahb", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = ; interrupt-controller; #interrupt-cells = <1>; @@ -2932,12 +2929,10 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "bus", "iface", "rot", "lut", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_ROT_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; - assigned-clock-rates = <300000000>, - <19200000>, + assigned-clock-rates = <19200000>, <19200000>, <19200000>; operating-points-v2 = <&mdp_opp_table>; From patchwork Thu Mar 3 08:08:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Polimera X-Patchwork-Id: 547895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FAE7C433EF for ; Thu, 3 Mar 2022 08:09:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230464AbiCCIJs (ORCPT ); Thu, 3 Mar 2022 03:09:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231142AbiCCIJd (ORCPT ); Thu, 3 Mar 2022 03:09:33 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F3961704F5; Thu, 3 Mar 2022 00:08:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1646294926; x=1677830926; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=knGo+0I6kiExJnkYlOIMEDQ7SnglzfM6cRK2vpYjK+4=; b=jn+g9Z/VtloZdQeNI5x7PnSvEk42v7i2jrnyDy8ziiKXCFNgy6U+FAuy jen8ZjQ1sf34WAM2doH5izFtxMYY6u6D2gcKmTVzQ6sawpw00W1QREDRf SzyuS74jUpO1VDt7eA/P9psXKgH52KR0shHaWZ/HzKJVd3MktypEZ1abf 0=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 03 Mar 2022 00:08:46 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 03 Mar 2022 00:08:44 -0800 X-QCInternal: smtphost Received: from vpolimer-linux.qualcomm.com ([10.204.67.235]) by ironmsg02-blr.qualcomm.com with ESMTP; 03 Mar 2022 13:38:33 +0530 Received: by vpolimer-linux.qualcomm.com (Postfix, from userid 463814) id E8ED24E1B; Thu, 3 Mar 2022 13:38:32 +0530 (IST) From: Vinod Polimera To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Vinod Polimera , linux-kernel@vger.kernel.org, robdclark@gmail.com, dianders@chromium.org, swboyd@chromium.org, quic_kalyant@quicinc.com Subject: [PATCH v3 3/3] arm64/dts/qcom/sdm845: remove assigned-clock-rate property for mdp clk Date: Thu, 3 Mar 2022 13:38:24 +0530 Message-Id: <1646294904-4753-4-git-send-email-quic_vpolimer@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1646294904-4753-1-git-send-email-quic_vpolimer@quicinc.com> References: <1646294904-4753-1-git-send-email-quic_vpolimer@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Kernel clock driver assumes that initial rate is the max rate for that clock and was not allowing it to scale beyond the assigned clock value. Drop the assigned clock rate property and vote on the mdp clock as per calculated value during the usecase. Fixes: 08c2a076d1("arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file") Signed-off-by: Vinod Polimera --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0d6286d..80dc486 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4181,9 +4181,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = ; interrupt-controller; #interrupt-cells = <1>; @@ -4214,10 +4211,8 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <300000000>, - <19200000>; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SDM845_CX>;