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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id d16-20020a17090ad99000b001bcbc4247a0sm2901211pjv.57.2022.03.03.12.46.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:46:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 1/7] target/nios2: Remove mmu_read_debug Date: Thu, 3 Mar 2022 10:46:18 -1000 Message-Id: <20220303204624.468786-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303204624.468786-1-richard.henderson@linaro.org> References: <20220303204624.468786-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::533 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This functionality can be had via plugins, if desired. In the meantime, it is unused code. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/helper.h | 1 - target/nios2/mmu.h | 1 - target/nios2/mmu.c | 20 -------------------- target/nios2/op_helper.c | 5 ----- target/nios2/translate.c | 17 ----------------- 5 files changed, 44 deletions(-) diff --git a/target/nios2/helper.h b/target/nios2/helper.h index 6c8f0b5b35..6d8eec1814 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -21,7 +21,6 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) #if !defined(CONFIG_USER_ONLY) -DEF_HELPER_2(mmu_read_debug, void, env, i32) DEF_HELPER_3(mmu_write, void, env, i32, i32) DEF_HELPER_1(check_interrupts, void, env) #endif diff --git a/target/nios2/mmu.h b/target/nios2/mmu.h index 4f46fbb82e..b7785b46c0 100644 --- a/target/nios2/mmu.h +++ b/target/nios2/mmu.h @@ -44,7 +44,6 @@ void mmu_flip_um(CPUNios2State *env, unsigned int um); unsigned int mmu_translate(CPUNios2State *env, Nios2MMULookup *lu, target_ulong vaddr, int rw, int mmu_idx); -void mmu_read_debug(CPUNios2State *env, uint32_t rn); void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v); void mmu_init(CPUNios2State *env); diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 2545c06761..5616c39d54 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -35,26 +35,6 @@ #define MMU_LOG(x) #endif -void mmu_read_debug(CPUNios2State *env, uint32_t rn) -{ - switch (rn) { - case CR_TLBACC: - MMU_LOG(qemu_log("TLBACC READ %08X\n", env->regs[rn])); - break; - - case CR_TLBMISC: - MMU_LOG(qemu_log("TLBMISC READ %08X\n", env->regs[rn])); - break; - - case CR_PTEADDR: - MMU_LOG(qemu_log("PTEADDR READ %08X\n", env->regs[rn])); - break; - - default: - break; - } -} - /* rw - 0 = read, 1 = write, 2 = fetch. */ unsigned int mmu_translate(CPUNios2State *env, Nios2MMULookup *lu, diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index a59003855a..61fc4dc903 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -26,11 +26,6 @@ #include "qemu/main-loop.h" #if !defined(CONFIG_USER_ONLY) -void helper_mmu_read_debug(CPUNios2State *env, uint32_t rn) -{ - mmu_read_debug(env, rn); -} - void helper_mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) { mmu_write(env, rn, v); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index f9abc2fdd2..194c8ebafd 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -448,23 +448,6 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) gen_check_supervisor(dc); switch (instr.imm5 + CR_BASE) { - case CR_PTEADDR: - case CR_TLBACC: - case CR_TLBMISC: - { -#if !defined(CONFIG_USER_ONLY) - if (likely(instr.c != R_ZERO)) { - tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]); -#ifdef DEBUG_MMU - TCGv_i32 tmp = tcg_const_i32(instr.imm5 + CR_BASE); - gen_helper_mmu_read_debug(cpu_R[instr.c], cpu_env, tmp); - tcg_temp_free_i32(tmp); -#endif - } -#endif - break; - } - default: if (likely(instr.c != R_ZERO)) { tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]); From patchwork Thu Mar 3 20:46:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 547813 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp969128imq; 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id d16-20020a17090ad99000b001bcbc4247a0sm2901211pjv.57.2022.03.03.12.46.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:46:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 2/7] target/nios2: Replace MMU_LOG with tracepoints Date: Thu, 3 Mar 2022 10:46:19 -1000 Message-Id: <20220303204624.468786-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303204624.468786-1-richard.henderson@linaro.org> References: <20220303204624.468786-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- meson.build | 1 + target/nios2/mmu.c | 96 ++++++++++++--------------------------- target/nios2/trace-events | 10 ++++ 3 files changed, 39 insertions(+), 68 deletions(-) create mode 100644 target/nios2/trace-events diff --git a/meson.build b/meson.build index a5b63e62cd..038502714a 100644 --- a/meson.build +++ b/meson.build @@ -2705,6 +2705,7 @@ if have_system or have_user 'target/i386', 'target/i386/kvm', 'target/mips/tcg', + 'target/nios2', 'target/ppc', 'target/riscv', 'target/s390x', diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 5616c39d54..306370f675 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -23,18 +23,10 @@ #include "cpu.h" #include "exec/exec-all.h" #include "mmu.h" +#include "trace/trace-target_nios2.h" #if !defined(CONFIG_USER_ONLY) -/* Define this to enable MMU debug messages */ -/* #define DEBUG_MMU */ - -#ifdef DEBUG_MMU -#define MMU_LOG(x) x -#else -#define MMU_LOG(x) -#endif - /* rw - 0 = read, 1 = write, 2 = fetch. */ unsigned int mmu_translate(CPUNios2State *env, Nios2MMULookup *lu, @@ -43,37 +35,26 @@ unsigned int mmu_translate(CPUNios2State *env, Nios2CPU *cpu = env_archcpu(env); int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; int vpn = vaddr >> 12; + int way, n_ways = cpu->tlb_num_ways; - MMU_LOG(qemu_log("mmu_translate vaddr %08X, pid %08X, vpn %08X\n", - vaddr, pid, vpn)); - - int way; - for (way = 0; way < cpu->tlb_num_ways; way++) { - - Nios2TLBEntry *entry = - &env->mmu.tlb[(way * cpu->tlb_num_ways) + - (vpn & env->mmu.tlb_entry_mask)]; - - MMU_LOG(qemu_log("TLB[%d] TAG %08X, VPN %08X\n", - (way * cpu->tlb_num_ways) + - (vpn & env->mmu.tlb_entry_mask), - entry->tag, (entry->tag >> 12))); + for (way = 0; way < n_ways; way++) { + uint32_t index = (way * n_ways) + (vpn & env->mmu.tlb_entry_mask); + Nios2TLBEntry *entry = &env->mmu.tlb[index]; if (((entry->tag >> 12) != vpn) || (((entry->tag & (1 << 11)) == 0) && ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) != pid))) { + trace_nios2_mmu_translate_miss(vaddr, pid, index, entry->tag); continue; } + lu->vaddr = vaddr & TARGET_PAGE_MASK; lu->paddr = (entry->data & CR_TLBACC_PFN_MASK) << TARGET_PAGE_BITS; lu->prot = ((entry->data & CR_TLBACC_R) ? PAGE_READ : 0) | ((entry->data & CR_TLBACC_W) ? PAGE_WRITE : 0) | ((entry->data & CR_TLBACC_X) ? PAGE_EXEC : 0); - MMU_LOG(qemu_log("HIT TLB[%d] %08X %08X %08X\n", - (way * cpu->tlb_num_ways) + - (vpn & env->mmu.tlb_entry_mask), - lu->vaddr, lu->paddr, lu->prot)); + trace_nios2_mmu_translate_hit(vaddr, pid, index, lu->paddr, lu->prot); return 1; } return 0; @@ -84,21 +65,18 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t pid) CPUState *cs = env_cpu(env); Nios2CPU *cpu = env_archcpu(env); int idx; - MMU_LOG(qemu_log("TLB Flush PID %d\n", pid)); for (idx = 0; idx < cpu->tlb_num_entries; idx++) { Nios2TLBEntry *entry = &env->mmu.tlb[idx]; - MMU_LOG(qemu_log("TLB[%d] => %08X %08X\n", - idx, entry->tag, entry->data)); - if ((entry->tag & (1 << 10)) && (!(entry->tag & (1 << 11))) && ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) == pid)) { uint32_t vaddr = entry->tag & TARGET_PAGE_MASK; - MMU_LOG(qemu_log("TLB Flush Page %08X\n", vaddr)); - + trace_nios2_mmu_flush_pid_hit(pid, idx, vaddr); tlb_flush_page(cs, vaddr); + } else { + trace_nios2_mmu_flush_pid_miss(pid, idx, entry->tag); } } } @@ -108,18 +86,15 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) CPUState *cs = env_cpu(env); Nios2CPU *cpu = env_archcpu(env); - MMU_LOG(qemu_log("mmu_write %08X = %08X\n", rn, v)); - switch (rn) { case CR_TLBACC: - MMU_LOG(qemu_log("TLBACC: IG %02X, FLAGS %c%c%c%c%c, PFN %05X\n", - v >> CR_TLBACC_IGN_SHIFT, - (v & CR_TLBACC_C) ? 'C' : '.', - (v & CR_TLBACC_R) ? 'R' : '.', - (v & CR_TLBACC_W) ? 'W' : '.', - (v & CR_TLBACC_X) ? 'X' : '.', - (v & CR_TLBACC_G) ? 'G' : '.', - v & CR_TLBACC_PFN_MASK)); + trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT, + (v & CR_TLBACC_C) ? 'C' : '.', + (v & CR_TLBACC_R) ? 'R' : '.', + (v & CR_TLBACC_W) ? 'W' : '.', + (v & CR_TLBACC_X) ? 'X' : '.', + (v & CR_TLBACC_G) ? 'G' : '.', + v & CR_TLBACC_PFN_MASK); /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) { @@ -138,16 +113,10 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) if ((entry->tag != newTag) || (entry->data != newData)) { if (entry->tag & (1 << 10)) { /* Flush existing entry */ - MMU_LOG(qemu_log("TLB Flush Page (OLD) %08X\n", - entry->tag & TARGET_PAGE_MASK)); tlb_flush_page(cs, entry->tag & TARGET_PAGE_MASK); } entry->tag = newTag; entry->data = newData; - MMU_LOG(qemu_log("TLB[%d] = %08X %08X\n", - (way * cpu->tlb_num_ways) + - (vpn & env->mmu.tlb_entry_mask), - entry->tag, entry->data)); } /* Auto-increment tlbmisc.WAY */ env->regs[CR_TLBMISC] = @@ -161,15 +130,14 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) break; case CR_TLBMISC: - MMU_LOG(qemu_log("TLBMISC: WAY %X, FLAGS %c%c%c%c%c%c, PID %04X\n", - v >> CR_TLBMISC_WAY_SHIFT, - (v & CR_TLBMISC_RD) ? 'R' : '.', - (v & CR_TLBMISC_WR) ? 'W' : '.', - (v & CR_TLBMISC_DBL) ? '2' : '.', - (v & CR_TLBMISC_BAD) ? 'B' : '.', - (v & CR_TLBMISC_PERM) ? 'P' : '.', - (v & CR_TLBMISC_D) ? 'D' : '.', - (v & CR_TLBMISC_PID_MASK) >> 4)); + trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT, + (v & CR_TLBMISC_RD) ? 'R' : '.', + (v & CR_TLBMISC_WR) ? 'W' : '.', + (v & CR_TLBMISC_DBL) ? '2' : '.', + (v & CR_TLBMISC_BAD) ? 'B' : '.', + (v & CR_TLBMISC_PERM) ? 'P' : '.', + (v & CR_TLBMISC_D) ? 'D' : '.', + (v & CR_TLBMISC_PID_MASK) >> 4); if ((v & CR_TLBMISC_PID_MASK) != (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) { @@ -193,11 +161,6 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) CR_TLBMISC_PID_SHIFT); env->regs[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK; env->regs[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT; - MMU_LOG(qemu_log("TLB READ way %d, vpn %05X, tag %08X, data %08X, " - "tlbacc %08X, tlbmisc %08X, pteaddr %08X\n", - way, vpn, entry->tag, entry->data, - env->regs[CR_TLBACC], env->regs[CR_TLBMISC], - env->regs[CR_PTEADDR])); } else { env->regs[CR_TLBMISC] = v; } @@ -206,9 +169,8 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) break; case CR_PTEADDR: - MMU_LOG(qemu_log("PTEADDR: PTBASE %03X, VPN %05X\n", - v >> CR_PTEADDR_PTBASE_SHIFT, - (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT)); + trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT, + (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT); /* Writes to PTEADDR don't change the read-back VPN value */ env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) | @@ -226,8 +188,6 @@ void mmu_init(CPUNios2State *env) Nios2CPU *cpu = env_archcpu(env); Nios2MMU *mmu = &env->mmu; - MMU_LOG(qemu_log("mmu_init\n")); - mmu->tlb_entry_mask = (cpu->tlb_num_entries / cpu->tlb_num_ways) - 1; mmu->tlb = g_new0(Nios2TLBEntry, cpu->tlb_num_entries); } diff --git a/target/nios2/trace-events b/target/nios2/trace-events new file mode 100644 index 0000000000..07f1f0a5e7 --- /dev/null +++ b/target/nios2/trace-events @@ -0,0 +1,10 @@ +# mmu.c +nios2_mmu_translate_miss(uint32_t vaddr, uint32_t pid, uint32_t index, uint32_t tag) "mmu_translate: MISS vaddr=0x%08x pid=%u TLB[%u] tag=0x%08x" +nios2_mmu_translate_hit(uint32_t vaddr, uint32_t pid, uint32_t index, uint32_t paddr, uint32_t prot) "mmu_translate: HIT vaddr=0x%08x pid=%u TLB[%u] paddr=0x%08x prot=0x%x" + +nios2_mmu_flush_pid_miss(uint32_t pid, uint32_t index, uint32_t vaddr) "mmu_flush: MISS pid=%u TLB[%u] tag=0x%08x" +nios2_mmu_flush_pid_hit(uint32_t pid, uint32_t index, uint32_t vaddr) "mmu_flush: HIT pid=%u TLB[%u] vaddr=0x%08x" + +nios2_mmu_write_tlbacc(uint32_t ig, char c, char r, char w, char x, char g, uint32_t pfn) "mmu_write_tlbacc: ig=0x%02x flags=%c%c%c%c%c pfn=0x%08x" +nios2_mmu_write_tlbmisc(uint32_t way, char r, char w, char t, char b, char p, char d, uint32_t pid) "mmu_write_tlbmisc: way=0x%x flags=%c%c%c%c%c%c pid=%u" +nios2_mmu_write_pteaddr(uint32_t ptb, uint32_t vpn) "mmu_write_pteaddr: ptbase=0x%03x vpn=0x%05x" From patchwork Thu Mar 3 20:46:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 547815 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp970181imq; Thu, 3 Mar 2022 12:51:27 -0800 (PST) X-Google-Smtp-Source: ABdhPJyw4HEH434bk+cyd0sjE5JzAvQAyCirRBzWeAxSxreCfwGH8u0EYByZBPie8ugxr4l89DV0 X-Received: by 2002:a81:6dd1:0:b0:2dc:56d1:1dae with SMTP id i200-20020a816dd1000000b002dc56d11daemr1611625ywc.479.1646340687477; Thu, 03 Mar 2022 12:51:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646340687; cv=none; d=google.com; s=arc-20160816; b=Zg6qRpOWDPgIFEBLDxdHmfYvmW+Bln62KHZRBiWk1hg4ry6jWOofGBpg+4DCls/zMG DNKB+z16EGsn2UuU30L7Mf+imEfrozeDjYTfVlLsfPcJ0NFICNnGfVXP8cBwHBQeRyI9 rCwArZ4hYgKioFORl21QTiFCVZKOKErcEvSWYBgqwiYGajty4xncDuTdULqdE2WQwSAN Fpzss6FIY/DmxdEv1K8YMAhIlkZqZECdrOghVTfutc6iEdoACDx83R5zcsczM0oaROGg TnHjyURWUySlbcYNg1m5I5lFs9AM7trec51ZIBskZ7ik1PeMmfIT1N8mohv/Gk7Vi7pI bP+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DgijVqHZRbMJcToV5HUeYKBRNb+4RK7lyL5hmphZYzc=; b=MSAjhGJchbN9C2p5Fk6iSTJLa/EqQ4inIBVCEvf0k70+vg8XMGz7yF+yQBKuwlFa0R AYaRV9FVqvJKvt5hxMBp0UB2TnoX0C/IqTE41YsmKEubzOHQ9Q5xYGvZsRBtPwk5LnAF ymDj5T1crTUFnRVmAT5CcZmJudCtUpkd9Q8GunSEJoRhwF29GRpEmJ2IsVORYgVLjCg/ cX05p8pv7r7oMDqF50MnnxcILQk3L/8aEBN2yAlpzdOPYOKrj2IrSmnJYDYGHVKWnCyJ W6G8aOb17b2PEZqXmXIWwE6/d7xkliBUHjBOLIOut+C3DvsQsYn0yWb3VgbNjfAkMG1h ZwuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JoFEt+d6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id d16-20020a17090ad99000b001bcbc4247a0sm2901211pjv.57.2022.03.03.12.46.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:46:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 3/7] target/nios2: Only build mmu.c for system mode Date: Thu, 3 Mar 2022 10:46:20 -1000 Message-Id: <20220303204624.468786-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303204624.468786-1-richard.henderson@linaro.org> References: <20220303204624.468786-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can thus remove an ifdef covering the entire file. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/nios2/mmu.c | 3 --- target/nios2/meson.build | 3 +-- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 306370f675..437fad09b7 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -25,7 +25,6 @@ #include "mmu.h" #include "trace/trace-target_nios2.h" -#if !defined(CONFIG_USER_ONLY) /* rw - 0 = read, 1 = write, 2 = fetch. */ unsigned int mmu_translate(CPUNios2State *env, @@ -217,5 +216,3 @@ void dump_mmu(CPUNios2State *env) (entry->data & CR_TLBACC_X) ? 'X' : '-'); } } - -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/meson.build b/target/nios2/meson.build index e643917db1..62b384702d 100644 --- a/target/nios2/meson.build +++ b/target/nios2/meson.build @@ -2,14 +2,13 @@ nios2_ss = ss.source_set() nios2_ss.add(files( 'cpu.c', 'helper.c', - 'mmu.c', 'nios2-semi.c', 'op_helper.c', 'translate.c', )) nios2_softmmu_ss = ss.source_set() -nios2_softmmu_ss.add(files('monitor.c')) +nios2_softmmu_ss.add(files('monitor.c', 'mmu.c')) target_arch += {'nios2': nios2_ss} target_softmmu_arch += {'nios2': nios2_softmmu_ss} From patchwork Thu Mar 3 20:46:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 547811 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp967780imq; Thu, 3 Mar 2022 12:47:29 -0800 (PST) X-Google-Smtp-Source: ABdhPJwZJNehpDhbK+6+IZSWEb+KPXfINpjP2e7esTbVoFXYwd3j/Cdd6er9Xme1ITauI2a0lXgE X-Received: by 2002:a25:d408:0:b0:628:bc90:57e5 with SMTP id m8-20020a25d408000000b00628bc9057e5mr5877063ybf.320.1646340449607; Thu, 03 Mar 2022 12:47:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646340449; cv=none; d=google.com; s=arc-20160816; b=mKOvWwHOaxjCcrMrvj9xUQQ1n9pSa1xwvQ3TR7MgNqDFjoghjW2TbJSHxU+OQrc/RV TjBmuNxg8AZVtpAJLqZgSyXaZcpxJm6e7vsp2SpSKs7u4c8g888t8afOhtQmas6vrrdg OnhrsAG195AU3ZCrRNisRqz1LFi10D1s61AE0L7dGCxwYXnmHDlt/I7pKVKVUADa0lrP NaARgmYSTyMjkWiMUIQL3i7sj0w4d+SPAevjVQzipuC5695Uw6xard3y97wAYgWMklnV IflCumJu8v3iLpWd4/srW93EeBMjiSRXs5O6rqaLJlheXExsG3ji6VFEPpYhQ7nbS7lW C4Hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=her8508EwA+z2+eb8zvRxH56IuxcXKjAk0c8gMcBkP8=; b=Td6MeP2FII7bUAVIfSIPFNabHZaAv7sv2Ny/iHbFfBTBzVWQtykdeB37s01aE6H79m JTBRib2aTeP/KLcVQhhTWtnzsD/EHBtohnd7+rvYaNndGnPJAcW51FDSvbH7vQO03EUg kKalQGGafesBXhjLGhIx6sfpuc9bpnHpcdD1WSs/2bAzudW0X/MZJX/Xr3WOERTEJGfg U+lr6NyOGqa+TpPicCk+QSizrjbFyL1Sro/oQGJ0A6tBfRG2ZR7x0AsSoGosLRdznziE +ZByazRG9GZXRFIlsuc9GlxaevLTSbfcoYgkXvwImjSLEA7kht+SzVm/Jl5p0Z+iEKlk ersQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZX0CxXI5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id d16-20020a17090ad99000b001bcbc4247a0sm2901211pjv.57.2022.03.03.12.46.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:46:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 4/7] target/nios2: Hoist R_ZERO check in rdctl Date: Thu, 3 Mar 2022 10:46:21 -1000 Message-Id: <20220303204624.468786-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303204624.468786-1-richard.henderson@linaro.org> References: <20220303204624.468786-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::431 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will avoid having to replicate the check to additional cases. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/nios2/translate.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 194c8ebafd..fa355308a9 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -447,11 +447,13 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) gen_check_supervisor(dc); + if (unlikely(instr.c == R_ZERO)) { + return; + } + switch (instr.imm5 + CR_BASE) { default: - if (likely(instr.c != R_ZERO)) { - tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]); - } + tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]); break; } } From patchwork Thu Mar 3 20:46:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 547816 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp970201imq; Thu, 3 Mar 2022 12:51:29 -0800 (PST) X-Google-Smtp-Source: ABdhPJzkDSpQW2b9adFj8pWgJPYooAqJqqWavAgDKYuLUE/sHSV0J6FC9wpVCmbRMe+JjtgeQPY9 X-Received: by 2002:a81:b89:0:b0:2db:c3d0:ae32 with SMTP id 131-20020a810b89000000b002dbc3d0ae32mr17663915ywl.436.1646340689673; Thu, 03 Mar 2022 12:51:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646340689; cv=none; d=google.com; s=arc-20160816; b=D/F8egYxkYD0THZGIgA05ykhF6X7jIb+wKNLeZ6xQsa+ntHUe2uoR1lf6MEmuwWIQb wkA+03bX4Igg311amPqh9q9xMOHmH55JIv+BpKCU5EU/qZ9//BWy3aDPX4E5F9ktcixA 0OZkljR71j7wGKMgx5HXCtmwcCO72O2CVMo9jvTjCGwYoroc8Zmrc1bJ6YZHxpldbE5m y6TO7B8SerRdZIwCAey0UYHsCO/shCdQSxPOV8K7b75gWpms58lcgIHvVEq3wZo4uuBR Jv5i9Jc/Qke770vMML8Q9OsY0lnUYMucSp+y6c6LkiOYuJQlGz3P1KKkmk9g7xsFsbWL 6qGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VYs8n9ySlRa4OB2uec0koEx8EcehzROHnTlgvRTS7Ns=; b=Kw6PvEXEJhGVap6Rk9VRGFY0uVitvc9s1ywKX4vVEpQZ72/qI/h0Pwf2I0hupUPXRE ESitwpLUBpt9G1z11KduPVxTwuJcExl0JcMh3Cce5d/vm8YjEPro48+uhJLjxHQyW7rd 4TABmvA2kVgxGj+Q4Td0uOJ5wGkONcfToc8p9/6MNHmyVVs/LX/A8fLNWbdPlklkLhWK hQ4c+sT7Jii67dbBX4QBN5Fiw4X0T3Csk9kMOAHOazmUoakgZTAeo5XF7QupvbhMHY18 K1D+Ay5cif+BYvWuqwltbw6zxymN6rI1v/1fgr+ehmEYM5M2cPQqAGTvrCuLKmLP6iKS CBmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uKGGJeYA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id d16-20020a17090ad99000b001bcbc4247a0sm2901211pjv.57.2022.03.03.12.46.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:46:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 5/7] target/nios2: Split mmu_write Date: Thu, 3 Mar 2022 10:46:22 -1000 Message-Id: <20220303204624.468786-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303204624.468786-1-richard.henderson@linaro.org> References: <20220303204624.468786-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::630 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create three separate functions for the three separate registers. Avoid extra dispatch through op_helper.c. Dispatch to the correct function in translation. Clean up the ifdefs in wrctl. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/helper.h | 4 +- target/nios2/mmu.c | 180 +++++++++++++++++++-------------------- target/nios2/op_helper.c | 5 -- target/nios2/translate.c | 26 +++--- 4 files changed, 104 insertions(+), 111 deletions(-) diff --git a/target/nios2/helper.h b/target/nios2/helper.h index 6d8eec1814..21ef7f0791 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -21,6 +21,8 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) #if !defined(CONFIG_USER_ONLY) -DEF_HELPER_3(mmu_write, void, env, i32, i32) +DEF_HELPER_2(mmu_write_tlbacc, void, env, i32) +DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32) +DEF_HELPER_2(mmu_write_pteaddr, void, env, i32) DEF_HELPER_1(check_interrupts, void, env) #endif diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 437fad09b7..4daab2a7ab 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "mmu.h" +#include "exec/helper-proto.h" #include "trace/trace-target_nios2.h" @@ -80,106 +81,103 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t pid) } } -void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) +void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) { CPUState *cs = env_cpu(env); Nios2CPU *cpu = env_archcpu(env); - switch (rn) { - case CR_TLBACC: - trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT, - (v & CR_TLBACC_C) ? 'C' : '.', - (v & CR_TLBACC_R) ? 'R' : '.', - (v & CR_TLBACC_W) ? 'W' : '.', - (v & CR_TLBACC_X) ? 'X' : '.', - (v & CR_TLBACC_G) ? 'G' : '.', - v & CR_TLBACC_PFN_MASK); + trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT, + (v & CR_TLBACC_C) ? 'C' : '.', + (v & CR_TLBACC_R) ? 'R' : '.', + (v & CR_TLBACC_W) ? 'W' : '.', + (v & CR_TLBACC_X) ? 'X' : '.', + (v & CR_TLBACC_G) ? 'G' : '.', + v & CR_TLBACC_PFN_MASK); - /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ - if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) { - int way = (env->regs[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); - int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; - int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; - int g = (v & CR_TLBACC_G) ? 1 : 0; - int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0; - Nios2TLBEntry *entry = - &env->mmu.tlb[(way * cpu->tlb_num_ways) + - (vpn & env->mmu.tlb_entry_mask)]; - uint32_t newTag = (vpn << 12) | (g << 11) | (valid << 10) | pid; - uint32_t newData = v & (CR_TLBACC_C | CR_TLBACC_R | CR_TLBACC_W | - CR_TLBACC_X | CR_TLBACC_PFN_MASK); + /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ + if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) { + int way = (env->regs[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); + int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; + int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; + int g = (v & CR_TLBACC_G) ? 1 : 0; + int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0; + Nios2TLBEntry *entry = + &env->mmu.tlb[(way * cpu->tlb_num_ways) + + (vpn & env->mmu.tlb_entry_mask)]; + uint32_t newTag = (vpn << 12) | (g << 11) | (valid << 10) | pid; + uint32_t newData = v & (CR_TLBACC_C | CR_TLBACC_R | CR_TLBACC_W | + CR_TLBACC_X | CR_TLBACC_PFN_MASK); - if ((entry->tag != newTag) || (entry->data != newData)) { - if (entry->tag & (1 << 10)) { - /* Flush existing entry */ - tlb_flush_page(cs, entry->tag & TARGET_PAGE_MASK); - } - entry->tag = newTag; - entry->data = newData; + if ((entry->tag != newTag) || (entry->data != newData)) { + if (entry->tag & (1 << 10)) { + /* Flush existing entry */ + tlb_flush_page(cs, entry->tag & TARGET_PAGE_MASK); } - /* Auto-increment tlbmisc.WAY */ - env->regs[CR_TLBMISC] = - (env->regs[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) | - (((way + 1) & (cpu->tlb_num_ways - 1)) << - CR_TLBMISC_WAY_SHIFT); + entry->tag = newTag; + entry->data = newData; } - - /* Writes to TLBACC don't change the read-back value */ - env->mmu.tlbacc_wr = v; - break; - - case CR_TLBMISC: - trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT, - (v & CR_TLBMISC_RD) ? 'R' : '.', - (v & CR_TLBMISC_WR) ? 'W' : '.', - (v & CR_TLBMISC_DBL) ? '2' : '.', - (v & CR_TLBMISC_BAD) ? 'B' : '.', - (v & CR_TLBMISC_PERM) ? 'P' : '.', - (v & CR_TLBMISC_D) ? 'D' : '.', - (v & CR_TLBMISC_PID_MASK) >> 4); - - if ((v & CR_TLBMISC_PID_MASK) != - (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) { - mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> - CR_TLBMISC_PID_SHIFT); - } - /* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */ - if (v & CR_TLBMISC_RD) { - int way = (v >> CR_TLBMISC_WAY_SHIFT); - int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; - Nios2TLBEntry *entry = - &env->mmu.tlb[(way * cpu->tlb_num_ways) + - (vpn & env->mmu.tlb_entry_mask)]; - - env->regs[CR_TLBACC] &= CR_TLBACC_IGN_MASK; - env->regs[CR_TLBACC] |= entry->data; - env->regs[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0; - env->regs[CR_TLBMISC] = - (v & ~CR_TLBMISC_PID_MASK) | - ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << - CR_TLBMISC_PID_SHIFT); - env->regs[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK; - env->regs[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT; - } else { - env->regs[CR_TLBMISC] = v; - } - - env->mmu.tlbmisc_wr = v; - break; - - case CR_PTEADDR: - trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT, - (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT); - - /* Writes to PTEADDR don't change the read-back VPN value */ - env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) | - (env->regs[CR_PTEADDR] & CR_PTEADDR_VPN_MASK); - env->mmu.pteaddr_wr = v; - break; - - default: - break; + /* Auto-increment tlbmisc.WAY */ + env->regs[CR_TLBMISC] = + (env->regs[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) | + (((way + 1) & (cpu->tlb_num_ways - 1)) << + CR_TLBMISC_WAY_SHIFT); } + + /* Writes to TLBACC don't change the read-back value */ + env->mmu.tlbacc_wr = v; +} + +void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) +{ + Nios2CPU *cpu = env_archcpu(env); + + trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT, + (v & CR_TLBMISC_RD) ? 'R' : '.', + (v & CR_TLBMISC_WR) ? 'W' : '.', + (v & CR_TLBMISC_DBL) ? '2' : '.', + (v & CR_TLBMISC_BAD) ? 'B' : '.', + (v & CR_TLBMISC_PERM) ? 'P' : '.', + (v & CR_TLBMISC_D) ? 'D' : '.', + (v & CR_TLBMISC_PID_MASK) >> 4); + + if ((v & CR_TLBMISC_PID_MASK) != + (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) { + mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> + CR_TLBMISC_PID_SHIFT); + } + /* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */ + if (v & CR_TLBMISC_RD) { + int way = (v >> CR_TLBMISC_WAY_SHIFT); + int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; + Nios2TLBEntry *entry = + &env->mmu.tlb[(way * cpu->tlb_num_ways) + + (vpn & env->mmu.tlb_entry_mask)]; + + env->regs[CR_TLBACC] &= CR_TLBACC_IGN_MASK; + env->regs[CR_TLBACC] |= entry->data; + env->regs[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0; + env->regs[CR_TLBMISC] = + (v & ~CR_TLBMISC_PID_MASK) | + ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << + CR_TLBMISC_PID_SHIFT); + env->regs[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK; + env->regs[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT; + } else { + env->regs[CR_TLBMISC] = v; + } + + env->mmu.tlbmisc_wr = v; +} + +void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v) +{ + trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT, + (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT); + + /* Writes to PTEADDR don't change the read-back VPN value */ + env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) | + (env->regs[CR_PTEADDR] & CR_PTEADDR_VPN_MASK); + env->mmu.pteaddr_wr = v; } void mmu_init(CPUNios2State *env) diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 61fc4dc903..d729379e4d 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -26,11 +26,6 @@ #include "qemu/main-loop.h" #if !defined(CONFIG_USER_ONLY) -void helper_mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) -{ - mmu_write(env, rn, v); -} - static void nios2_check_interrupts(CPUNios2State *env) { if (env->irq_pending && diff --git a/target/nios2/translate.c b/target/nios2/translate.c index fa355308a9..52965ba17e 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -461,30 +461,28 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) /* ctlN <- rA */ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) { - R_TYPE(instr, code); - gen_check_supervisor(dc); +#ifndef CONFIG_USER_ONLY + R_TYPE(instr, code); + TCGv v = load_gpr(dc, instr.a); + switch (instr.imm5 + CR_BASE) { case CR_PTEADDR: - case CR_TLBACC: - case CR_TLBMISC: - { -#if !defined(CONFIG_USER_ONLY) - TCGv_i32 tmp = tcg_const_i32(instr.imm5 + CR_BASE); - gen_helper_mmu_write(cpu_env, tmp, load_gpr(dc, instr.a)); - tcg_temp_free_i32(tmp); -#endif + gen_helper_mmu_write_pteaddr(cpu_env, v); + break; + case CR_TLBACC: + gen_helper_mmu_write_tlbacc(cpu_env, v); + break; + case CR_TLBMISC: + gen_helper_mmu_write_tlbmisc(cpu_env, v); break; - } - default: - tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], load_gpr(dc, instr.a)); + tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v); break; } /* If interrupts were enabled using WRCTL, trigger them. */ -#if !defined(CONFIG_USER_ONLY) if ((instr.imm5 + CR_BASE) == CR_STATUS) { if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_start(); From patchwork Thu Mar 3 20:46:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 547814 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp969158imq; Thu, 3 Mar 2022 12:49:42 -0800 (PST) X-Google-Smtp-Source: ABdhPJx0Oqi5g7gjB7iQXhZUf/KoudZSoGa++V3ofahKPGdbNEq4gjPMttWBKHkXfHp+fo5pTMzR X-Received: by 2002:a5b:689:0:b0:61d:9014:bbbe with SMTP id j9-20020a5b0689000000b0061d9014bbbemr34681804ybq.34.1646340582258; Thu, 03 Mar 2022 12:49:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646340582; cv=none; d=google.com; s=arc-20160816; b=j49/gQf0GUo6IB8QQhRAyIIQpIWNGoFWL/2/dty3EHElomY397D3+uf9S2Lmgq4VBZ Oy61Qsph9smypxXntrNIMAeL6DBieMD/d8Ngbi80ESUP0vPrWnLDt6ULILHBEd4gWvhL wGhpY/JoS59Mac/FilkKDO/04ZwR4qE4yoxH2hZ9scFSo4feCDMPSRtotE7xtE+rnGk7 RuI1ESUAtZsmiQ1OzNiUG8tLHM6YnEwriBsNaLtBXb78thaHmSHUcctWHG5JUsLJWf/L Od+CwtpR5/JNe0B0U3iQDi4hQMScmVhlWg5X6PnJ4qfCJzYuu1BfCybY/Akfxt+9GY3d zHZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ngdOSpEXdyoj/2hX4DgLlWUWJ0os8VUKvzBanI2gIUE=; b=n08BJTjD970AstgbwX1/yj0Sx+1c+S9VB7psr9PAU8B1LGxvFIOz8g/8FeI7BGKped +2mTx7FTdWZYIU04RD/vd0vfb50cH8ciR+4WS0iA/b1tZWS6odX8i6vkTBzfqcO+QHtq Z4Q0+ORkVFxgzAZKhSXZj/VL81qbqxJWsQxvSHORiMx1I6+GRUajneYpHL6ofcRXs0ER oGC6ATOMf5ouuptn8AuD2Z6f+lI+MLjaZkKdz+ELVb2auRCLoaGfC16fF198CTNC0eem +2MVqJ53hbLYicjjE62FZ91ImUUiGqfGTnQREAHnk47eh6hiT4bzip0BJaLvnNLOYgF6 7udg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RvUciXSh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id d16-20020a17090ad99000b001bcbc4247a0sm2901211pjv.57.2022.03.03.12.46.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:46:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 6/7] target/nios2: Special case ipending in rdctl and wrctl Date: Thu, 3 Mar 2022 10:46:23 -1000 Message-Id: <20220303204624.468786-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303204624.468786-1-richard.henderson@linaro.org> References: <20220303204624.468786-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1033 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It was never correct to be able to write to ipending. Until the rest of the irq code is tidied, the read of ipending will generate an "unnecessary" mask. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/nios2/translate.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 52965ba17e..a5f8d20729 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -452,6 +452,17 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) } switch (instr.imm5 + CR_BASE) { + case CR_IPENDING: + /* + * The value of the ipending register is synthetic. + * In hw, this is the AND of a set of hardware irq lines + * with the ienable register. In qemu, we re-use the space + * of CR_IPENDING to store the set of irq lines, and so we + * must perform the AND here, and anywhere else we need the + * guest value of ipending. + */ + tcg_gen_and_tl(cpu_R[instr.c], cpu_R[CR_IPENDING], cpu_R[CR_IENABLE]); + break; default: tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]); break; @@ -477,6 +488,9 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) case CR_TLBMISC: gen_helper_mmu_write_tlbmisc(cpu_env, v); break; + case CR_IPENDING: + /* ipending is read only, writes ignored. */ + break; default: tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v); break; From patchwork Thu Mar 3 20:46:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 547812 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp967837imq; Thu, 3 Mar 2022 12:47:34 -0800 (PST) X-Google-Smtp-Source: ABdhPJzeMOTEjD6wkplaYG4rPcNw8+0swIKKB2xIs0u3EFp5uG+KjEr5Bbj2S1MMt2IM+oN+Wngl X-Received: by 2002:a81:6f07:0:b0:2db:e18a:97c1 with SMTP id k7-20020a816f07000000b002dbe18a97c1mr13879950ywc.106.1646340454058; Thu, 03 Mar 2022 12:47:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646340454; cv=none; d=google.com; s=arc-20160816; b=m4OZkG4tXl+zJLLmhk1vk9nowwzz9xX3HLf2ukg8sRrk0I9EggQeqWdjaB9L66kfmd 8di0a+82MSb9sSLWtt3sRnKgfyTj7G5UvUCjZcO0qpYM9H6zDH7Ii0winVIlTqTpkh1t YQl2GVOemky2AgE5q3/UeSroEjMwunDlBhS6VxsYVf5XM30+3yhWkr/nNdvuAQ7I4B9S B4yO7eJ/xINCKduioq7tsQyI1h2kGl1THVw1dHntsoivmAMpwLvxVpCY80nfARsJuZtr +tKdIDiurMMCAlS2n0hEt5VFBUgtBh/HU3qJ/FlbgCMeLob53Ee5JElkU7QGI9x1tFbY 0YVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NZsEcN4dnDK5OBQ0/25VfSwi8UBjAELqG0R7yGR1FOg=; b=XJO/O7Mqm3O+sNZJpQfTmJ0YKaflRRljgkj6cj8674h79Eik3Kzyo0mQtF1a67ieNn 0MT0AUGqz0ogLVWNPpzDxIvqEvQFgpsTAQ4rQjOuTrFhao30v0lxPM0Ixu9Lai9++F1e RXnvdhMKUs5MYTMsDusYKXo8ozyBuKnEuXDxF64B6dvpgOs6ho28UzZnXXit47WII5NZ m2rkvkT9mSRgNNbf/qqzUAmXo3OPdjHhtb7sXCzRO0aLhcMID3dXroBNMyoUYseqLpgc MgEK5HrNhc4ERzVLa0sbMPa2qNiHSgEFLATUESKS0zzT9nac33Q3HcdRv+22XleCBO6A AI/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Py/0eh9/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id d16-20020a17090ad99000b001bcbc4247a0sm2901211pjv.57.2022.03.03.12.46.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:46:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 7/7] target/nios2: Rewrite interrupt handling Date: Thu, 3 Mar 2022 10:46:24 -1000 Message-Id: <20220303204624.468786-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303204624.468786-1-richard.henderson@linaro.org> References: <20220303204624.468786-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Previously, we would avoid setting CPU_INTERRUPT_HARD when interrupts are disabled at a particular point in time, instead queuing the value into cpu->irq_pending. This is more complicated than required. Instead, set CPU_INTERRUPT_HARD any time there is a pending interrupt, and exclusively check for interrupts disabled in nios2_cpu_exec_interrupt. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 1 - target/nios2/helper.h | 1 - target/nios2/cpu.c | 10 ++++------ target/nios2/op_helper.c | 19 ------------------- target/nios2/translate.c | 14 +++++--------- 5 files changed, 9 insertions(+), 36 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index d2ba0c5bbd..a00e4229ce 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -160,7 +160,6 @@ struct CPUNios2State { #if !defined(CONFIG_USER_ONLY) Nios2MMU mmu; - uint32_t irq_pending; #endif int error_code; }; diff --git a/target/nios2/helper.h b/target/nios2/helper.h index 21ef7f0791..a44ecfdf7a 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -24,5 +24,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) DEF_HELPER_2(mmu_write_tlbacc, void, env, i32) DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32) DEF_HELPER_2(mmu_write_pteaddr, void, env, i32) -DEF_HELPER_1(check_interrupts, void, env) #endif diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 4cade61e93..6975ae4bdb 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -73,12 +73,9 @@ static void nios2_cpu_set_irq(void *opaque, int irq, int level) env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level); - env->irq_pending = env->regs[CR_IPENDING] & env->regs[CR_IENABLE]; - - if (env->irq_pending && (env->regs[CR_STATUS] & CR_STATUS_PIE)) { - env->irq_pending = 0; + if (env->regs[CR_IPENDING]) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else if (!env->irq_pending) { + } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); } } @@ -134,7 +131,8 @@ static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) CPUNios2State *env = &cpu->env; if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->regs[CR_STATUS] & CR_STATUS_PIE)) { + (env->regs[CR_STATUS] & CR_STATUS_PIE) && + (env->regs[CR_IPENDING] & env->regs[CR_IENABLE])) { cs->exception_index = EXCP_IRQ; nios2_cpu_do_interrupt(cs); return true; diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index d729379e4d..caa885f7b4 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -21,28 +21,9 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "qemu/main-loop.h" -#if !defined(CONFIG_USER_ONLY) -static void nios2_check_interrupts(CPUNios2State *env) -{ - if (env->irq_pending && - (env->regs[CR_STATUS] & CR_STATUS_PIE)) { - env->irq_pending = 0; - cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD); - } -} - -void helper_check_interrupts(CPUNios2State *env) -{ - qemu_mutex_lock_iothread(); - nios2_check_interrupts(env); - qemu_mutex_unlock_iothread(); -} -#endif /* !CONFIG_USER_ONLY */ - void helper_raise_exception(CPUNios2State *env, uint32_t index) { CPUState *cs = env_cpu(env); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index a5f8d20729..f89271dbed 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -491,19 +491,15 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) case CR_IPENDING: /* ipending is read only, writes ignored. */ break; + case CR_STATUS: + case CR_IENABLE: + /* If interrupts were enabled using WRCTL, trigger them. */ + dc->base.is_jmp = DISAS_UPDATE; + /* fall through */ default: tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v); break; } - - /* If interrupts were enabled using WRCTL, trigger them. */ - if ((instr.imm5 + CR_BASE) == CR_STATUS) { - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_check_interrupts(cpu_env); - dc->base.is_jmp = DISAS_UPDATE; - } #endif }