From patchwork Thu Mar 3 20:23:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547806 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp954506imq; Thu, 3 Mar 2022 12:26:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJxmh5SlHmnYc2B7SRQsX0U7zlkB6udRtp3qRI71xlwY0rf0N1zBd+tQLCrtl40L/4G0IJF7 X-Received: by 2002:a5b:f10:0:b0:628:8420:d694 with SMTP id x16-20020a5b0f10000000b006288420d694mr12834350ybr.483.1646339216765; Thu, 03 Mar 2022 12:26:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646339216; cv=none; d=google.com; s=arc-20160816; b=ishtKjlXCBgPfv6bGjlmxPfknujDPk1PHjCNbfTFabwjpszca5B0XgzEcNKjzwsPth kArezzcm0uuvbf6ObZDVRfLm7AIVEEX8WcjyUJtrnFO6WQtqbRknINzQ5CFCfty+4aZR syIbcSmmGJUa0TMAI9Ipg2wa/wZKTiexZv6nz1Eg1vDSNvN0Is8pLF7cINSofsnEjNRp I0jjP3ZI+IrtsHKHW+jepBH5G2/LPgDEHZo9uteGkEWhcttD+mlocfMSC3auRK9TOtPc qUOI/9kAB933lskkMn/niTU2nZlR2P4UVBH1KQnmJIs+CEm6mQzTTqgeWI0lCw8rRn6A niBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=29b8lo8/2aDtc19BPdL0SPSbYLySMtmUOuWMoFbG/ns=; b=ja/kH+QqnLWaAfqU8R/aKhW31VyPMN+6v9TZRhl4nqHJ5Uz8U7EeHe97Be2ricrIg8 bCXu995ssW2Ef6RulQFrA5Zt7XX0zzXWN5NJb1U7iGlVZCClF+4vbjpQ33QBEZ/wZvr2 qpdEElCA+MCkidOZGKd4Aj/vBvSPgVIhGHvZGDA3mHGgo86NDPGqtsB7DVRUnzUFupNg EMcoBTgW2rY3oe5Lc7ZNnpS+dDrJ9JS5d2eyS4x7SjmeSnwdxfFtKI/Qv2zlWjetcHfn Kux2DjxuWMJLwIIEHZHowkKw5nfq4DybmGt/y4hWC1E6weUw79HTCERiHCS12C+Gi4do 28CQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FvZhtGVe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s15-20020a25b94f000000b00628920b26c5si2408688ybm.596.2022.03.03.12.26.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Mar 2022 12:26:56 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FvZhtGVe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPs2K-0006rt-8D for patch@linaro.org; Thu, 03 Mar 2022 15:26:56 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49264) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPrzK-0001us-J8 for qemu-devel@nongnu.org; Thu, 03 Mar 2022 15:23:50 -0500 Received: from [2a00:1450:4864:20::434] (port=40663 helo=mail-wr1-x434.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nPrzH-0001ZQ-08 for qemu-devel@nongnu.org; Thu, 03 Mar 2022 15:23:49 -0500 Received: by mail-wr1-x434.google.com with SMTP id k24so89347wrd.7 for ; Thu, 03 Mar 2022 12:23:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=29b8lo8/2aDtc19BPdL0SPSbYLySMtmUOuWMoFbG/ns=; b=FvZhtGVer27dTJubJdUK4af2xjGTJfVuowUcpZS94HUS1nV8nO7QN1+HaS+qKU6FA+ ArCinFc1JY/PHXoXmEyvahtirOr6ZP2W0THT63dt3DGSL16iZps2aKzBpC8xpbeP2Alu kpO8jfcFHfmfIuI5yVE23AsfyMm4DgPrQe6bmnenEQi03euZJYebXkEdXbQjOQ5Rs447 oflJH+WeHusjde9I0JKq8AQyN19b5jLZQ2nEFg9xaLjdCyBBogjH2Q8t8SlNQY/9PX8h r5AjNN5D8jiOk/aBr9eGi/ttnDeFrmvBIGBJeo/5x+3kmPdWrVTRsCwBReUnwvN5C38K wioQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=29b8lo8/2aDtc19BPdL0SPSbYLySMtmUOuWMoFbG/ns=; b=AVCpR4Gbcp/aqwfDa/sZVDUKoxdqTZ2KiBi8J5t1dkPBycIp5paEHVVFvkiVqMMUf0 kRLntA2f74swj5/I0JjngOjrZCaH3P9/4ZYqbCL6NuppAJVS4MsfksxPDYVXbnoMWET8 viWaYLG9dg/O6m6rTxNJy/06KD25o4YTdPsRbQm4hzUDWHy4ywQEUA6BntTQW7jzKPGx oNSPnuYESThQQdlBI3ZbBLAHf1NDrNCEaZDRkmIDYnNTJt7H1qK1mvAaY9bJcJhzxSQB jgZIJ/4OtnuhFKn6jM25YKtCYVSdEILvywi4GdiPnAnwiTmmge1Sr04dvLFv3QX7YC0o 3tbg== X-Gm-Message-State: AOAM530BOiJfwM96bsUTEqPy3BRmtgMQHrgBQvcwXxuwOETpUQAfRTXs kbJmcMoEJW8IH9rs8pYjcsw6DQ== X-Received: by 2002:a5d:648d:0:b0:1ef:d62a:8414 with SMTP id o13-20020a5d648d000000b001efd62a8414mr15184822wri.99.1646339025232; Thu, 03 Mar 2022 12:23:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t5-20020adff045000000b001f0684c3404sm517060wro.11.2022.03.03.12.23.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:23:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/5] hw/intc/arm_gicv3_its: Add trace events for commands Date: Thu, 3 Mar 2022 20:23:37 +0000 Message-Id: <20220303202341.2232284-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303202341.2232284-1-peter.maydell@linaro.org> References: <20220303202341.2232284-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::434 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When debugging code that's using the ITS, it's helpful to see tracing of the ITS commands that the guest executes. Add suitable trace events. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_its.c | 28 ++++++++++++++++++++++++++-- hw/intc/trace-events | 12 ++++++++++++ 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 4f598d3c14f..77dc702734b 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -366,6 +366,19 @@ static ItsCmdResult process_its_cmd(GICv3ITSState *s, const uint64_t *cmdpkt, devid = (cmdpkt[0] & DEVID_MASK) >> DEVID_SHIFT; eventid = cmdpkt[1] & EVENTID_MASK; + switch (cmd) { + case INTERRUPT: + trace_gicv3_its_cmd_int(devid, eventid); + break; + case CLEAR: + trace_gicv3_its_cmd_clear(devid, eventid); + break; + case DISCARD: + trace_gicv3_its_cmd_discard(devid, eventid); + break; + default: + g_assert_not_reached(); + } return do_process_its_cmd(s, devid, eventid, cmd); } @@ -382,15 +395,16 @@ static ItsCmdResult process_mapti(GICv3ITSState *s, const uint64_t *cmdpkt, devid = (cmdpkt[0] & DEVID_MASK) >> DEVID_SHIFT; eventid = cmdpkt[1] & EVENTID_MASK; + icid = cmdpkt[2] & ICID_MASK; if (ignore_pInt) { pIntid = eventid; + trace_gicv3_its_cmd_mapi(devid, eventid, icid); } else { pIntid = (cmdpkt[1] & pINTID_MASK) >> pINTID_SHIFT; + trace_gicv3_its_cmd_mapti(devid, eventid, icid, pIntid); } - icid = cmdpkt[2] & ICID_MASK; - if (devid >= s->dt.num_entries) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid command attributes: devid %d>=%d", @@ -484,6 +498,7 @@ static ItsCmdResult process_mapc(GICv3ITSState *s, const uint64_t *cmdpkt) } else { cte.rdbase = 0; } + trace_gicv3_its_cmd_mapc(icid, cte.rdbase, cte.valid); if (icid >= s->ct.num_entries) { qemu_log_mask(LOG_GUEST_ERROR, "ITS MAPC: invalid ICID 0x%d", icid); @@ -539,6 +554,8 @@ static ItsCmdResult process_mapd(GICv3ITSState *s, const uint64_t *cmdpkt) dte.ittaddr = (cmdpkt[2] & ITTADDR_MASK) >> ITTADDR_SHIFT; dte.valid = cmdpkt[2] & CMD_FIELD_VALID_MASK; + trace_gicv3_its_cmd_mapd(devid, dte.size, dte.ittaddr, dte.valid); + if (devid >= s->dt.num_entries) { qemu_log_mask(LOG_GUEST_ERROR, "ITS MAPD: invalid device ID field 0x%x >= 0x%x\n", @@ -562,6 +579,8 @@ static ItsCmdResult process_movall(GICv3ITSState *s, const uint64_t *cmdpkt) rd1 = FIELD_EX64(cmdpkt[2], MOVALL_2, RDBASE1); rd2 = FIELD_EX64(cmdpkt[3], MOVALL_3, RDBASE2); + trace_gicv3_its_cmd_movall(rd1, rd2); + if (rd1 >= s->gicv3->num_cpu) { qemu_log_mask(LOG_GUEST_ERROR, "%s: RDBASE1 %" PRId64 @@ -601,6 +620,8 @@ static ItsCmdResult process_movi(GICv3ITSState *s, const uint64_t *cmdpkt) eventid = FIELD_EX64(cmdpkt[1], MOVI_1, EVENTID); new_icid = FIELD_EX64(cmdpkt[2], MOVI_2, ICID); + trace_gicv3_its_cmd_movi(devid, eventid, new_icid); + if (devid >= s->dt.num_entries) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid command attributes: devid %d>=%d", @@ -779,6 +800,7 @@ static void process_cmdq(GICv3ITSState *s) * is already consistent by the time SYNC command is executed. * Hence no further processing is required for SYNC command. */ + trace_gicv3_its_cmd_sync(); break; case GITS_CMD_MAPD: result = process_mapd(s, cmdpkt); @@ -803,6 +825,7 @@ static void process_cmdq(GICv3ITSState *s) * need to trigger lpi priority re-calculation to be in * sync with LPI config table or pending table changes. */ + trace_gicv3_its_cmd_inv(); for (i = 0; i < s->gicv3->num_cpu; i++) { gicv3_redist_update_lpi(&s->gicv3->cpu[i]); } @@ -814,6 +837,7 @@ static void process_cmdq(GICv3ITSState *s) result = process_movall(s, cmdpkt); break; default: + trace_gicv3_its_cmd_unknown(cmd); break; } if (result == CMD_CONTINUE) { diff --git a/hw/intc/trace-events b/hw/intc/trace-events index b28cda4e08e..e92662b405c 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -176,6 +176,18 @@ gicv3_its_write(uint64_t offset, uint64_t data, unsigned size) "GICv3 ITS write: gicv3_its_badwrite(uint64_t offset, uint64_t data, unsigned size) "GICv3 ITS write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u: error" gicv3_its_translation_write(uint64_t offset, uint64_t data, unsigned size, uint32_t requester_id) "GICv3 ITS TRANSLATER write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u requester_id 0x%x" gicv3_its_process_command(uint32_t rd_offset, uint8_t cmd) "GICv3 ITS: processing command at offset 0x%x: 0x%x" +gicv3_its_cmd_int(uint32_t devid, uint32_t eventid) "GICv3 ITS: command INT DeviceID 0x%x EventID 0x%x" +gicv3_its_cmd_clear(uint32_t devid, uint32_t eventid) "GICv3 ITS: command CLEAR DeviceID 0x%x EventID 0x%x" +gicv3_its_cmd_discard(uint32_t devid, uint32_t eventid) "GICv3 ITS: command DISCARD DeviceID 0x%x EventID 0x%x" +gicv3_its_cmd_sync(void) "GICv3 ITS: command SYNC" +gicv3_its_cmd_mapd(uint32_t devid, uint32_t size, uint64_t ittaddr, int valid) "GICv3 ITS: command MAPD DeviceID 0x%x Size 0x%x ITT_addr 0x%" PRIx64 " V %d" +gicv3_its_cmd_mapc(uint32_t icid, uint64_t rdbase, int valid) "GICv3 ITS: command MAPC ICID 0x%x RDbase 0x%" PRIx64 " V %d" +gicv3_its_cmd_mapi(uint32_t devid, uint32_t eventid, uint32_t icid) "GICv3 ITS: command MAPI DeviceID 0x%x EventID 0x%x ICID 0x%x" +gicv3_its_cmd_mapti(uint32_t devid, uint32_t eventid, uint32_t icid, uint32_t intid) "GICv3 ITS: command MAPTI DeviceID 0x%x EventID 0x%x ICID 0x%x pINTID 0x%x" +gicv3_its_cmd_inv(void) "GICv3 ITS: command INV or INVALL" +gicv3_its_cmd_movall(uint64_t rd1, uint64_t rd2) "GICv3 ITS: command MOVALL RDbase1 0x%" PRIx64 " RDbase2 0x%" PRIx64 +gicv3_its_cmd_movi(uint32_t devid, uint32_t eventid, uint32_t icid) "GICv3 ITS: command MOVI DeviceID 0x%x EventID 0x%x ICID 0x%x" +gicv3_its_cmd_unknown(unsigned cmd) "GICv3 ITS: unknown command 0x%x" # armv7m_nvic.c nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d" From patchwork Thu Mar 3 20:23:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547805 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp953201imq; Thu, 3 Mar 2022 12:25:10 -0800 (PST) X-Google-Smtp-Source: ABdhPJwWfEAqgzkXfGwZFBEenZTUH6ghaS+cqBL8JjsPe3dSKiPtG70HrFu9mLyR2+31OAcmzcU2 X-Received: by 2002:a25:86c5:0:b0:628:a0f0:dea with SMTP id y5-20020a2586c5000000b00628a0f00deamr8628917ybm.88.1646339110280; Thu, 03 Mar 2022 12:25:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646339110; cv=none; d=google.com; s=arc-20160816; b=I4/nJLsscWsDi6JBRrNE0viFeYXTLZKKUBZ7X3ga6iLHm670k+/gXOlwzw2QCIV4xw OkaAutDxUMNpurL3a/Rjo0qFfA4odohVJWx4VIftkpypk+OjtSeZ5Ny4kADC+aRVw5Gs OMML4Ej9cQDWAn955p3LtxMf31pPja4NsohszHgxJHa47XE1rq0VcOa+xZlCDEzPdx0J dpmrGMHXbhv/gavAMNkDVprPjcxmVx5+BibZ4rBX5hZTuJRSwG2DK8GYs3CF4i6kHFih Aqi2vJQonlRplEIKp/n+j3rGSEAjx9kzDSIj+ix9WevqnhIi0k5HKuDBQIL8UMjhGfi4 2oMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cuehPBnSig6Jq64CPU+VvGsY4ITWKqf7FpYjraZi08c=; b=pabCJXRm2mtL9mdErQPwAJKLrrDwepsx7NEwohkkN/sZuxGZFk0IwbxC/3yX+1X4Qq H2MhtAstdZpkYb9Yo+NNEulXkIQBfu2WvM/MEVFYF0Rxk4oZjGj6ddO3nYKMbze70TE5 N5w2Lji4RTzHiALE9RMyBqaFF/5He+AkowOR/QSZoLcStJ1j/nS0t44woL1fsS+evxDb lKr8r5YnVIcZRhDqTi/qnCIW1kSK45bf+cpwu92sdpfSoXPXdxa63eJvXmVOdpd8Wjgw ciZtd7KIL+cLnl5OYwVx17WKBUi/HFXRnTQXHtpGdKYTTHpL1HnR2O8z4qUZ6PWOWpH6 P2PQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lh2DXkHp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i134-20020a253b8c000000b006242ade2a3fsi2440420yba.500.2022.03.03.12.25.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Mar 2022 12:25:10 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lh2DXkHp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPs0b-000390-PG for patch@linaro.org; Thu, 03 Mar 2022 15:25:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49256) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPrzK-0001uo-IA for qemu-devel@nongnu.org; Thu, 03 Mar 2022 15:23:50 -0500 Received: from [2a00:1450:4864:20::436] (port=40665 helo=mail-wr1-x436.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nPrzH-0001Ze-Dj for qemu-devel@nongnu.org; Thu, 03 Mar 2022 15:23:49 -0500 Received: by mail-wr1-x436.google.com with SMTP id k24so89370wrd.7 for ; Thu, 03 Mar 2022 12:23:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cuehPBnSig6Jq64CPU+VvGsY4ITWKqf7FpYjraZi08c=; b=lh2DXkHpu6gA7JtD0EIV9dIIJ5LkgmiGkyMK+H1hF33HZpC+Z0TgjMe7lDUijwCjiW rqjh2K/6f4DC/jYVS+dXQvXtdhQiPYELPmqEV5U40b+lwhCU6MJUG5ndq2+S2k/EXbAp qEgfuWJr9PFMwygugz65LxWJgEaGqG3rpoDB5L2XsHeYwQf3PqVW4tfmDYKqDr/+/YJp JS96ZM/Ho9HXowBrQxzpa3cNb3JVV0kyvc6o9rWUdO5qgnOF34jD2qkCzEqkaPuEFw6x rHv9NY0ovvYhcJL4qPR8yO0vW/idiKXJzYNwWAizO5P0Kvj2hpbf8fTTTg9sykD9dyeb tuyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cuehPBnSig6Jq64CPU+VvGsY4ITWKqf7FpYjraZi08c=; b=B2RGmdursagLNYpJAylSGsZzl+XPVYe7wefFOCeC8VodB0T/Wc3ybA/UQkSqNrkOIE oV22Tlh6esIMBtYCVA4Z96rHp7eVT8pmfFg9olPmhe+UFDQiEuJ77uBQbrjZTZrXr9oH g+Xmr52brgOaYKpEySC35M7Ek4Tt8EgZfoyu4iO68rObuEK3lV4WB20jhLI6Ux7bYU/d 1K5RXZum8cpAS3wPiVvKchSVUD3lAGuu4hjuDu5pGd8zgMPG2UuOUjTVcw/0hgC++SlO K8M1mEKImJU6ii9qTXjTZR/NSly7IseAp0F9ZYQ+JOQgNEfb8mdzsfCTFOLlH/otwlK9 YCHQ== X-Gm-Message-State: AOAM532VKj3zmvTyyhrghNp5xtxwgsA+Lvuq/Bhr1tCnl48O8BqUxnty /O3FRxDuy94Q7v5pdmGsPCVwaA== X-Received: by 2002:adf:d089:0:b0:1ed:9e86:2144 with SMTP id y9-20020adfd089000000b001ed9e862144mr27167687wrh.363.1646339026067; Thu, 03 Mar 2022 12:23:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t5-20020adff045000000b001f0684c3404sm517060wro.11.2022.03.03.12.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:23:45 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/5] hw/intc/arm_gicv3_its: Add trace events for table reads and writes Date: Thu, 3 Mar 2022 20:23:38 +0000 Message-Id: <20220303202341.2232284-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303202341.2232284-1-peter.maydell@linaro.org> References: <20220303202341.2232284-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::436 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For debugging guest use of the ITS, it can be helpful to trace when the ITS reads and writes the in-memory tables. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_its.c | 37 +++++++++++++++++++++++++++++++------ hw/intc/trace-events | 9 +++++++++ 2 files changed, 40 insertions(+), 6 deletions(-) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 77dc702734b..9f4df6a8cbb 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -161,16 +161,22 @@ static MemTxResult get_cte(GICv3ITSState *s, uint16_t icid, CTEntry *cte) if (entry_addr == -1) { /* No L2 table entry, i.e. no valid CTE, or a memory error */ cte->valid = false; - return res; + goto out; } cteval = address_space_ldq_le(as, entry_addr, MEMTXATTRS_UNSPECIFIED, &res); if (res != MEMTX_OK) { - return res; + goto out; } cte->valid = FIELD_EX64(cteval, CTE, VALID); cte->rdbase = FIELD_EX64(cteval, CTE, RDBASE); - return MEMTX_OK; +out: + if (res != MEMTX_OK) { + trace_gicv3_its_cte_read_fault(icid); + } else { + trace_gicv3_its_cte_read(icid, cte->valid, cte->rdbase); + } + return res; } /* @@ -187,6 +193,10 @@ static bool update_ite(GICv3ITSState *s, uint32_t eventid, const DTEntry *dte, uint64_t itel = 0; uint32_t iteh = 0; + trace_gicv3_its_ite_write(dte->ittaddr, eventid, ite->valid, + ite->inttype, ite->intid, ite->icid, + ite->vpeid, ite->doorbell); + if (ite->valid) { itel = FIELD_DP64(itel, ITE_L, VALID, 1); itel = FIELD_DP64(itel, ITE_L, INTTYPE, ite->inttype); @@ -221,11 +231,13 @@ static MemTxResult get_ite(GICv3ITSState *s, uint32_t eventid, itel = address_space_ldq_le(as, iteaddr, MEMTXATTRS_UNSPECIFIED, &res); if (res != MEMTX_OK) { + trace_gicv3_its_ite_read_fault(dte->ittaddr, eventid); return res; } iteh = address_space_ldl_le(as, iteaddr + 8, MEMTXATTRS_UNSPECIFIED, &res); if (res != MEMTX_OK) { + trace_gicv3_its_ite_read_fault(dte->ittaddr, eventid); return res; } @@ -235,6 +247,9 @@ static MemTxResult get_ite(GICv3ITSState *s, uint32_t eventid, ite->icid = FIELD_EX64(itel, ITE_L, ICID); ite->vpeid = FIELD_EX64(itel, ITE_L, VPEID); ite->doorbell = FIELD_EX64(iteh, ITE_H, DOORBELL); + trace_gicv3_its_ite_read(dte->ittaddr, eventid, ite->valid, + ite->inttype, ite->intid, ite->icid, + ite->vpeid, ite->doorbell); return MEMTX_OK; } @@ -254,17 +269,23 @@ static MemTxResult get_dte(GICv3ITSState *s, uint32_t devid, DTEntry *dte) if (entry_addr == -1) { /* No L2 table entry, i.e. no valid DTE, or a memory error */ dte->valid = false; - return res; + goto out; } dteval = address_space_ldq_le(as, entry_addr, MEMTXATTRS_UNSPECIFIED, &res); if (res != MEMTX_OK) { - return res; + goto out; } dte->valid = FIELD_EX64(dteval, DTE, VALID); dte->size = FIELD_EX64(dteval, DTE, SIZE); /* DTE word field stores bits [51:8] of the ITT address */ dte->ittaddr = FIELD_EX64(dteval, DTE, ITTADDR) << ITTADDR_SHIFT; - return MEMTX_OK; +out: + if (res != MEMTX_OK) { + trace_gicv3_its_dte_read_fault(devid); + } else { + trace_gicv3_its_dte_read(devid, dte->valid, dte->size, dte->ittaddr); + } + return res; } /* @@ -465,6 +486,8 @@ static bool update_cte(GICv3ITSState *s, uint16_t icid, const CTEntry *cte) uint64_t cteval = 0; MemTxResult res = MEMTX_OK; + trace_gicv3_its_cte_write(icid, cte->valid, cte->rdbase); + if (cte->valid) { /* add mapping entry to collection table */ cteval = FIELD_DP64(cteval, CTE, VALID, 1); @@ -524,6 +547,8 @@ static bool update_dte(GICv3ITSState *s, uint32_t devid, const DTEntry *dte) uint64_t dteval = 0; MemTxResult res = MEMTX_OK; + trace_gicv3_its_dte_write(devid, dte->valid, dte->size, dte->ittaddr); + if (dte->valid) { /* add mapping entry to device table */ dteval = FIELD_DP64(dteval, DTE, VALID, 1); diff --git a/hw/intc/trace-events b/hw/intc/trace-events index e92662b405c..53414aa1979 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -188,6 +188,15 @@ gicv3_its_cmd_inv(void) "GICv3 ITS: command INV or INVALL" gicv3_its_cmd_movall(uint64_t rd1, uint64_t rd2) "GICv3 ITS: command MOVALL RDbase1 0x%" PRIx64 " RDbase2 0x%" PRIx64 gicv3_its_cmd_movi(uint32_t devid, uint32_t eventid, uint32_t icid) "GICv3 ITS: command MOVI DeviceID 0x%x EventID 0x%x ICID 0x%x" gicv3_its_cmd_unknown(unsigned cmd) "GICv3 ITS: unknown command 0x%x" +gicv3_its_cte_read(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table read for ICID 0x%x: valid %d RDBase 0x%x" +gicv3_its_cte_write(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table write for ICID 0x%x: valid %d RDBase 0x%x" +gicv3_its_cte_read_fault(uint32_t icid) "GICv3 ITS: Collection Table read for ICID 0x%x: faulted" +gicv3_its_ite_read(uint64_t ittaddr, uint32_t eventid, int valid, int inttype, uint32_t intid, uint32_t icid, uint32_t vpeid, uint32_t doorbell) "GICv3 ITS: Interrupt Table read for ITTaddr 0x%" PRIx64 " EventID 0x%x: valid %d inttype %d intid 0x%x ICID 0x%x vPEID 0x%x doorbell 0x%x" +gicv3_its_ite_read_fault(uint64_t ittaddr, uint32_t eventid) "GICv3 ITS: Interrupt Table read for ITTaddr 0x%" PRIx64 " EventID 0x%x: faulted" +gicv3_its_ite_write(uint64_t ittaddr, uint32_t eventid, int valid, int inttype, uint32_t intid, uint32_t icid, uint32_t vpeid, uint32_t doorbell) "GICv3 ITS: Interrupt Table write for ITTaddr 0x%" PRIx64 " EventID 0x%x: valid %d inttype %d intid 0x%x ICID 0x%x vPEID 0x%x doorbell 0x%x" +gicv3_its_dte_read(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr) "GICv3 ITS: Device Table read for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64 +gicv3_its_dte_write(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr) "GICv3 ITS: Device Table write for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64 +gicv3_its_dte_read_fault(uint32_t devid) "GICv3 ITS: Device Table read for DeviceID 0x%x: faulted" # armv7m_nvic.c nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d" From patchwork Thu Mar 3 20:23:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547804 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp953187imq; Thu, 3 Mar 2022 12:25:09 -0800 (PST) X-Google-Smtp-Source: ABdhPJyeEp6pDqIP6ac25HP0AqbEi1ceq6TXstnoTSMaea+G/FBXu8ID52MSkapaDZOfIHmUqoc6 X-Received: by 2002:a81:f57:0:b0:2d2:abf6:489c with SMTP id 84-20020a810f57000000b002d2abf6489cmr37796898ywp.232.1646339109515; Thu, 03 Mar 2022 12:25:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646339109; cv=none; d=google.com; s=arc-20160816; b=eZhmIQb44kRYbHxnU9kelmLNOFXnM4SJgmk3nO9LSq1z6/aMJTvmRfX3WW/BgtF8zP kHsbwgOhf+Nt7lVv09LfDnNWqvkeYOCru/ONGEfF27PiS4V1rSvkd5HO/TcM6efgOZ/T E7nlVOuu9nf3EN4+l1aUj739mNHqCi9WyfEDTsDz10ZRMpN9h4JoX79tkUZCCBsBap1e CrjCdlHoQHLrhnvYCtlL9p1EntY1rfhk/TPRX/e7DRUkyaBFhD35nFyTyHEQFroJkQUj W4jyLS5e/L1PjHZyMiZNeALiOtRmCFzEY2DXBfUkYldF0EqEDxyL75kqE6jOeM9fcJle rRFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BwQur4NZBGGWfHrVPMLWwKCyDvLwx3c9PUY0EKxgx9k=; b=L8t9JkskZIUU+w57nzbbqT25soCkdicUdCdfd1ZqFqCF0ccQeHnRZthi0UQYsJBbNM WEv6SMu+uKyRFHnAAQ0GLJzVMRzDlS1FTA5l7OpySBgrmcEoUh1O5Y9FWrrj/IsKG90O cIt7vRx7fangAdrU7egmo33S3P1K6PJg8+IVoKay2Qa/p57HoLsZ8SAp4x+gq18vngfC jRz0zezlLbhUMRux6uD4trUDQV6mVNaVzDEOvm4UcqIAHAGoaz8ptpPpREKGzdqklRFL /J3uK+m8PFN47YoJ5KzrAJc/+6j8RM5P2WHl9EL3VxOK5qjb5aN0JFhUBqNmx6kndEt4 P//g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dnTyXeu1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j21-20020a252315000000b006288cd863b5si2414355ybj.490.2022.03.03.12.25.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Mar 2022 12:25:09 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dnTyXeu1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34068 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPs0b-0002y2-1a for patch@linaro.org; Thu, 03 Mar 2022 15:25:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPrzK-0001ut-Qn for qemu-devel@nongnu.org; Thu, 03 Mar 2022 15:23:50 -0500 Received: from [2a00:1450:4864:20::32e] (port=53868 helo=mail-wm1-x32e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nPrzI-0001Zz-Gt for qemu-devel@nongnu.org; Thu, 03 Mar 2022 15:23:50 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 19so3574938wmy.3 for ; Thu, 03 Mar 2022 12:23:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BwQur4NZBGGWfHrVPMLWwKCyDvLwx3c9PUY0EKxgx9k=; b=dnTyXeu1Yaiit8GnHMv0BTLnhMuUWGKjNnwyZ6lmKiSXTrd+TuVV72sNBvqSS0Ag2A FpRdeJ8+7KgV5TH1M+5jE3/WhiWhRkN6Z0eS5SMiq7U7HC6uI7qA0Tnia6vZjdYYD/ug m2o+ls1iCbirTUg2um/VeaHHHRsySaA0pjQLLgXpWLtO/lAYbHKpq1dbt9hi1mtHSXRW vwm2Xy32mAsNEY92jj66Op34Ml06WTblylElZNSXPYGwQ8q8Rkom21gNc30fTkt/sdBV QKViKUiamVLpiHg5ViTa3hY7QYuTho/Esctg/cDBGPZBYu4FdDK4FwEFV/QjApQw4n1c RERw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BwQur4NZBGGWfHrVPMLWwKCyDvLwx3c9PUY0EKxgx9k=; b=MMbYm85Jp5FMKtGKLxsg+1naAPtxcyt7k476+mkyx3MQeQ2+pYGHA+uHmKf5af7OPD 5mh4PgrAneBmpPZI6orqEm2FR5/UDxzyUWvP3qaa6lmNzFXDNsgoyRdRJMRzc624qfsY 9exoPoNL2mmZo0Tx+iFMd2i2vZQvQ1yj+y4Tx4XALGhT77X2Mi07g/tO/gc7fRYosJvC lpsP/bcx/Ca9jxzTPpTYFubbmFpstzUrpBZdadMbYfEtxAe79afybJzoULMWPn3YUJN1 H3mIfxqJKi/rBRxtwZ8VIGM9nztFcX/8NJJrmLNxrnCgJmjnn5+a9X93wiylWJKgBa4z YqHQ== X-Gm-Message-State: AOAM533Vrx8SfFAznoTblvpX60S77EGAugPZP6cQP/j4eh8eQ3IUJ5zd GWkk+0IQ5sbw9s7Cd9BOXxYTyA== X-Received: by 2002:a05:600c:3d0b:b0:382:aa17:8f16 with SMTP id bh11-20020a05600c3d0b00b00382aa178f16mr5025218wmb.82.1646339027128; Thu, 03 Mar 2022 12:23:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t5-20020adff045000000b001f0684c3404sm517060wro.11.2022.03.03.12.23.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:23:46 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/5] hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps Date: Thu, 3 Mar 2022 20:23:39 +0000 Message-Id: <20220303202341.2232284-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303202341.2232284-1-peter.maydell@linaro.org> References: <20220303202341.2232284-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The GICv3 has some registers that support byte accesses, and some that support 8-byte accesses. Our TCG implementation implements all of this, switching on the 'size' argument and handling the registers that must support reads of that size while logging an error for attempted accesses to registers that do not support that size access. However we forgot to tell the core memory subsystem about this by specifying the .impl and .valid fields in the MemoryRegionOps struct, so the core was happily simulating 8 byte accesses by combining two 4 byte accesses. This doesn't have much guest-visible effect, since there aren't many 8 byte registers and they all support being written in two 4 byte parts. Set the .impl and .valid fields to say that all sizes from 1 to 8 bytes are both valid and implemented by the device. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 6d3c8ee231c..0b8f79a1227 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -369,11 +369,19 @@ static const MemoryRegionOps gic_ops[] = { .read_with_attrs = gicv3_dist_read, .write_with_attrs = gicv3_dist_write, .endianness = DEVICE_NATIVE_ENDIAN, + .valid.min_access_size = 1, + .valid.max_access_size = 8, + .impl.min_access_size = 1, + .impl.max_access_size = 8, }, { .read_with_attrs = gicv3_redist_read, .write_with_attrs = gicv3_redist_write, .endianness = DEVICE_NATIVE_ENDIAN, + .valid.min_access_size = 1, + .valid.max_access_size = 8, + .impl.min_access_size = 1, + .impl.max_access_size = 8, } }; From patchwork Thu Mar 3 20:23:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547807 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp954632imq; Thu, 3 Mar 2022 12:27:09 -0800 (PST) X-Google-Smtp-Source: ABdhPJwqPlddvgqUtNKaTOTq9Q6PpZ2YteE1wyA8KtS7Dn/dAdmO+mJIIAL3gUo7V+oseBMhRep/ X-Received: by 2002:a81:a748:0:b0:2d6:1f8b:23a9 with SMTP id e69-20020a81a748000000b002d61f8b23a9mr36906491ywh.329.1646339229680; Thu, 03 Mar 2022 12:27:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646339229; cv=none; d=google.com; s=arc-20160816; b=YTb/BKyhkg1Ee+K8G/6M7ZLAGmTnzeu+OxOpKwS22bee3JJxFj8uqAzJ2a3SwANiUi j0Q7wmnNtBciY1k0jInUkWhN09CfaXq49iQ19zSnFV1EmaJxrbg278PFxOHSqZGL/LAo KBeefcKkSaAbZv9dJWu5/my3GnxcQCLMyHeW9tELaPGx4IQ3ige4WUrFwcs7FYHg+Ofe Tw8VJ0m0CeJrf+YMFJ/iXT/wkLtSk3Q5pZ2x1GUf9p3mardl6WV3BiJ/mDxtNR+pddwT H76zCa61JIqRFtzTTf5MWjYx0n+Ax0dyVWAFaJxdo7vIe7p2APhpG9lqtck553FKWowz uk5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uXh/JEg5Ojwyym5i/HIshpVVO/CoNEWjAFuxDcAMKaM=; b=Ie9IPc6HpBWeqlCKceuWouOztP1r0xavR/Bqa1x7+2yErTurDq/8h89aM6vsU3AhwI TTd38xwLfxE5Gb+gE8kUuPdjhMBSsw7szhB8IaT0a81879sT3HyJ4kDifykBQ7QfS7d9 LcDQio4ZnHNGxkSJtAmo+3oU22BXfXGSL29RQaXnBt49YMVLVxH6RWCcSpX2ortYvy55 ytEvTGdRY5BiS+Oi7Zp6taFVDp9WrxnY3O5pfqwu0aQsZGdkIjZruRES1oMLo8H2l8sn UQu2J6Gl0OLD1eKp5zDCKhim6TXiNBg3I0Dy8o3G+N/HRNhNomQIVZzTcdsdZl3D49qz L+bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t0kvC9pL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id bu11-20020a056902090b00b006287d01649bsi2765125ybb.393.2022.03.03.12.27.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Mar 2022 12:27:09 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t0kvC9pL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPs2X-0007X5-5h for patch@linaro.org; Thu, 03 Mar 2022 15:27:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPrzL-0001wV-WE for qemu-devel@nongnu.org; Thu, 03 Mar 2022 15:23:52 -0500 Received: from [2a00:1450:4864:20::32b] (port=38868 helo=mail-wm1-x32b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nPrzK-0001aF-97 for qemu-devel@nongnu.org; Thu, 03 Mar 2022 15:23:51 -0500 Received: by mail-wm1-x32b.google.com with SMTP id m42-20020a05600c3b2a00b00382ab337e14so4821838wms.3 for ; Thu, 03 Mar 2022 12:23:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uXh/JEg5Ojwyym5i/HIshpVVO/CoNEWjAFuxDcAMKaM=; b=t0kvC9pLVwUMkJQ4I3iU4/DxiKZBqLj20I4aoau3o5xkZgwlCdfX2ZlTIRvHvQwfRF tEXJNPIWlWRJcBMltI6ueZSYuuCT7tVlUjbP3SlIa9GujD92TkSOqPa7v5Tm5/MBSgVY DGksTdMhOuabrknUVRT9F83S3AkafioBQ5FrGy0ntl7myl/8+ossWuhBMkygXHGeOO70 NCEcExPJsnysQrkDrn2zAiAYyPF3w4vih+wWdCWsCB/CeC2EvvU9TfNXh0dRWuuccbwD 5By4sgoegm2ZepJ6fO1e6Stf9H225tjpqPqIESF7nAJ73CAvYhgzSC1K/KEI8pvlkg1Q cqWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uXh/JEg5Ojwyym5i/HIshpVVO/CoNEWjAFuxDcAMKaM=; b=mPnpumG5JlbfBE/F/v/M8JybwnX47+RhKl0BVy8LyCcBqWThFyuqKzzELzhfgY3VOe U/QHohWWqav1EjMy0hktk0r1u36MsK+/4qs+/9bsvvMxFw/7gjpM55phlTZje4HsnT4Z o7DrXT8o0V5nvFHyPfM1YnJ/KAj31M5jWJPAI6Q/+l25sKEtWHr95S1Efm9B2EIr6Kqm 40Wc9+VhgzNw3QCyA8JN3KWhxo37yXzhd47OtGc7Djjt3+cDNVmBLHKXmt2aZMQJl/wO kO45wCENRdO4YFcYOKF5fu9T9q818zRFlXlzgHUoHEfpAoIvyBX4xtCSi/1iOc7QtCe+ 4vGw== X-Gm-Message-State: AOAM533x463fi4uC8LiL5D3FlXsfQm2bRF/7lNRa2D424cWTHDw2vggw Se0xn7cEO+R3uaKr6dKlpNlsjwKN1LbAiw== X-Received: by 2002:a7b:c347:0:b0:37e:68e6:d85c with SMTP id l7-20020a7bc347000000b0037e68e6d85cmr5022675wmj.176.1646339027932; Thu, 03 Mar 2022 12:23:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t5-20020adff045000000b001f0684c3404sm517060wro.11.2022.03.03.12.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:23:47 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/5] hw/intc/arm_gicv3: Fix missing spaces in error log messages Date: Thu, 3 Mar 2022 20:23:40 +0000 Message-Id: <20220303202341.2232284-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303202341.2232284-1-peter.maydell@linaro.org> References: <20220303202341.2232284-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32b (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We forgot a space in some log messages, so the output ended up looking like gicv3_dist_write: invalid guest write at offset 0000000000008000size 8 with a missing space before "size". Add the missing spaces. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_dist.c | 4 ++-- hw/intc/arm_gicv3_its.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 4164500ea96..28d913b2114 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -838,7 +838,7 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, if (!r) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest read at offset " TARGET_FMT_plx - "size %u\n", __func__, offset, size); + " size %u\n", __func__, offset, size); trace_gicv3_dist_badread(offset, size, attrs.secure); /* The spec requires that reserved registers are RAZ/WI; * so use MEMTX_ERROR returns from leaf functions as a way to @@ -879,7 +879,7 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data, if (!r) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write at offset " TARGET_FMT_plx - "size %u\n", __func__, offset, size); + " size %u\n", __func__, offset, size); trace_gicv3_dist_badwrite(offset, data, size, attrs.secure); /* The spec requires that reserved registers are RAZ/WI; * so use MEMTX_ERROR returns from leaf functions as a way to diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 9f4df6a8cbb..b96b874afdf 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1313,7 +1313,7 @@ static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data, if (!result) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest read at offset " TARGET_FMT_plx - "size %u\n", __func__, offset, size); + " size %u\n", __func__, offset, size); trace_gicv3_its_badread(offset, size); /* * The spec requires that reserved registers are RAZ/WI; @@ -1349,7 +1349,7 @@ static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data, if (!result) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write at offset " TARGET_FMT_plx - "size %u\n", __func__, offset, size); + " size %u\n", __func__, offset, size); trace_gicv3_its_badwrite(offset, data, size); /* * The spec requires that reserved registers are RAZ/WI; From patchwork Thu Mar 3 20:23:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547808 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp955533imq; Thu, 3 Mar 2022 12:28:37 -0800 (PST) X-Google-Smtp-Source: ABdhPJw6/ichlV9+oLApMJiYnuUkC6TMWBOAFLyOy/r6UbMVCYt0UDtlQRRQftgpPZLrWzQhaMDv X-Received: by 2002:a81:e343:0:b0:2db:58be:a8c7 with SMTP id w3-20020a81e343000000b002db58bea8c7mr25923545ywl.138.1646339317226; Thu, 03 Mar 2022 12:28:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646339317; cv=none; d=google.com; s=arc-20160816; b=ZKPBNVOnFiOH7d2AVAb77UZh76DkmR4sXWUYhv8n8x8sH/Kel9r73TSmguo7nw7VzT eO9LUYa7O/u2yxChHM5u8tnitWNxXhl/xBjsj6MiuWTNaVKeiq0toy0aEgwuEDRkXE+N QDKZNy1fwF2HInpOq77m9pFpgt83VMS6JawmVat4gpsZAHjOTBKT9RkGgIIdG7JhSZdQ Vl3lkgzSIA1kkscR7K4dthAo4PEpJPu61wh3iuXplKnMaQq68srK4FoIRnbMxei+5sni PUhkCdTkFGfxlCP+o/9a5SkC0g7FIlQbicHb7U4muQc51PPBkuxj+ZnLeGGk+3H+CIFt UhBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xKReK7BLUtScKzpLEmLwjn4Pt9dG6hDPDWKrdARJTHU=; b=yUf7OHU1EAYe+PXFkaASw+XmGQr6SM9NevuLehp6/NykizA1HIR4pe4K+bXK0/lGvC aTAUBFmPpjZai9ExS81Pnt0q1tJnmTX3JcY4UfoUPTgl0d5wuMvp+YUZkCCdEXAc9AhQ VvMc+5s9dv7rMeYFBHKFzH99mHL6fjut79Ucx56qnvI5OyR5ScziL3esMtjPkHJ7QaJY r1rTASswU1mlwXAV9mCS4vsbhkyhx1PnOJ3LwCwuExJIhi7Gde0V0CK/3f1b7ihJ5Y88 aXM2WfIdakyqk6xjazZiyfF/70eNznNQuTHABHZVmnX/p9vIXbyliy3MnR0Q3WzCMXzO GDew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FxxjCgcD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p22-20020a254216000000b0062883fa82f2si2385500yba.582.2022.03.03.12.28.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Mar 2022 12:28:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FxxjCgcD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45468 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPs3w-0002wL-OY for patch@linaro.org; Thu, 03 Mar 2022 15:28:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49310) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPrzL-0001wT-Mk for qemu-devel@nongnu.org; Thu, 03 Mar 2022 15:23:52 -0500 Received: from [2a00:1450:4864:20::330] (port=33255 helo=mail-wm1-x330.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nPrzK-0001ab-9T for qemu-devel@nongnu.org; Thu, 03 Mar 2022 15:23:51 -0500 Received: by mail-wm1-x330.google.com with SMTP id n33-20020a05600c3ba100b003832caf7f3aso3129603wms.0 for ; Thu, 03 Mar 2022 12:23:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xKReK7BLUtScKzpLEmLwjn4Pt9dG6hDPDWKrdARJTHU=; b=FxxjCgcDHZwQsUyp6QeRLD3H+nQyw1V2wfkP202duNc+5jC56dwCux1o2tsoyHqFP7 oDtQa3GuiUhQsR8HGGmH5ZJkcGDegzl2LQPOzpiPU99FFJUVUtlSGtks+ojYWlwkEmt0 VUZLf9veJ4sWobkZp44Vv0Lg+w3j2+fDpRLgLrwtfti2f+oW1HNYV+x4YS48fUL33hA3 D5lc1Xt7jZdtsBFfBU0X7vzjlHekIlOmRB+ozOduLBZmWPvPKtgZmGObMCveGqUUgROL yqje+Qe35Oh37tEi7nYGVY3cHAvsuNmDRx+bpptrF17XLSzpfl4OUGFYAZspTK1+QPoO t6TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xKReK7BLUtScKzpLEmLwjn4Pt9dG6hDPDWKrdARJTHU=; b=cWrfwgPSd847A1cTffQpPcjZn9DRvRbQbYuxAPbARj6Gc2d6Hh1HBNE3khdEjBU1Eb Fcywj9C2LlpOQJ5qHGj9B+BKEZIUI1LUCLqHMTN0NjHOikH2fjt/5utWI0jDXPOEy95A 2jk2ETjA+kkB90F49h6Do+xBOC4lr5NIN5b4a7nIdbIBbW3jgqhQzkFVS5j85WUFUa59 sYfPbDsRnOy+ZnCxpSwgc5KiardYNoeoRjXSDdjNXynIbFPAvNF0hdGEYbX6FLhFghHb 8BkrfChem5fwhG7pchjPE+/nMl6ehRubQTOKteghLRAa1d4GVATeoMK88T+wsjOm4VmL HRSw== X-Gm-Message-State: AOAM531WJLY+wa7tsD7HTxqOIK/6sBOfKl98tnAhi2enHD/8avuz2CQp hEKP4mhUkxLzdNdT7cPU+t6xRFim3Imvvw== X-Received: by 2002:a05:600c:3c98:b0:37f:2f14:7be7 with SMTP id bg24-20020a05600c3c9800b0037f2f147be7mr5143205wmb.180.1646339028719; Thu, 03 Mar 2022 12:23:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t5-20020adff045000000b001f0684c3404sm517060wro.11.2022.03.03.12.23.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:23:48 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/5] hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event Date: Thu, 3 Mar 2022 20:23:41 +0000 Message-Id: <20220303202341.2232284-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303202341.2232284-1-peter.maydell@linaro.org> References: <20220303202341.2232284-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::330 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The trace_gicv3_icv_hppir_read trace event takes an integer value which it uses to form the register name, which should be either ICV_HPPIR0 or ICV_HPPIR1. We were passing in the 'grp' variable for this, but that is either GICV3_G0 or GICV3_G1NS, which happen to be 0 and 2, which meant that tracing for the ICV_HPPIR1 register was incorrectly printed as ICV_HPPIR2. Use the same approach we do for all the other similar trace events, and pass in 'ri->crm == 8 ? 0 : 1', deriving the index value directly from the ARMCPRegInfo struct. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_cpuif.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index d7e03d0cab8..1a3d440a54b 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -612,7 +612,8 @@ static uint64_t icv_hppir_read(CPUARMState *env, const ARMCPRegInfo *ri) } } - trace_gicv3_icv_hppir_read(grp, gicv3_redist_affid(cs), value); + trace_gicv3_icv_hppir_read(ri->crm == 8 ? 0 : 1, + gicv3_redist_affid(cs), value); return value; }