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[24.155.109.49]) by smtp.googlemail.com with ESMTPSA id c78sm8545501oig.30.2018.12.03.13.32.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Dec 2018 13:32:26 -0800 (PST) From: Rob Herring To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Sean Hudson , Frank Rowand , linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Grant Likely , Kumar Gala , arm@kernel.org, Jonathan Corbet , Mark Rutland , Masahiro Yamada , Michal Marek , linux-doc@vger.kernel.org, linux-kbuild@vger.kernel.org Subject: [PATCH v2 01/34] kbuild: Add support for DT binding schema checks Date: Mon, 3 Dec 2018 15:31:50 -0600 Message-Id: <20181203213223.16986-2-robh@kernel.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181203213223.16986-1-robh@kernel.org> References: <20181203213223.16986-1-robh@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds the build infrastructure for checking DT binding schema documents and validating dts files using the binding schema. Check DT binding schema documents: make dt_binding_check Build dts files and check using DT binding schema: make dtbs_check Optionally, DT_SCHEMA_FILES can passed in with a schema file(s) to use for validation. This makes it easier to find and fix errors generated by a specific schema. Currently, the validation targets are separate from a normal build to avoid a hard dependency on the external DT schema project and because there are lots of warnings generated. Cc: Jonathan Corbet Cc: Mark Rutland Cc: Masahiro Yamada Cc: Michal Marek Cc: linux-doc@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kbuild@vger.kernel.org Signed-off-by: Rob Herring --- .gitignore | 1 + Documentation/Makefile | 2 +- Documentation/devicetree/bindings/.gitignore | 1 + Documentation/devicetree/bindings/Makefile | 33 ++++++++++++++++++++ Makefile | 11 +++++-- scripts/Makefile.lib | 24 ++++++++++++-- 6 files changed, 67 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/.gitignore create mode 100644 Documentation/devicetree/bindings/Makefile -- 2.19.1 diff --git a/.gitignore b/.gitignore index 97ba6b79834c..a20ac26aa2f5 100644 --- a/.gitignore +++ b/.gitignore @@ -15,6 +15,7 @@ *.bin *.bz2 *.c.[012]*.* +*.dt.yaml *.dtb *.dtb.S *.dwo diff --git a/Documentation/Makefile b/Documentation/Makefile index 2ca77ad0f238..9786957c6a35 100644 --- a/Documentation/Makefile +++ b/Documentation/Makefile @@ -2,7 +2,7 @@ # Makefile for Sphinx documentation # -subdir-y := +subdir-y := devicetree/bindings/ # You can set these variables from the command line. SPHINXBUILD = sphinx-build diff --git a/Documentation/devicetree/bindings/.gitignore b/Documentation/devicetree/bindings/.gitignore new file mode 100644 index 000000000000..d9194c02dd08 --- /dev/null +++ b/Documentation/devicetree/bindings/.gitignore @@ -0,0 +1 @@ +*.example.dts diff --git a/Documentation/devicetree/bindings/Makefile b/Documentation/devicetree/bindings/Makefile new file mode 100644 index 000000000000..ee0110dd8131 --- /dev/null +++ b/Documentation/devicetree/bindings/Makefile @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 +DT_DOC_CHECKER ?= dt-doc-validate +DT_EXTRACT_EX ?= dt-extract-example +DT_MK_SCHEMA ?= dt-mk-schema +DT_MK_SCHEMA_FLAGS := $(if $(DT_SCHEMA_FILES), -u) + +quiet_cmd_chk_binding = CHKDT $< + cmd_chk_binding = (set -e; \ + $(DT_DOC_CHECKER) $< ; \ + mkdir -p $(dir $@) ; \ + $(DT_EXTRACT_EX) $< > $@ ) + +$(obj)/%.example.dts: $(src)/%.yaml FORCE + $(call if_changed,chk_binding) + +DT_TMP_SCHEMA := .schema.yaml.tmp +extra-y += $(DT_TMP_SCHEMA) + +quiet_cmd_mk_schema = SCHEMA $@ + cmd_mk_schema = mkdir -p $(obj); \ + rm -f $@; \ + $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) -o $@ $< + +DT_DOCS = $(shell cd $(srctree)/$(src) && find * -name '*.yaml') +DT_SCHEMA_FILES ?= $(addprefix $(src)/,$(DT_DOCS)) + +extra-y += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES)) +extra-y += $(patsubst $(src)/%.yaml,%.example.dtb, $(DT_SCHEMA_FILES)) + +$(obj)/$(DT_TMP_SCHEMA): $(addprefix $(obj)/,$(patsubst $(src)/%.yaml,%.example.dtb, $(DT_SCHEMA_FILES))) + +$(obj)/$(DT_TMP_SCHEMA): $(addprefix $(srctree)/, $(DT_SCHEMA_FILES)) FORCE + $(call if_changed,mk_schema) diff --git a/Makefile b/Makefile index 2f36db897895..ff59adf43300 100644 --- a/Makefile +++ b/Makefile @@ -1232,10 +1232,13 @@ ifneq ($(dtstree),) %.dtb: prepare3 scripts_dtc $(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@ -PHONY += dtbs dtbs_install +PHONY += dtbs dtbs_install dt_binding_check dtbs: prepare3 scripts_dtc $(Q)$(MAKE) $(build)=$(dtstree) +dtbs_check: prepare3 dt_binding_check + $(Q)$(MAKE) $(build)=$(dtstree) CHECK_DTBS=1 + dtbs_install: $(Q)$(MAKE) $(dtbinst)=$(dtstree) @@ -1249,6 +1252,9 @@ PHONY += scripts_dtc scripts_dtc: scripts_basic $(Q)$(MAKE) $(build)=scripts/dtc +dt_binding_check: scripts_dtc + $(Q)$(MAKE) $(build)=Documentation/devicetree/bindings + # --------------------------------------------------------------------------- # Modules @@ -1611,7 +1617,8 @@ clean: $(clean-dirs) $(call cmd,rmfiles) @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \ \( -name '*.[aios]' -o -name '*.ko' -o -name '.*.cmd' \ - -o -name '*.ko.*' -o -name '*.dtb' -o -name '*.dtb.S' \ + -o -name '*.ko.*' \ + -o -name '*.dtb' -o -name '*.dtb.S' -o -name '*.dt.yaml' \ -o -name '*.dwo' -o -name '*.lst' \ -o -name '*.su' \ -o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \ diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 8fe4468f9bda..d1c5630ba24c 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -61,6 +61,11 @@ real-obj-m := $(foreach m, $(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y)) extra-y += $(dtb-y) extra-$(CONFIG_OF_ALL_DTBS) += $(dtb-) +ifneq ($(CHECK_DTBS),) +extra-y += $(patsubst %.dtb,%.dt.yaml, $(dtb-y)) +extra-$(CONFIG_OF_ALL_DTBS) += $(patsubst %.dtb,%.dt.yaml, $(dtb-)) +endif + # Add subdir path extra-y := $(addprefix $(obj)/,$(extra-y)) @@ -284,13 +289,28 @@ $(obj)/%.dtb.S: $(obj)/%.dtb FORCE quiet_cmd_dtc = DTC $@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ - $(DTC) -O dtb -o $@ -b 0 \ + $(DTC) -O $(2) -o $@ -b 0 \ $(addprefix -i,$(dir $<) $(DTC_INCLUDE)) $(DTC_FLAGS) \ -d $(depfile).dtc.tmp $(dtc-tmp) ; \ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) $(obj)/%.dtb: $(src)/%.dts $(DTC) FORCE - $(call if_changed_dep,dtc) + $(call if_changed_dep,dtc,dtb) + +DT_CHECKER ?= dt-validate +DT_BINDING_DIR := Documentation/devicetree/bindings +DT_TMP_SCHEMA := $(objtree)/$(DT_BINDING_DIR)/.schema.yaml.tmp + +quiet_cmd_dtb_check = CHECK $@ + cmd_dtb_check = $(DT_CHECKER) -p $(DT_TMP_SCHEMA) $@ ; + +define rule_dtc_dt_yaml + $(call cmd_and_fixdep,dtc,yaml) \ + $(call echo-cmd,dtb_check) $(cmd_dtb_check) +endef + +$(obj)/%.dt.yaml: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE + $(call if_changed_rule,dtc_dt_yaml) dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) From patchwork Mon Dec 3 21:31:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 152779 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp7320524ljp; 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[24.155.109.49]) by smtp.googlemail.com with ESMTPSA id c78sm8545501oig.30.2018.12.03.13.32.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Dec 2018 13:32:33 -0800 (PST) From: Rob Herring To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Sean Hudson , Frank Rowand , linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Grant Likely , Kumar Gala , arm@kernel.org, Mark Rutland , Matthias Brugger , linux-mediatek@lists.infradead.org Subject: [PATCH v2 07/34] dt-bindings: arm: Convert cpu binding to json-schema Date: Mon, 3 Dec 2018 15:31:56 -0600 Message-Id: <20181203213223.16986-8-robh@kernel.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181203213223.16986-1-robh@kernel.org> References: <20181203213223.16986-1-robh@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert ARM CPU binding to DT schema format using json-schema. Cc: Mark Rutland Cc: Matthias Brugger Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/cpus.txt | 490 ----------------- .../devicetree/bindings/arm/cpus.yaml | 507 ++++++++++++++++++ 2 files changed, 507 insertions(+), 490 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/cpus.txt create mode 100644 Documentation/devicetree/bindings/arm/cpus.yaml -- 2.19.1 diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt deleted file mode 100644 index b0198a1cf403..000000000000 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ /dev/null @@ -1,490 +0,0 @@ -================= -ARM CPUs bindings -================= - -The device tree allows to describe the layout of CPUs in a system through -the "cpus" node, which in turn contains a number of subnodes (ie "cpu") -defining properties for every cpu. - -Bindings for CPU nodes follow the Devicetree Specification, available from: - -https://www.devicetree.org/specifications/ - -with updates for 32-bit and 64-bit ARM systems provided in this document. - -================================ -Convention used in this document -================================ - -This document follows the conventions described in the Devicetree -Specification, with the addition: - -- square brackets define bitfields, eg reg[7:0] value of the bitfield in - the reg property contained in bits 7 down to 0 - -===================================== -cpus and cpu node bindings definition -===================================== - -The ARM architecture, in accordance with the Devicetree Specification, -requires the cpus and cpu nodes to be present and contain the properties -described below. - -- cpus node - - Description: Container of cpu nodes - - The node name must be "cpus". - - A cpus node must define the following properties: - - - #address-cells - Usage: required - Value type: - - Definition depends on ARM architecture version and - configuration: - - # On uniprocessor ARM architectures previous to v7 - value must be 1, to enable a simple enumeration - scheme for processors that do not have a HW CPU - identification register. - # On 32-bit ARM 11 MPcore, ARM v7 or later systems - value must be 1, that corresponds to CPUID/MPIDR - registers sizes. - # On ARM v8 64-bit systems value should be set to 2, - that corresponds to the MPIDR_EL1 register size. - If MPIDR_EL1[63:32] value is equal to 0 on all CPUs - in the system, #address-cells can be set to 1, since - MPIDR_EL1[63:32] bits are not used for CPUs - identification. - - #size-cells - Usage: required - Value type: - Definition: must be set to 0 - -- cpu node - - Description: Describes a CPU in an ARM based system - - PROPERTIES - - - device_type - Usage: required - Value type: - Definition: must be "cpu" - - reg - Usage and definition depend on ARM architecture version and - configuration: - - # On uniprocessor ARM architectures previous to v7 - this property is required and must be set to 0. - - # On ARM 11 MPcore based systems this property is - required and matches the CPUID[11:0] register bits. - - Bits [11:0] in the reg cell must be set to - bits [11:0] in CPU ID register. - - All other bits in the reg cell must be set to 0. - - # On 32-bit ARM v7 or later systems this property is - required and matches the CPU MPIDR[23:0] register - bits. - - Bits [23:0] in the reg cell must be set to - bits [23:0] in MPIDR. - - All other bits in the reg cell must be set to 0. - - # On ARM v8 64-bit systems this property is required - and matches the MPIDR_EL1 register affinity bits. - - * If cpus node's #address-cells property is set to 2 - - The first reg cell bits [7:0] must be set to - bits [39:32] of MPIDR_EL1. - - The second reg cell bits [23:0] must be set to - bits [23:0] of MPIDR_EL1. - - * If cpus node's #address-cells property is set to 1 - - The reg cell bits [23:0] must be set to bits [23:0] - of MPIDR_EL1. - - All other bits in the reg cells must be set to 0. - - - compatible: - Usage: required - Value type: - Definition: should be one of: - "arm,arm710t" - "arm,arm720t" - "arm,arm740t" - "arm,arm7ej-s" - "arm,arm7tdmi" - "arm,arm7tdmi-s" - "arm,arm9es" - "arm,arm9ej-s" - "arm,arm920t" - "arm,arm922t" - "arm,arm925" - "arm,arm926e-s" - "arm,arm926ej-s" - "arm,arm940t" - "arm,arm946e-s" - "arm,arm966e-s" - "arm,arm968e-s" - "arm,arm9tdmi" - "arm,arm1020e" - "arm,arm1020t" - "arm,arm1022e" - "arm,arm1026ej-s" - "arm,arm1136j-s" - "arm,arm1136jf-s" - "arm,arm1156t2-s" - "arm,arm1156t2f-s" - "arm,arm1176jzf" - "arm,arm1176jz-s" - "arm,arm1176jzf-s" - "arm,arm11mpcore" - "arm,cortex-a5" - "arm,cortex-a7" - "arm,cortex-a8" - "arm,cortex-a9" - "arm,cortex-a12" - "arm,cortex-a15" - "arm,cortex-a17" - "arm,cortex-a53" - "arm,cortex-a57" - "arm,cortex-a72" - "arm,cortex-a73" - "arm,cortex-m0" - "arm,cortex-m0+" - "arm,cortex-m1" - "arm,cortex-m3" - "arm,cortex-m4" - "arm,cortex-r4" - "arm,cortex-r5" - "arm,cortex-r7" - "brcm,brahma-b15" - "brcm,brahma-b53" - "brcm,vulcan" - "cavium,thunder" - "cavium,thunder2" - "faraday,fa526" - "intel,sa110" - "intel,sa1100" - "marvell,feroceon" - "marvell,mohawk" - "marvell,pj4a" - "marvell,pj4b" - "marvell,sheeva-v5" - "nvidia,tegra132-denver" - "nvidia,tegra186-denver" - "nvidia,tegra194-carmel" - "qcom,krait" - "qcom,kryo" - "qcom,kryo385" - "qcom,scorpion" - - enable-method - Value type: - Usage and definition depend on ARM architecture version. - # On ARM v8 64-bit this property is required and must - be one of: - "psci" - "spin-table" - # On ARM 32-bit systems this property is optional and - can be one of: - "actions,s500-smp" - "allwinner,sun6i-a31" - "allwinner,sun8i-a23" - "allwinner,sun9i-a80-smp" - "amlogic,meson8-smp" - "amlogic,meson8b-smp" - "arm,realview-smp" - "brcm,bcm11351-cpu-method" - "brcm,bcm23550" - "brcm,bcm2836-smp" - "brcm,bcm-nsp-smp" - "brcm,brahma-b15" - "marvell,armada-375-smp" - "marvell,armada-380-smp" - "marvell,armada-390-smp" - "marvell,armada-xp-smp" - "marvell,98dx3236-smp" - "mediatek,mt6589-smp" - "mediatek,mt81xx-tz-smp" - "qcom,gcc-msm8660" - "qcom,kpss-acc-v1" - "qcom,kpss-acc-v2" - "renesas,apmu" - "renesas,r9a06g032-smp" - "rockchip,rk3036-smp" - "rockchip,rk3066-smp" - "ste,dbx500-smp" - - - cpu-release-addr - Usage: required for systems that have an "enable-method" - property value of "spin-table". - Value type: - Definition: - # On ARM v8 64-bit systems must be a two cell - property identifying a 64-bit zero-initialised - memory location. - - - qcom,saw - Usage: required for systems that have an "enable-method" - property value of "qcom,kpss-acc-v1" or - "qcom,kpss-acc-v2" - Value type: - Definition: Specifies the SAW[1] node associated with this CPU. - - - qcom,acc - Usage: required for systems that have an "enable-method" - property value of "qcom,kpss-acc-v1" or - "qcom,kpss-acc-v2" - Value type: - Definition: Specifies the ACC[2] node associated with this CPU. - - - cpu-idle-states - Usage: Optional - Value type: - Definition: - # List of phandles to idle state nodes supported - by this cpu [3]. - - - capacity-dmips-mhz - Usage: Optional - Value type: - Definition: - # u32 value representing CPU capacity [4] in - DMIPS/MHz, relative to highest capacity-dmips-mhz - in the system. - - - rockchip,pmu - Usage: optional for systems that have an "enable-method" - property value of "rockchip,rk3066-smp" - While optional, it is the preferred way to get access to - the cpu-core power-domains. - Value type: - Definition: Specifies the syscon node controlling the cpu core - power domains. - - - dynamic-power-coefficient - Usage: optional - Value type: - Definition: A u32 value that represents the running time dynamic - power coefficient in units of uW/MHz/V^2. The - coefficient can either be calculated from power - measurements or derived by analysis. - - The dynamic power consumption of the CPU is - proportional to the square of the Voltage (V) and - the clock frequency (f). The coefficient is used to - calculate the dynamic power as below - - - Pdyn = dynamic-power-coefficient * V^2 * f - - where voltage is in V, frequency is in MHz. - -Example 1 (dual-cluster big.LITTLE system 32-bit): - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - }; - }; - -Example 2 (Cortex-A8 uniprocessor 32-bit system): - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - }; - }; - -Example 3 (ARM 926EJ-S uniprocessor 32-bit system): - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - reg = <0x0>; - }; - }; - -Example 4 (ARM Cortex-A57 64-bit system): - -cpus { - #size-cells = <0>; - #address-cells = <2>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; -}; - --- -[1] arm/msm/qcom,saw2.txt -[2] arm/msm/qcom,kpss-acc.txt -[3] ARM Linux kernel documentation - idle states bindings - Documentation/devicetree/bindings/arm/idle-states.txt -[4] ARM Linux kernel documentation - cpu capacity bindings - Documentation/devicetree/bindings/arm/cpu-capacity.txt diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml new file mode 100644 index 000000000000..298c17b327c6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -0,0 +1,507 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM CPUs bindings + +maintainers: + - Lorenzo Pieralisi + +description: |+ + The device tree allows to describe the layout of CPUs in a system through + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") + defining properties for every cpu. + + Bindings for CPU nodes follow the Devicetree Specification, available from: + + https://www.devicetree.org/specifications/ + + with updates for 32-bit and 64-bit ARM systems provided in this document. + + ================================ + Convention used in this document + ================================ + + This document follows the conventions described in the Devicetree + Specification, with the addition: + + - square brackets define bitfields, eg reg[7:0] value of the bitfield in + the reg property contained in bits 7 down to 0 + + ===================================== + cpus and cpu node bindings definition + ===================================== + + The ARM architecture, in accordance with the Devicetree Specification, + requires the cpus and cpu nodes to be present and contain the properties + described below. + +properties: + $nodename: + const: cpus + description: Container of cpu nodes + + '#address-cells': + enum: [1, 2] + description: | + Definition depends on ARM architecture version and configuration: + + On uniprocessor ARM architectures previous to v7 + value must be 1, to enable a simple enumeration + scheme for processors that do not have a HW CPU + identification register. + On 32-bit ARM 11 MPcore, ARM v7 or later systems + value must be 1, that corresponds to CPUID/MPIDR + registers sizes. + On ARM v8 64-bit systems value should be set to 2, + that corresponds to the MPIDR_EL1 register size. + If MPIDR_EL1[63:32] value is equal to 0 on all CPUs + in the system, #address-cells can be set to 1, since + MPIDR_EL1[63:32] bits are not used for CPUs + identification. + + '#size-cells': + const: 0 + +patternProperties: + '^cpu@[0-9a-f]+$': + properties: + device_type: + const: cpu + + reg: + maxItems: 1 + description: | + Usage and definition depend on ARM architecture version and + configuration: + + On uniprocessor ARM architectures previous to v7 + this property is required and must be set to 0. + + On ARM 11 MPcore based systems this property is + required and matches the CPUID[11:0] register bits. + + Bits [11:0] in the reg cell must be set to + bits [11:0] in CPU ID register. + + All other bits in the reg cell must be set to 0. + + On 32-bit ARM v7 or later systems this property is + required and matches the CPU MPIDR[23:0] register + bits. + + Bits [23:0] in the reg cell must be set to + bits [23:0] in MPIDR. + + All other bits in the reg cell must be set to 0. + + On ARM v8 64-bit systems this property is required + and matches the MPIDR_EL1 register affinity bits. + + * If cpus node's #address-cells property is set to 2 + + The first reg cell bits [7:0] must be set to + bits [39:32] of MPIDR_EL1. + + The second reg cell bits [23:0] must be set to + bits [23:0] of MPIDR_EL1. + + * If cpus node's #address-cells property is set to 1 + + The reg cell bits [23:0] must be set to bits [23:0] + of MPIDR_EL1. + + All other bits in the reg cells must be set to 0. + + compatible: + items: + - enum: + - arm,arm710t + - arm,arm720t + - arm,arm740t + - arm,arm7ej-s + - arm,arm7tdmi + - arm,arm7tdmi-s + - arm,arm9es + - arm,arm9ej-s + - arm,arm920t + - arm,arm922t + - arm,arm925 + - arm,arm926e-s + - arm,arm926ej-s + - arm,arm940t + - arm,arm946e-s + - arm,arm966e-s + - arm,arm968e-s + - arm,arm9tdmi + - arm,arm1020e + - arm,arm1020t + - arm,arm1022e + - arm,arm1026ej-s + - arm,arm1136j-s + - arm,arm1136jf-s + - arm,arm1156t2-s + - arm,arm1156t2f-s + - arm,arm1176jzf + - arm,arm1176jz-s + - arm,arm1176jzf-s + - arm,arm11mpcore + - arm,armv8 # Only for s/w models + - arm,cortex-a5 + - arm,cortex-a7 + - arm,cortex-a8 + - arm,cortex-a9 + - arm,cortex-a12 + - arm,cortex-a15 + - arm,cortex-a17 + - arm,cortex-a53 + - arm,cortex-a57 + - arm,cortex-a72 + - arm,cortex-a73 + - arm,cortex-m0 + - arm,cortex-m0+ + - arm,cortex-m1 + - arm,cortex-m3 + - arm,cortex-m4 + - arm,cortex-r4 + - arm,cortex-r5 + - arm,cortex-r7 + - brcm,brahma-b15 + - brcm,brahma-b53 + - brcm,vulcan + - cavium,thunder + - cavium,thunder2 + - faraday,fa526 + - intel,sa110 + - intel,sa1100 + - marvell,feroceon + - marvell,mohawk + - marvell,pj4a + - marvell,pj4b + - marvell,sheeva-v5 + - marvell,sheeva-v7 + - nvidia,tegra132-denver + - nvidia,tegra186-denver + - nvidia,tegra194-carmel + - qcom,krait + - qcom,kryo + - qcom,kryo385 + - qcom,scorpion + + enable-method: + allOf: + - $ref: '/schemas/types.yaml#/definitions/string' + - oneOf: + # On ARM v8 64-bit this property is required + - enum: + - psci + - spin-table + # On ARM 32-bit systems this property is optional + - enum: + - actions,s500-smp + - allwinner,sun6i-a31 + - allwinner,sun8i-a23 + - allwinner,sun9i-a80-smp + - allwinner,sun8i-a83t-smp + - amlogic,meson8-smp + - amlogic,meson8b-smp + - arm,realview-smp + - brcm,bcm11351-cpu-method + - brcm,bcm23550 + - brcm,bcm2836-smp + - brcm,bcm63138 + - brcm,bcm-nsp-smp + - brcm,brahma-b15 + - marvell,armada-375-smp + - marvell,armada-380-smp + - marvell,armada-390-smp + - marvell,armada-xp-smp + - marvell,98dx3236-smp + - mediatek,mt6589-smp + - mediatek,mt81xx-tz-smp + - qcom,gcc-msm8660 + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + - renesas,apmu + - renesas,r9a06g032-smp + - rockchip,rk3036-smp + - rockchip,rk3066-smp + - ste,dbx500-smp + + cpu-release-addr: + $ref: '/schemas/types.yaml#/definitions/uint64' + + description: + Required for systems that have an "enable-method" + property value of "spin-table". + On ARM v8 64-bit systems must be a two cell + property identifying a 64-bit zero-initialised + memory location. + + cpu-idle-states: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: | + List of phandles to idle state nodes supported + by this cpu (see ./idle-states.txt). + + capacity-dmips-mhz: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + u32 value representing CPU capacity (see ./cpu-capacity.txt) in + DMIPS/MHz, relative to highest capacity-dmips-mhz + in the system. + + dynamic-power-coefficient: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + A u32 value that represents the running time dynamic + power coefficient in units of uW/MHz/V^2. The + coefficient can either be calculated from power + measurements or derived by analysis. + + The dynamic power consumption of the CPU is + proportional to the square of the Voltage (V) and + the clock frequency (f). The coefficient is used to + calculate the dynamic power as below - + + Pdyn = dynamic-power-coefficient * V^2 * f + + where voltage is in V, frequency is in MHz. + + qcom,saw: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the SAW* node associated with this CPU. + + Required for systems that have an "enable-method" property + value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" + + * arm/msm/qcom,saw2.txt + + qcom,acc: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the ACC* node associated with this CPU. + + Required for systems that have an "enable-method" property + value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" + + * arm/msm/qcom,kpss-acc.txt + + rockchip,pmu: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the syscon node controlling the cpu core power domains. + + Optional for systems that have an "enable-method" + property value of "rockchip,rk3066-smp" + While optional, it is the preferred way to get access to + the cpu-core power-domains. + + required: + - device_type + - reg + - compatible + + dependencies: + cpu-release-addr: [enable-method] + rockchip,pmu: [enable-method] + +required: + - '#address-cells' + - '#size-cells' + +examples: + - | + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + }; + }; + + - | + // Example 2 (Cortex-A8 uniprocessor 32-bit system): + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + }; + }; + + - | + // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + reg = <0x0>; + }; + }; + + - | + // Example 4 (ARM Cortex-A57 64-bit system): + cpus { + #size-cells = <0>; + #address-cells = <2>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10000>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10001>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10000>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10001>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + }; +... 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[24.155.109.49]) by smtp.googlemail.com with ESMTPSA id c78sm8545501oig.30.2018.12.03.13.32.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Dec 2018 13:32:34 -0800 (PST) From: Rob Herring To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Sean Hudson , Frank Rowand , linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Grant Likely , Kumar Gala , arm@kernel.org, Will Deacon , Mark Rutland Subject: [PATCH v2 08/34] dt-bindings: arm: Convert PMU binding to json-schema Date: Mon, 3 Dec 2018 15:31:57 -0600 Message-Id: <20181203213223.16986-9-robh@kernel.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181203213223.16986-1-robh@kernel.org> References: <20181203213223.16986-1-robh@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert ARM PMU binding to DT schema format using json-schema. Cc: Will Deacon Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/pmu.txt | 70 -------------- .../devicetree/bindings/arm/pmu.yaml | 91 +++++++++++++++++++ 2 files changed, 91 insertions(+), 70 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/pmu.txt create mode 100644 Documentation/devicetree/bindings/arm/pmu.yaml -- 2.19.1 diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt deleted file mode 100644 index 13611a8199bb..000000000000 --- a/Documentation/devicetree/bindings/arm/pmu.txt +++ /dev/null @@ -1,70 +0,0 @@ -* ARM Performance Monitor Units - -ARM cores often have a PMU for counting cpu and cache events like cache misses -and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU -representation in the device tree should be done as under:- - -Required properties: - -- compatible : should be one of - "apm,potenza-pmu" - "arm,armv8-pmuv3" - "arm,cortex-a73-pmu" - "arm,cortex-a72-pmu" - "arm,cortex-a57-pmu" - "arm,cortex-a53-pmu" - "arm,cortex-a35-pmu" - "arm,cortex-a17-pmu" - "arm,cortex-a15-pmu" - "arm,cortex-a12-pmu" - "arm,cortex-a9-pmu" - "arm,cortex-a8-pmu" - "arm,cortex-a7-pmu" - "arm,cortex-a5-pmu" - "arm,arm11mpcore-pmu" - "arm,arm1176-pmu" - "arm,arm1136-pmu" - "brcm,vulcan-pmu" - "cavium,thunder-pmu" - "qcom,scorpion-pmu" - "qcom,scorpion-mp-pmu" - "qcom,krait-pmu" -- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu - interrupt (PPI) then 1 interrupt should be specified. - -Optional properties: - -- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU - nodes corresponding directly to the affinity of - the SPIs listed in the interrupts property. - - When using a PPI, specifies a list of phandles to CPU - nodes corresponding to the set of CPUs which have - a PMU of this type signalling the PPI listed in the - interrupts property, unless this is already specified - by the PPI interrupt specifier itself (in which case - the interrupt-affinity property shouldn't be present). - - This property should be present when there is more than - a single SPI. - - -- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd - events. - -- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register - (SDER) is accessible. This will cause the driver to do - any setup required that is only possible in ARMv7 secure - state. If not present the ARMv7 SDER will not be touched, - which means the PMU may fail to operate unless external - code (bootloader or security monitor) has performed the - appropriate initialisation. Note that this property is - not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux - in Non-secure state. - -Example: - -pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <100 101>; -}; diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml new file mode 100644 index 000000000000..3ea4abfbf276 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Performance Monitor Units + +maintainers: + - Mark Rutland + - Will Deacon + +description: |+ + ARM cores often have a PMU for counting cpu and cache events like cache misses + and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU + representation in the device tree should be done as under:- + +properties: + compatible: + oneOf: + - items: + - enum: + - apm,potenza-pmu + - arm,armv8-pmuv3 + - arm,cortex-a73-pmu + - arm,cortex-a72-pmu + - arm,cortex-a57-pmu + - arm,cortex-a53-pmu + - arm,cortex-a35-pmu + - arm,cortex-a17-pmu + - arm,cortex-a15-pmu + - arm,cortex-a12-pmu + - arm,cortex-a9-pmu + - arm,cortex-a8-pmu + - arm,cortex-a7-pmu + - arm,cortex-a5-pmu + - arm,arm11mpcore-pmu + - arm,arm1176-pmu + - arm,arm1136-pmu + - brcm,vulcan-pmu + - cavium,thunder-pmu + - qcom,scorpion-pmu + - qcom,scorpion-mp-pmu + - qcom,krait-pmu + - items: + - const: arm,cortex-a7-pmu + - const: arm,cortex-a15-pmu + + interrupts: + # Don't know how many CPUs, so no constraints to specify + description: 1 per-cpu interrupt (PPI) or 1 interrupt per core. + + interrupt-affinity: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + When using SPIs, specifies a list of phandles to CPU + nodes corresponding directly to the affinity of + the SPIs listed in the interrupts property. + + When using a PPI, specifies a list of phandles to CPU + nodes corresponding to the set of CPUs which have + a PMU of this type signalling the PPI listed in the + interrupts property, unless this is already specified + by the PPI interrupt specifier itself (in which case + the interrupt-affinity property shouldn't be present). + + This property should be present when there is more than + a single SPI. + + qcom,no-pc-write: + type: boolean + description: + Indicates that this PMU doesn't support the 0xc and 0xd events. + + secure-reg-access: + type: boolean + description: + Indicates that the ARMv7 Secure Debug Enable Register + (SDER) is accessible. This will cause the driver to do + any setup required that is only possible in ARMv7 secure + state. If not present the ARMv7 SDER will not be touched, + which means the PMU may fail to operate unless external + code (bootloader or security monitor) has performed the + appropriate initialisation. Note that this property is + not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux + in Non-secure state. + +required: + - compatible + +... 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[24.155.109.49]) by smtp.googlemail.com with ESMTPSA id c78sm8545501oig.30.2018.12.03.13.32.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Dec 2018 13:32:39 -0800 (PST) From: Rob Herring To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Sean Hudson , Frank Rowand , linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Grant Likely , Kumar Gala , arm@kernel.org, Mark Rutland , Dinh Nguyen Subject: [PATCH v2 12/34] dt-bindings: arm: Convert Altera board/soc bindings to json-schema Date: Mon, 3 Dec 2018 15:32:01 -0600 Message-Id: <20181203213223.16986-13-robh@kernel.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181203213223.16986-1-robh@kernel.org> References: <20181203213223.16986-1-robh@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Altera SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: Dinh Nguyen Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/altera.txt | 14 ------------- .../devicetree/bindings/arm/altera.yaml | 20 +++++++++++++++++++ 2 files changed, 20 insertions(+), 14 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/altera.txt create mode 100644 Documentation/devicetree/bindings/arm/altera.yaml -- 2.19.1 Acked-by: Dinh Nguyen diff --git a/Documentation/devicetree/bindings/arm/altera.txt b/Documentation/devicetree/bindings/arm/altera.txt deleted file mode 100644 index 558735aacca8..000000000000 --- a/Documentation/devicetree/bindings/arm/altera.txt +++ /dev/null @@ -1,14 +0,0 @@ -Altera's SoCFPGA platform device tree bindings ---------------------------------------------- - -Boards with Cyclone 5 SoC: -Required root node properties: -compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - -Boards with Arria 5 SoC: -Required root node properties: -compatible = "altr,socfpga-arria5", "altr,socfpga"; - -Boards with Arria 10 SoC: -Required root node properties: -compatible = "altr,socfpga-arria10", "altr,socfpga"; diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml new file mode 100644 index 000000000000..49e0362ddc11 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/altera.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera's SoCFPGA platform device tree bindings + +maintainers: + - Dinh Nguyen + +properties: + compatible: + items: + - enum: + - altr,socfpga-cyclone5 + - altr,socfpga-arria5 + - altr,socfpga-arria10 + - const: altr,socfpga +... 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[24.155.109.49]) by smtp.googlemail.com with ESMTPSA id c78sm8545501oig.30.2018.12.03.13.32.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Dec 2018 13:32:54 -0800 (PST) From: Rob Herring To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Sean Hudson , Frank Rowand , linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Grant Likely , Kumar Gala , arm@kernel.org, Mark Rutland , Heiko Stuebner , linux-rockchip@lists.infradead.org Subject: [PATCH v2 24/34] dt-bindings: arm: Convert Rockchip board/soc bindings to json-schema Date: Mon, 3 Dec 2018 15:32:13 -0600 Message-Id: <20181203213223.16986-25-robh@kernel.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181203213223.16986-1-robh@kernel.org> References: <20181203213223.16986-1-robh@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Rockchip SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: Heiko Stuebner Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/rockchip.txt | 240 ----------------- .../devicetree/bindings/arm/rockchip.yaml | 251 ++++++++++++++++++ 2 files changed, 251 insertions(+), 240 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/rockchip.txt create mode 100644 Documentation/devicetree/bindings/arm/rockchip.yaml -- 2.19.1 diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt deleted file mode 100644 index 0cc71236d639..000000000000 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ /dev/null @@ -1,240 +0,0 @@ -Rockchip platforms device tree bindings ---------------------------------------- - -- 96boards RK3399 Ficus (ROCK960 Enterprise Edition) - Required root node properties: - - compatible = "vamrs,ficus", "rockchip,rk3399"; - -- 96boards RK3399 Rock960 (ROCK960 Consumer Edition) - Required root node properties: - - compatible = "vamrs,rock960", "rockchip,rk3399"; - -- Amarula Vyasa RK3288 board - Required root node properties: - - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; - -- Asus Tinker board - Required root node properties: - - compatible = "asus,rk3288-tinker", "rockchip,rk3288"; - -- Asus Tinker board S - Required root node properties: - - compatible = "asus,rk3288-tinker-s", "rockchip,rk3288"; - -- Kylin RK3036 board: - Required root node properties: - - compatible = "rockchip,kylin-rk3036", "rockchip,rk3036"; - -- MarsBoard RK3066 board: - Required root node properties: - - compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; - -- bq Curie 2 tablet: - Required root node properties: - - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; - -- ChipSPARK Rayeager PX2 board: - Required root node properties: - - compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; - -- Radxa Rock board: - Required root node properties: - - compatible = "radxa,rock", "rockchip,rk3188"; - -- Radxa Rock2 Square board: - Required root node properties: - - compatible = "radxa,rock2-square", "rockchip,rk3288"; - -- Rikomagic MK808 v1 board: - Required root node properties: - - compatible = "rikomagic,mk808", "rockchip,rk3066a"; - -- Firefly Firefly-RK3288 board: - Required root node properties: - - compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; - or - - compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; - -- Firefly Firefly-RK3288 Reload board: - Required root node properties: - - compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; - -- Firefly Firefly-RK3399 board: - Required root node properties: - - compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; - -- Firefly roc-rk3328-cc board: - Required root node properties: - - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; - -- Firefly ROC-RK3399-PC board: - Required root node properties: - - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; - -- ChipSPARK PopMetal-RK3288 board: - Required root node properties: - - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; - -- Netxeon R89 board: - Required root node properties: - - compatible = "netxeon,r89", "rockchip,rk3288"; - -- GeekBuying GeekBox: - Required root node properties: - - compatible = "geekbuying,geekbox", "rockchip,rk3368"; - -- Google Bob (Asus Chromebook Flip C101PA): - Required root node properties: - compatible = "google,bob-rev13", "google,bob-rev12", - "google,bob-rev11", "google,bob-rev10", - "google,bob-rev9", "google,bob-rev8", - "google,bob-rev7", "google,bob-rev6", - "google,bob-rev5", "google,bob-rev4", - "google,bob", "google,gru", "rockchip,rk3399"; - -- Google Brain (dev-board): - Required root node properties: - - compatible = "google,veyron-brain-rev0", "google,veyron-brain", - "google,veyron", "rockchip,rk3288"; - -- Google Gru (dev-board): - Required root node properties: - - compatible = "google,gru-rev15", "google,gru-rev14", - "google,gru-rev13", "google,gru-rev12", - "google,gru-rev11", "google,gru-rev10", - "google,gru-rev9", "google,gru-rev8", - "google,gru-rev7", "google,gru-rev6", - "google,gru-rev5", "google,gru-rev4", - "google,gru-rev3", "google,gru-rev2", - "google,gru", "rockchip,rk3399"; - -- Google Jaq (Haier Chromebook 11 and more): - Required root node properties: - - compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4", - "google,veyron-jaq-rev3", "google,veyron-jaq-rev2", - "google,veyron-jaq-rev1", "google,veyron-jaq", - "google,veyron", "rockchip,rk3288"; - -- Google Jerry (Hisense Chromebook C11 and more): - Required root node properties: - - compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", - "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", - "google,veyron-jerry-rev3", "google,veyron-jerry", - "google,veyron", "rockchip,rk3288"; - -- Google Kevin (Samsung Chromebook Plus): - Required root node properties: - - compatible = "google,kevin-rev15", "google,kevin-rev14", - "google,kevin-rev13", "google,kevin-rev12", - "google,kevin-rev11", "google,kevin-rev10", - "google,kevin-rev9", "google,kevin-rev8", - "google,kevin-rev7", "google,kevin-rev6", - "google,kevin", "google,gru", "rockchip,rk3399"; - -- Google Mickey (Asus Chromebit CS10): - Required root node properties: - - compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", - "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", - "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", - "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", - "google,veyron-mickey-rev0", "google,veyron-mickey", - "google,veyron", "rockchip,rk3288"; - -- Google Minnie (Asus Chromebook Flip C100P): - Required root node properties: - - compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", - "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", - "google,veyron-minnie-rev0", "google,veyron-minnie", - "google,veyron", "rockchip,rk3288"; - -- Google Pinky (dev-board): - Required root node properties: - - compatible = "google,veyron-pinky-rev2", "google,veyron-pinky", - "google,veyron", "rockchip,rk3288"; - -- Google Speedy (Asus C201 Chromebook): - Required root node properties: - - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", - "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", - "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", - "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", - "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; - -- mqmaker MiQi: - Required root node properties: - - compatible = "mqmaker,miqi", "rockchip,rk3288"; - -- Phytec phyCORE-RK3288: Rapid Development Kit - Required root node properties: - - compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288"; - -- Pine64 Rock64 board: - Required root node properties: - - compatible = "pine64,rock64", "rockchip,rk3328"; - -- Pine64 RockPro64 board: - Required root node properties: - - compatible = "pine64,rockpro64", "rockchip,rk3399"; - -- Rockchip PX3 Evaluation board: - Required root node properties: - - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; - -- Rockchip PX5 Evaluation board: - Required root node properties: - - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; - -- Rockchip PX30 Evaluation board: - Required root node properties: - - compatible = "rockchip,px30-evb", "rockchip,px30"; - -- Rockchip RV1108 Evaluation board - Required root node properties: - - compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; - -- Rockchip RK3368 evb: - Required root node properties: - - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; - -- Rockchip R88 board: - Required root node properties: - - compatible = "rockchip,r88", "rockchip,rk3368"; - -- Rockchip RK3228 Evaluation board: - Required root node properties: - - compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; - -- Rockchip RK3229 Evaluation board: - - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - -- Rockchip RK3288 Fennec board: - Required root node properties: - - compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; - -- Rockchip RK3328 evb: - Required root node properties: - - compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; - -- Rockchip RK3399 evb: - Required root node properties: - - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; - -- Rockchip RK3399 Sapphire board standalone: - Required root node properties: - - compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; - -- Rockchip RK3399 Sapphire Excavator board: - Required root node properties: - - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; - -- Theobroma Systems RK3368-uQ7 Haikou Baseboard: - Required root node properties: - - compatible = "tsd,rk3368-uq7-haikou", "rockchip,rk3368"; - -- Theobroma Systems RK3399-Q7 Haikou Baseboard: - Required root node properties: - - compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399"; - -- Tronsmart Orion R68 Meta - Required root node properties: - - compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368"; diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml new file mode 100644 index 000000000000..3d30ec9adcd3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -0,0 +1,251 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/rockchip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip platforms device tree bindings + +maintainers: + - Beniamino Galvani + - Heiko Stuebner + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - amarula,vyasa-rk3288 + - asus,rk3288-tinker + - asus,rk3288-tinker-s + - radxa,rock2-square + - chipspark,popmetal-rk3288 + - netxeon,r89 + - firefly,firefly-rk3288 + - firefly,firefly-rk3288-beta + - firefly,firefly-rk3288-reload + - mqmaker,miqi + - rockchip,rk3288-fennec + - const: rockchip,rk3288 + + - description: Phytec phyCORE-RK3288 Rapid Development Kit + items: + - const: phytec,rk3288-pcm-947 + - const: phytec,rk3288-phycore-som + - const: rockchip,rk3288 + + - description: Google Mickey (Asus Chromebit CS10) + items: + - const: google,veyron-mickey-rev8 + - const: google,veyron-mickey-rev7 + - const: google,veyron-mickey-rev6 + - const: google,veyron-mickey-rev5 + - const: google,veyron-mickey-rev4 + - const: google,veyron-mickey-rev3 + - const: google,veyron-mickey-rev2 + - const: google,veyron-mickey-rev1 + - const: google,veyron-mickey-rev0 + - const: google,veyron-mickey + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Minnie (Asus Chromebook Flip C100P) + items: + - const: google,veyron-minnie-rev4 + - const: google,veyron-minnie-rev3 + - const: google,veyron-minnie-rev2 + - const: google,veyron-minnie-rev1 + - const: google,veyron-minnie-rev0 + - const: google,veyron-minnie + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Pinky (dev-board) + items: + - const: google,veyron-pinky-rev2 + - const: google,veyron-pinky + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Speedy (Asus C201 Chromebook) + items: + - const: google,veyron-speedy-rev9 + - const: google,veyron-speedy-rev8 + - const: google,veyron-speedy-rev7 + - const: google,veyron-speedy-rev6 + - const: google,veyron-speedy-rev5 + - const: google,veyron-speedy-rev4 + - const: google,veyron-speedy-rev3 + - const: google,veyron-speedy-rev2 + - const: google,veyron-speedy + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Jaq (Haier Chromebook 11 and more) + items: + - const: google,veyron-jaq-rev5 + - const: google,veyron-jaq-rev4 + - const: google,veyron-jaq-rev3 + - const: google,veyron-jaq-rev2 + - const: google,veyron-jaq-rev1 + - const: google,veyron-jaq + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Jerry (Hisense Chromebook C11 and more) + items: + - const: google,veyron-jerry-rev7 + - const: google,veyron-jerry-rev6 + - const: google,veyron-jerry-rev5 + - const: google,veyron-jerry-rev4 + - const: google,veyron-jerry-rev3 + - const: google,veyron-jerry + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Brain (dev-board) + items: + - const: google,veyron-brain-rev0 + - const: google,veyron-brain + - const: google,veyron + - const: rockchip,rk3288 + + - items: + - enum: + - rockchip,kylin-rk3036 + - const: rockchip,rk3036 + + - items: + - enum: + - haoyu,marsboard-rk3066 + - mundoreader,bq-curie2 + - chipspark,rayeager-px2 + - rikomagic,mk80 + - const: rockchip,rk3066a + + - items: + - enum: + - radxa,rock + - const: rockchip,rk3188 + + - items: + - const: rockchip,px3-evb + - const: rockchip,px3 + - const: rockchip,rk3188 + + - items: + - enum: + - firefly,roc-rk3328-cc + - pine64,rock64 + - rockchip,rk3328-evb + - const: rockchip,rk3328 + + - items: + - enum: + - geekbuying,geekbox + - rockchip,rk3368-evb-act8846 + - rockchip,r88 + - tsd,rk3368-uq7-haikou + - tronsmart,orion-r68-meta + - const: rockchip,rk3368 + + - items: + - enum: + - geekbuying,geekbox + - rockchip,rk3368-evb-act8846 + - rockchip,r88 + - tsd,rk3368-uq7-haikou + - tronsmart,orion-r68-meta + - const: rockchip,rk3368 + + - items: + - const: rockchip,px5-evb + - const: rockchip,px5 + - const: rockchip,rk3368 + + - items: + - enum: + - firefly,firefly-rk3399 + - firefly,roc-rk3399-pc + - pine64,rockpro64 + - rockchip,rk3399-evb + - rockchip,rk3399-sapphire + - rockchip,rk3399-sapphire-excavator + - tsd,rk3399-q7-haikou + - vamrs,ficus + - vamrs,rock960 # 96boards RK3399 Rock960 (ROCK960 Consumer Edition) + - const: rockchip,rk3399 + + - description: Google Bob (Asus Chromebook Flip C101PA) + items: + - const: google,bob-rev13 + - const: google,bob-rev12 + - const: google,bob-rev11 + - const: google,bob-rev10 + - const: google,bob-rev9 + - const: google,bob-rev8 + - const: google,bob-rev7 + - const: google,bob-rev6 + - const: google,bob-rev5 + - const: google,bob-rev4 + - const: google,bob + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Gru (dev-board) + items: + - const: google,gru-rev15 + - const: google,gru-rev14 + - const: google,gru-rev13 + - const: google,gru-rev12 + - const: google,gru-rev11 + - const: google,gru-rev10 + - const: google,gru-rev9 + - const: google,gru-rev8 + - const: google,gru-rev7 + - const: google,gru-rev6 + - const: google,gru-rev5 + - const: google,gru-rev4 + - const: google,gru-rev3 + - const: google,gru-rev2 + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Kevin (Samsung Chromebook Plus) + items: + - const: google,kevin-rev15 + - const: google,kevin-rev14 + - const: google,kevin-rev13 + - const: google,kevin-rev12 + - const: google,kevin-rev11 + - const: google,kevin-rev10 + - const: google,kevin-rev9 + - const: google,kevin-rev8 + - const: google,kevin-rev7 + - const: google,kevin-rev6 + - const: google,kevin + - const: google,gru + - const: rockchip,rk3399 + + - items: + - enum: + - rockchip,px30-evb + - const: rockchip,px30 + + - items: + - enum: + - rockchip,rv1108-evb + - const: rockchip,rv1108 + + - items: + - enum: + - rockchip,rk3228-evb + - const: rockchip,rk3228 + + - items: + - enum: + - rockchip,rk3229-evb + - const: rockchip,rk3229 +... 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[24.155.109.49]) by smtp.googlemail.com with ESMTPSA id c78sm8545501oig.30.2018.12.03.13.32.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Dec 2018 13:32:55 -0800 (PST) From: Rob Herring To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Sean Hudson , Frank Rowand , linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Grant Likely , Kumar Gala , arm@kernel.org, Mark Rutland , Simon Horman , Magnus Damm , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 25/34] dt-bindings: arm: renesas: Move 'renesas, prr' binding to its own doc Date: Mon, 3 Dec 2018 15:32:14 -0600 Message-Id: <20181203213223.16986-26-robh@kernel.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181203213223.16986-1-robh@kernel.org> References: <20181203213223.16986-1-robh@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation to convert board-level bindings to json-schema, move various misc SoC bindings out to their own file. Cc: Mark Rutland Cc: Simon Horman Cc: Magnus Damm Cc: devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/renesas,prr.txt | 20 +++++++++++++++++++ .../devicetree/bindings/arm/shmobile.txt | 18 ----------------- 2 files changed, 20 insertions(+), 18 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.txt -- 2.19.1 diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.txt b/Documentation/devicetree/bindings/arm/renesas,prr.txt new file mode 100644 index 000000000000..08e482e953ca --- /dev/null +++ b/Documentation/devicetree/bindings/arm/renesas,prr.txt @@ -0,0 +1,20 @@ +Renesas Product Register + +Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that +allows to retrieve SoC product and revision information. If present, a device +node for this register should be added. + +Required properties: + - compatible: Must be one of: + "renesas,prr" + "renesas,bsid" + - reg: Base address and length of the register block. + + +Examples +-------- + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 58c4256d37a3..5f18ce9cdbb8 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -149,21 +149,3 @@ Boards: compatible = "renesas,v3msk", "renesas,r8a77970" - Wheat (RTP0RC7792ASKB0000JE) compatible = "renesas,wheat", "renesas,r8a7792" - - -Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that -allows to retrieve SoC product and revision information. If present, a device -node for this register should be added. - -Required properties: - - compatible: Must be "renesas,prr" or "renesas,bsid" - - reg: Base address and length of the register block. - - -Examples --------- - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - };