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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/26] mps3-an547: Add missing user ahb interfaces Date: Wed, 2 Mar 2022 20:52:05 +0000 Message-Id: <20220302205230.2122390-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::330 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jimmy Brisson With these interfaces missing, TFM would delegate peripherals 0, 1, 2, 3 and 8, and qemu would ignore the delegation of interface 8, as it thought interface 4 was eth & USB. This patch corrects this behavior and allows TFM to delegate the eth & USB peripheral to NS mode. (The old QEMU behaviour was based on revision B of the AN547 appnote; revision C corrects this error in the documentation, and this commit brings QEMU in to line with how the FPGA image really behaves.) Signed-off-by: Jimmy Brisson Message-id: 20220210210227.3203883-1-jimmy.brisson@linaro.org Reviewed-by: Peter Maydell [PMM: added commit message note clarifying that the old behaviour was a docs issue, not because there were two different versions of the FPGA image] Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index f40e854dec7..e287ad4d06b 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -1078,6 +1078,10 @@ static void mps2tz_common_init(MachineState *machine) { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, + { /* port 4 USER AHB interface 0 */ }, + { /* port 5 USER AHB interface 1 */ }, + { /* port 6 USER AHB interface 2 */ }, + { /* port 7 USER AHB interface 3 */ }, { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } }, }, }, From patchwork Wed Mar 2 20:52:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547523 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp32011imq; Wed, 2 Mar 2022 13:02:15 -0800 (PST) X-Google-Smtp-Source: ABdhPJyGQLHIyaqCCJkJtMphMWd3FscLxG/LjAEwjDEiwTFcpH4XdNuaLBwrl/P/Jnu/LlToC8s1 X-Received: by 2002:a05:6808:e89:b0:2cf:cad3:e427 with SMTP id k9-20020a0568080e8900b002cfcad3e427mr1728817oil.20.1646254935345; Wed, 02 Mar 2022 13:02:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646254935; cv=none; d=google.com; s=arc-20160816; b=0CSOZJcNFkVh7xkr1jF1aJWWLsJgoFme0y59jwzT8UYRBFvtQuA2bHtNSxVja7ZUNh CXifAlS1NCbG4YhGwI/LVbX8u6+mpAHE9zNP9kkJUHV2+VFeaaz0rLvJVOxrLbogVL2t /q960Ggid1m2GvSfdCuab5slVVWqg2D8VPz4zexH6+moqcQDx2ocX4sefQYZXU1mmcO0 ASjHvt7ZNlt/ACUeK8YGDLZJo0cY/eSSlnMJebFfcguhunklDdRlqogzwoa45taNYKji AL+SH2XGaeNHLlju6VfL8NzQJcL3gigYg3E4qtT5jrbc5k23Nu3pkiZqYW8rCalu4Nrr SDAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FAP8anOWorF+Rmm2oJQLE0W4TFL2c2lUXLkzNZ7iIa4=; b=WMnxagvfRKQVrW0Mik42p/CmNMoyjgKWwn8vq+9fpW3o3DmgTrTF3t5tOIX8Ktj/Bu 39FaSxn1oMySjLbhoTHS9aT9/Jfpc1+MNdFASUSPBVF/+kQ4cNZUNujPM/Jwz/f4Pxe8 JZm7aW0w8sediisrZAf9otWeaEYqw7qnrlO1amQUUAMcSu6jhr6+3Dd53ranb5hOpBU0 OYt3CMMsIhmHa1QnIGg0MLAzjU6LehoDWwRY41YtolWlH14sfjR4oErAEIo40PTpSPTZ FvZoCHXHD7lWz5NbNfb9O1DdauuL95bEv/dsB5ent5rgrWKPUAFHWNE4p3J6qA0TMN8p JT+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oLPlWkwx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/26] hw/arm/mps2-tz.c: Update AN547 documentation URL Date: Wed, 2 Mar 2022 20:52:06 +0000 Message-Id: <20220302205230.2122390-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::333 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AN547 application note URL has changed: update our comment accordingly. (Rev B is still downloadable from the old URL, but there is a new Rev C of the document now.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-id: 20220221094144.426191-1-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index e287ad4d06b..4017392bf5a 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -32,7 +32,7 @@ * Application Note AN524: * https://developer.arm.com/documentation/dai0524/latest/ * Application Note AN547: - * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf + * https://developer.arm.com/documentation/dai0547/latest/ * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide * (ARM ECM0601256) for the details of some of the device layout: From patchwork Wed Mar 2 20:52:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547520 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp29332imq; Wed, 2 Mar 2022 12:58:25 -0800 (PST) X-Google-Smtp-Source: ABdhPJwc1pTMU0Vbh4yFR9tQtNbTdYeV2JsiOl9H/6dPsLM3+uF7ATy4uG9FE9/+/sbM2Motfoo0 X-Received: by 2002:a67:eac5:0:b0:31c:411:8f0a with SMTP id s5-20020a67eac5000000b0031c04118f0amr15187597vso.29.1646254705588; Wed, 02 Mar 2022 12:58:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646254705; cv=none; d=google.com; s=arc-20160816; b=OBH16aU5/oLD/EdPGEfNJ84UfJVkwK3YMUK+Z17IxaYJjY8nBglprTvOpF+TYrle2e aIZmMTVGbzpIZG/aRaFIuyQqO0KfMLGt8VUklZvC7SRUYeGvp4Uf/FLa8U+2Bd4ORn/K NPRFu0R/QKVuvOjRJB+9eJtFnCXuM3AROuKIfAAUABYcOGM48sWY2Yixrx0XEnrrFeQR 7nk65XyaEHAydo+2dVGaDBn8MSV8jYElUPGjkfB+Eq4mLOYY1tV6ZxhHa9V9Ww2rDhHD R3cCfMBj6NjUc5jMNzbDHTQGz6ykXzlPJHkwGHcIBfYozDLpCyXTCgXIh7Q8FS/0KA9A jtrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WQH43RYLvQDXPun3Ra4uvCKAv6ejoTJuD3KqLrDM/Eg=; b=mdlo4TfhLqtkozpp9NZ8CuAOYGYXMyfGQW/S65D47Ko8EQGaB4qRxLAZ1oAERzKxhY gF06jt17YEPftt3lsf2iBmN1SoFEWzsi5ADnXSg3IKWwruvdx8uu8Ft/7vz1+ss6of7p Uht2u+LAzuPLlqC3sney3zFDF7KOAmZGi/gdee1Rg04wvVhgPHD5W34SrfcFdHjhaYSb CYRaL0+YicO9NBHkqqpsUDnxsdfGA709TFibQamPeMSRc5o+S4rzy/3lWwn66HtyyIAy NFlPTtiwtZu/e/c76Jg9UQmtn7d8oirtmlCZIZ9HCYzq1cR03JD5dljeSKjImIc71oEZ zC3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E6+bFSCK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/26] hw/input/tsc210x: Don't abort on bad SPI word widths Date: Wed, 2 Mar 2022 20:52:07 +0000 Message-Id: <20220302205230.2122390-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::335 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The tsc210x doesn't support anything other than 16-bit reads on the SPI bus, but the guest can program the SPI controller to attempt them anyway. If this happens, don't abort QEMU, just log this as a guest error. This fixes our machine_arm_n8x0.py:N8x0Machine.test_n800 acceptance test, which hits this assertion. The reason we hit the assertion is because the guest kernel thinks there is a TSC2005 on this SPI bus address, not a TSC210x. (The n810 *does* have a TSC2005 at this address.) The TSC2005 supports the 24-bit accesses which the guest driver makes, and the TSC210x does not (that is, our TSC210x emulation is not missing support for a word width the hardware can handle). It's not clear whether the problem here is that the guest kernel incorrectly thinks the n800 has the same device at this SPI bus address as the n810, or that QEMU's n810 board model doesn't get the SPI devices right. At this late date there no longer appears to be any reliable information on the web about the hardware behaviour, but I am inclined to think this is a guest kernel bug. In any case, we prefer not to abort QEMU for guest-triggerable conditions, so logging the error is the right thing to do. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/736 Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Message-id: 20220221140750.514557-1-peter.maydell@linaro.org --- hw/input/tsc210x.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c index b0d5c2dd748..df7313db5d7 100644 --- a/hw/input/tsc210x.c +++ b/hw/input/tsc210x.c @@ -24,6 +24,7 @@ #include "hw/hw.h" #include "audio/audio.h" #include "qemu/timer.h" +#include "qemu/log.h" #include "sysemu/reset.h" #include "ui/console.h" #include "hw/arm/omap.h" /* For I2SCodec */ @@ -910,8 +911,11 @@ uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len) TSC210xState *s = opaque; uint32_t ret = 0; - if (len != 16) - hw_error("%s: FIXME: bad SPI word width %i\n", __func__, len); + if (len != 16) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad SPI word width %i\n", __func__, len); + return 0; + } /* TODO: sequential reads etc - how do we make sure the host doesn't * unintentionally read out a conversion result from a register while From patchwork Wed Mar 2 20:52:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547517 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp27048imq; Wed, 2 Mar 2022 12:54:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJzI5ysY8EudEMNHFbaT1UY6nCpfxkbsDGrKHnaw4J1a90fMzV8tjmfY+AYGHXaWo/Qj4OHb X-Received: by 2002:a05:6808:1246:b0:2c9:efa5:7209 with SMTP id o6-20020a056808124600b002c9efa57209mr1614000oiv.62.1646254473703; Wed, 02 Mar 2022 12:54:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646254473; cv=none; d=google.com; s=arc-20160816; b=VyuW9HTKlhVV7oJQipjZughG8+2YfxgNNiqiI3jv+f27/gbUVr/PMAYvZMpH9sj/Sd gFsx6Leu4THDJmNSxThsVkkhdJsZ19wfPglWTUI1tCvgMFnms6l5TkJQ8Yh8k7FNKYkn 2UoNKb6hBdMJFMN7dwttaRRlP3onkIS1tASTHpDUTvZZoD4ddMXgTm0MMMbvoqVTSe81 tGUcYl0+UjZwke2muXntP+b1as9uQhKxHxe+PK3IMkO3jI0pO+0wkbzPTzHUz+zlvK4K nrERZc36cQtdJSb7HxocQWnfKtXCwIU5obQSRPNDHh9ZlwLAR9t14RT2SIgWLu+5n6Pk lW8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1l2NOv9OwvipekROpdxjCaOFOo+1t/8TzNdjQpxDeL4=; b=uHFKNBeFylVTYQAmltgci1XDJ05Q9VMO7yK6CXlK6KwBxuVwvUfyCXZ0Wvr0Tmtwd8 QjAy+13a67u3eC3TjCzFA9ictHjGNTwL3srw+wkGSGR4000W0Q9+ighxoar7AIuAFn/P hkcdXQxl2JTDzhfFUf+QTepVgZj6iVmFoj34LMopjl9PvcFuk3tl1iNRHlF91qXRLn9o gfjSKhVSmdezzqZdT2eHBzqs7kHcHrH85k10qrYmG+xG0Cm2awJdd0BlBLXiY8mYHOp/ wV2GlZvwxCO9Y77Hur2OBHsYzgkSSN1em30noG9XB/dSkb6maFWCCPoPKl1yP7H1vUyo qlcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XRPSAMbj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/26] hw/i2c: flatten pca954x mux device Date: Wed, 2 Mar 2022 20:52:08 +0000 Message-Id: <20220302205230.2122390-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32f (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Patrick Venture Previously this device created N subdevices which each owned an i2c bus. Now this device simply owns the N i2c busses directly. Tested: Verified devices behind mux are still accessible via qmp and i2c from within an arm32 SoC. Reviewed-by: Hao Wu Signed-off-by: Patrick Venture Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-id: 20220202164533.1283668-1-venture@google.com Signed-off-by: Peter Maydell --- hw/i2c/i2c_mux_pca954x.c | 77 +++++++--------------------------------- 1 file changed, 13 insertions(+), 64 deletions(-) diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw/i2c/i2c_mux_pca954x.c index 847c59921cf..a9517b612ae 100644 --- a/hw/i2c/i2c_mux_pca954x.c +++ b/hw/i2c/i2c_mux_pca954x.c @@ -30,24 +30,6 @@ #define PCA9548_CHANNEL_COUNT 8 #define PCA9546_CHANNEL_COUNT 4 -/* - * struct Pca954xChannel - The i2c mux device will have N of these states - * that own the i2c channel bus. - * @bus: The owned channel bus. - * @enabled: Is this channel active? - */ -typedef struct Pca954xChannel { - SysBusDevice parent; - - I2CBus *bus; - - bool enabled; -} Pca954xChannel; - -#define TYPE_PCA954X_CHANNEL "pca954x-channel" -#define PCA954X_CHANNEL(obj) \ - OBJECT_CHECK(Pca954xChannel, (obj), TYPE_PCA954X_CHANNEL) - /* * struct Pca954xState - The pca954x state object. * @control: The value written to the mux control. @@ -59,8 +41,8 @@ typedef struct Pca954xState { uint8_t control; - /* The channel i2c buses. */ - Pca954xChannel channel[PCA9548_CHANNEL_COUNT]; + bool enabled[PCA9548_CHANNEL_COUNT]; + I2CBus *bus[PCA9548_CHANNEL_COUNT]; } Pca954xState; /* @@ -98,11 +80,11 @@ static bool pca954x_match(I2CSlave *candidate, uint8_t address, } for (i = 0; i < mc->nchans; i++) { - if (!mux->channel[i].enabled) { + if (!mux->enabled[i]) { continue; } - if (i2c_scan_bus(mux->channel[i].bus, address, broadcast, + if (i2c_scan_bus(mux->bus[i], address, broadcast, current_devs)) { if (!broadcast) { return true; @@ -125,9 +107,9 @@ static void pca954x_enable_channel(Pca954xState *s, uint8_t enable_mask) */ for (i = 0; i < mc->nchans; i++) { if (enable_mask & (1 << i)) { - s->channel[i].enabled = true; + s->enabled[i] = true; } else { - s->channel[i].enabled = false; + s->enabled[i] = false; } } } @@ -184,23 +166,7 @@ I2CBus *pca954x_i2c_get_bus(I2CSlave *mux, uint8_t channel) Pca954xState *pca954x = PCA954X(mux); g_assert(channel < pc->nchans); - return I2C_BUS(qdev_get_child_bus(DEVICE(&pca954x->channel[channel]), - "i2c-bus")); -} - -static void pca954x_channel_init(Object *obj) -{ - Pca954xChannel *s = PCA954X_CHANNEL(obj); - s->bus = i2c_init_bus(DEVICE(s), "i2c-bus"); - - /* Start all channels as disabled. */ - s->enabled = false; -} - -static void pca954x_channel_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - dc->desc = "Pca954x Channel"; + return pca954x->bus[channel]; } static void pca9546_class_init(ObjectClass *klass, void *data) @@ -215,28 +181,19 @@ static void pca9548_class_init(ObjectClass *klass, void *data) s->nchans = PCA9548_CHANNEL_COUNT; } -static void pca954x_realize(DeviceState *dev, Error **errp) -{ - Pca954xState *s = PCA954X(dev); - Pca954xClass *c = PCA954X_GET_CLASS(s); - int i; - - /* SMBus modules. Cannot fail. */ - for (i = 0; i < c->nchans; i++) { - sysbus_realize(SYS_BUS_DEVICE(&s->channel[i]), &error_abort); - } -} - static void pca954x_init(Object *obj) { Pca954xState *s = PCA954X(obj); Pca954xClass *c = PCA954X_GET_CLASS(obj); int i; - /* Only initialize the children we expect. */ + /* SMBus modules. Cannot fail. */ for (i = 0; i < c->nchans; i++) { - object_initialize_child(obj, "channel[*]", &s->channel[i], - TYPE_PCA954X_CHANNEL); + g_autofree gchar *bus_name = g_strdup_printf("i2c.%d", i); + + /* start all channels as disabled. */ + s->enabled[i] = false; + s->bus[i] = i2c_init_bus(DEVICE(s), bus_name); } } @@ -252,7 +209,6 @@ static void pca954x_class_init(ObjectClass *klass, void *data) rc->phases.enter = pca954x_enter_reset; dc->desc = "Pca954x i2c-mux"; - dc->realize = pca954x_realize; k->write_data = pca954x_write_data; k->receive_byte = pca954x_read_byte; @@ -278,13 +234,6 @@ static const TypeInfo pca954x_info[] = { .parent = TYPE_PCA954X, .class_init = pca9548_class_init, }, - { - .name = TYPE_PCA954X_CHANNEL, - .parent = TYPE_SYS_BUS_DEVICE, - .class_init = pca954x_channel_class_init, - .instance_size = sizeof(Pca954xChannel), - .instance_init = pca954x_channel_init, - } }; DEFINE_TYPES(pca954x_info) From patchwork Wed Mar 2 20:52:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547518 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp29086imq; Wed, 2 Mar 2022 12:58:02 -0800 (PST) X-Google-Smtp-Source: ABdhPJyee0P5HNs311g13WomUsYaXe5dmLVyOgC0O6PE+AfQYpc1w1eLL4Parh9cYlXRlINj2JIP X-Received: by 2002:a25:1503:0:b0:628:3404:412c with SMTP id 3-20020a251503000000b006283404412cmr17114232ybv.15.1646254682468; Wed, 02 Mar 2022 12:58:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646254682; cv=none; d=google.com; s=arc-20160816; b=z/EWszfPJppuAt5PPsX5/oivTy48BQumUAsnW7Ypx2C5CgNCOYnhIuMi9vp0BJtjnt V7ejePmVCRDi8qumyGlFAFKt1WY4MEgGxQxIV8v+Kzt6Pdo58i51KvQMNGe0+auxWHEn ub3q1i7wdKR+EVaBBEUTitubjxd8y+1Fsxg/9hTvkGusNzN8s4qQxUHWxMN+X1cBSPkr 95Na6lYXB9KUJ2IW9gq7CqgVYwB+y13qtIfe+aBtFWR6hE6ORRQ5ocY7Poxwpp3+uBrM NMOHo+dQ5z5TT2OxZ7RPg9yRJcvX+MpRY6h2QAUwP6o8ac/rygrkV/G96tWBxUZQrxpD HgOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9/1gVGYDHfIM2iOzA0/RLao08BBx/4vLNzoqpMeDyBE=; b=gtPAmc+R3U3SpSFYypxa8pJrIM/I8Swj5cD9N2zq6l8E0NuNEoqqi4kqT7qDfb6HGX vhOaXmKaC+nBmUN5vlyan7GUE+izFT8PrK1O0yhhhw0cyQCacGGXRJYMCvTF7mtbeCU/ dAvuuaiC9FQeA3lFEn/KoToWJp/Vxhvst7itDQl2SGCHqiZv5yrpkimRMv01IUwMw4Pu JrFABEKQ1YfBqAeZUWd5uou+fLsRCfLpnHWZ8siCMNcuFXNR9arB3Tjblr1Gw34Aby/2 Dykucr7bhnCnbzfxZhYKw5Y9n2bAzQKZXh1WFxR2fbgE4HTLU3Pclm8mGv0rv4DUxbvm c0nA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K8otbdbv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/26] target/arm: Support PSCI 1.1 and SMCCC 1.0 Date: Wed, 2 Mar 2022 20:52:09 +0000 Message-Id: <20220302205230.2122390-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::434 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Akihiko Odaki Support the latest PSCI on TCG and HVF. A 64-bit function called from AArch32 now returns NOT_SUPPORTED, which is necessary to adhere to SMC Calling Convention 1.0. It is still not compliant with SMCCC 1.3 since they do not implement mandatory functions. Signed-off-by: Akihiko Odaki Message-id: 20220213035753.34577-1-akihiko.odaki@gmail.com Reviewed-by: Peter Maydell [PMM: update MISMATCH_CHECK checks on PSCI_VERSION macros to match] Signed-off-by: Peter Maydell --- target/arm/kvm-consts.h | 13 +++++++++---- hw/arm/boot.c | 12 +++++++++--- target/arm/cpu.c | 5 +++-- target/arm/hvf/hvf.c | 27 ++++++++++++++++++++++++++- target/arm/kvm64.c | 2 +- target/arm/psci.c | 35 ++++++++++++++++++++++++++++++++--- 6 files changed, 80 insertions(+), 14 deletions(-) diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index 580f1c1fee0..e770921ddc2 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -77,6 +77,8 @@ MISMATCH_CHECK(QEMU_PSCI_0_1_FN_MIGRATE, KVM_PSCI_FN_MIGRATE); #define QEMU_PSCI_0_2_FN64_AFFINITY_INFO QEMU_PSCI_0_2_FN64(4) #define QEMU_PSCI_0_2_FN64_MIGRATE QEMU_PSCI_0_2_FN64(5) +#define QEMU_PSCI_1_0_FN_PSCI_FEATURES QEMU_PSCI_0_2_FN(10) + MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_SUSPEND, PSCI_0_2_FN_CPU_SUSPEND); MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_OFF, PSCI_0_2_FN_CPU_OFF); MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_ON, PSCI_0_2_FN_CPU_ON); @@ -84,18 +86,21 @@ MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE, PSCI_0_2_FN_MIGRATE); MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_SUSPEND, PSCI_0_2_FN64_CPU_SUSPEND); MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_ON, PSCI_0_2_FN64_CPU_ON); MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_MIGRATE, PSCI_0_2_FN64_MIGRATE); +MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_FN_PSCI_FEATURES); /* PSCI v0.2 return values used by TCG emulation of PSCI */ /* No Trusted OS migration to worry about when offlining CPUs */ #define QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED 2 -/* We implement version 0.2 only */ -#define QEMU_PSCI_0_2_RET_VERSION_0_2 2 +#define QEMU_PSCI_VERSION_0_1 0x00001 +#define QEMU_PSCI_VERSION_0_2 0x00002 +#define QEMU_PSCI_VERSION_1_1 0x10001 MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP); -MISMATCH_CHECK(QEMU_PSCI_0_2_RET_VERSION_0_2, - (PSCI_VERSION_MAJOR(0) | PSCI_VERSION_MINOR(2))); +/* We don't bother to check every possible version value */ +MISMATCH_CHECK(QEMU_PSCI_VERSION_0_2, PSCI_VERSION(0, 2)); +MISMATCH_CHECK(QEMU_PSCI_VERSION_1_1, PSCI_VERSION(1, 1)); /* PSCI return values (inclusive of all PSCI versions) */ #define QEMU_PSCI_RET_SUCCESS 0 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index b1e95978f26..0eeef94ceb5 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -488,9 +488,15 @@ static void fdt_add_psci_node(void *fdt) } qemu_fdt_add_subnode(fdt, "/psci"); - if (armcpu->psci_version == 2) { - const char comp[] = "arm,psci-0.2\0arm,psci"; - qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); + if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2 || + armcpu->psci_version == QEMU_PSCI_VERSION_1_1) { + if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2) { + const char comp[] = "arm,psci-0.2\0arm,psci"; + qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); + } else { + const char comp[] = "arm,psci-1.0\0arm,psci-0.2\0arm,psci"; + qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); + } cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c085dc10ee7..dd64d178e2e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1110,11 +1110,12 @@ static void arm_cpu_initfn(Object *obj) * picky DTB consumer will also provide a helpful error message. */ cpu->dtb_compatible = "qemu,unknown"; - cpu->psci_version = 1; /* By default assume PSCI v0.1 */ + cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; if (tcg_enabled() || hvf_enabled()) { - cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */ + /* TCG and HVF implement PSCI 1.1 */ + cpu->psci_version = QEMU_PSCI_VERSION_1_1; } } diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 4d4ddab348a..8c34f86792e 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -678,7 +678,7 @@ static bool hvf_handle_psci_call(CPUState *cpu) switch (param[0]) { case QEMU_PSCI_0_2_FN_PSCI_VERSION: - ret = QEMU_PSCI_0_2_RET_VERSION_0_2; + ret = QEMU_PSCI_VERSION_1_1; break; case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ @@ -746,6 +746,31 @@ static bool hvf_handle_psci_call(CPUState *cpu) case QEMU_PSCI_0_2_FN_MIGRATE: ret = QEMU_PSCI_RET_NOT_SUPPORTED; break; + case QEMU_PSCI_1_0_FN_PSCI_FEATURES: + switch (param[1]) { + case QEMU_PSCI_0_2_FN_PSCI_VERSION: + case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: + case QEMU_PSCI_0_2_FN_AFFINITY_INFO: + case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: + case QEMU_PSCI_0_2_FN_SYSTEM_RESET: + case QEMU_PSCI_0_2_FN_SYSTEM_OFF: + case QEMU_PSCI_0_1_FN_CPU_ON: + case QEMU_PSCI_0_2_FN_CPU_ON: + case QEMU_PSCI_0_2_FN64_CPU_ON: + case QEMU_PSCI_0_1_FN_CPU_OFF: + case QEMU_PSCI_0_2_FN_CPU_OFF: + case QEMU_PSCI_0_1_FN_CPU_SUSPEND: + case QEMU_PSCI_0_2_FN_CPU_SUSPEND: + case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: + case QEMU_PSCI_1_0_FN_PSCI_FEATURES: + ret = 0; + break; + case QEMU_PSCI_0_1_FN_MIGRATE: + case QEMU_PSCI_0_2_FN_MIGRATE: + default: + ret = QEMU_PSCI_RET_NOT_SUPPORTED; + } + break; default: return false; } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 71c3ca69717..64d48bfb19d 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -864,7 +864,7 @@ int kvm_arch_init_vcpu(CPUState *cs) cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF; } if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { - cpu->psci_version = 2; + cpu->psci_version = QEMU_PSCI_VERSION_0_2; cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2; } if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { diff --git a/target/arm/psci.c b/target/arm/psci.c index b279c0b9a45..6c1239bb968 100644 --- a/target/arm/psci.c +++ b/target/arm/psci.c @@ -57,7 +57,7 @@ void arm_handle_psci_call(ARMCPU *cpu) { /* * This function partially implements the logic for dispatching Power State - * Coordination Interface (PSCI) calls (as described in ARM DEN 0022B.b), + * Coordination Interface (PSCI) calls (as described in ARM DEN 0022D.b), * to the extent required for bringing up and taking down secondary cores, * and for handling reset and poweroff requests. * Additional information about the calling convention used is available in @@ -80,7 +80,7 @@ void arm_handle_psci_call(ARMCPU *cpu) } if ((param[0] & QEMU_PSCI_0_2_64BIT) && !is_a64(env)) { - ret = QEMU_PSCI_RET_INVALID_PARAMS; + ret = QEMU_PSCI_RET_NOT_SUPPORTED; goto err; } @@ -89,7 +89,7 @@ void arm_handle_psci_call(ARMCPU *cpu) ARMCPU *target_cpu; case QEMU_PSCI_0_2_FN_PSCI_VERSION: - ret = QEMU_PSCI_0_2_RET_VERSION_0_2; + ret = QEMU_PSCI_VERSION_1_1; break; case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ @@ -170,6 +170,35 @@ void arm_handle_psci_call(ARMCPU *cpu) } helper_wfi(env, 4); break; + case QEMU_PSCI_1_0_FN_PSCI_FEATURES: + switch (param[1]) { + case QEMU_PSCI_0_2_FN_PSCI_VERSION: + case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: + case QEMU_PSCI_0_2_FN_AFFINITY_INFO: + case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: + case QEMU_PSCI_0_2_FN_SYSTEM_RESET: + case QEMU_PSCI_0_2_FN_SYSTEM_OFF: + case QEMU_PSCI_0_1_FN_CPU_ON: + case QEMU_PSCI_0_2_FN_CPU_ON: + case QEMU_PSCI_0_2_FN64_CPU_ON: + case QEMU_PSCI_0_1_FN_CPU_OFF: + case QEMU_PSCI_0_2_FN_CPU_OFF: + case QEMU_PSCI_0_1_FN_CPU_SUSPEND: + case QEMU_PSCI_0_2_FN_CPU_SUSPEND: + case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: + case QEMU_PSCI_1_0_FN_PSCI_FEATURES: + if (!(param[1] & QEMU_PSCI_0_2_64BIT) || is_a64(env)) { + ret = 0; + break; + } + /* fallthrough */ + case QEMU_PSCI_0_1_FN_MIGRATE: + case QEMU_PSCI_0_2_FN_MIGRATE: + default: + ret = QEMU_PSCI_RET_NOT_SUPPORTED; + break; + } + break; case QEMU_PSCI_0_1_FN_MIGRATE: case QEMU_PSCI_0_2_FN_MIGRATE: default: From patchwork Wed Mar 2 20:52:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547528 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp36564imq; Wed, 2 Mar 2022 13:08:01 -0800 (PST) X-Google-Smtp-Source: ABdhPJxSQcDBeDhi5QptBKx3qfhSELZghFqPnCyknj6x4tj9rdVQzTJqr9e+kMzw5YltFzVD2F4q X-Received: by 2002:a25:424e:0:b0:628:7c46:3e3e with SMTP id p75-20020a25424e000000b006287c463e3emr9735195yba.166.1646255281704; Wed, 02 Mar 2022 13:08:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646255281; cv=none; d=google.com; s=arc-20160816; b=WhZfuxSuPIZpQV6ibYBM05Md+3BCA2gGQGvU1EEhchWomwpj9Nr9LXaQ6rG8IR/ZIb 0mM+qEgAgo88IiIMxJtwQsCV4gmKzq5Qs5bdES1P3U4GWGer9JeJhml+90kNUsYaqEnx HUYgQRsqXHGmOGy9YMNJWzHKNFGqgrfwhEcxIMmQW3zoFXMENQFDdpvio29zHdbgoLL+ vWt2X7JNE6ybH8j8HWFlRg7kcEut7vDOaQmr3NchSutnB4a6NH1qb7QSYJBXmG5H4i4a y/fVLdnQSyslP9dABZvGkTxhAw8dHGsVnJHBsP27D0IAwIOBzLE+qdm5DNZ/v+dHiTtg SlPQ== ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/26] target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv() Date: Wed, 2 Mar 2022 20:52:10 +0000 Message-Id: <20220302205230.2122390-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::429 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Wentao_Liang handle_simd_shift_fpint_conv() was accidentally freeing the TCG temporary tcg_fpstatus too early, before the last use of it. Move the free down to where it belongs. Signed-off-by: Wentao_Liang Reviewed-by: Richard Henderson [PMM: cleaned up commit message] Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5a1df25f91e..d1a59fad9c2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9045,9 +9045,9 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, } } - tcg_temp_free_ptr(tcg_fpstatus); tcg_temp_free_i32(tcg_shift); gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + tcg_temp_free_ptr(tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); } From patchwork Wed Mar 2 20:52:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547522 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp31402imq; Wed, 2 Mar 2022 13:01:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJzmuIgIBOMaoqPDChBqOcn+ihXzGEs3CanuXetsl7dHNQ2jSvlQe52TNNXzo/ed7UAV4L5N X-Received: by 2002:a37:f903:0:b0:648:ca74:b7dc with SMTP id l3-20020a37f903000000b00648ca74b7dcmr17148766qkj.666.1646254893533; Wed, 02 Mar 2022 13:01:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646254893; cv=none; d=google.com; s=arc-20160816; b=AxzDW2ot2angZYPq8c+sDVMPCRcs4T9sj1sHjZZRzToG7sm04xtwASgA5w3NZy7vOM dK8r9/LXaoo7PB3mxkBm8ZUrmEyq/Dx1Bsk9NgNHo2Uc87H5KSE2hFSvQQ89VALfZJdm MINLmeGDlI0Uj9vJskM7boV8zxFb4WKL+qhIUVDxZfNdfPxvMDHmRy9c36OsHaFK8Ps5 CFztaoiVUlpAFoWtU8278Ja74Kzclo19PsY6pUtqUSX8eIV8Rtj/HxuROCVtOz/3LfJs ctA2KobQot9ILzgZ3OqG2UV2S9CgkciorU+p5hpKDlYlPa8aX9zEgwwy48/cwSYPiUZH pvqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7Iahj6+8k9bQAnoYUUi7Icju5K12EU5059U2BQiNTcI=; b=oxEcWz9KlnjIVJA53woGWA5UAHhdIntgw6xqAb2k6f8hd7xX8QWyi9928PaXZBmrlH 5TKmpjjZlLdgX29Dwn39+rH/FDwoxhsT0Vv/n20ol5spys1wN0fsZvKnNJExgDIh+8zE Qc2y2ONIjsPk2SS5+GbZGt7pqyxoyVYW9y9M16vMtxhJ/P+IOvLevdHs06tnIKT50Jxr PIb82bhFrXrX9SCetEb8eu2mVqA0I4j8Hws7f7sWbqnKvAT1mpfub416rrLN7QkEK41l itEInkt1WLV3s34UOVN96UWP76mVCEGuwKNWEObInfCs61hJuFGYIRA/764QCE/aad0j XR7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YGXayhGR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/26] tests/qtest: add qtests for npcm7xx sdhci Date: Wed, 2 Mar 2022 20:52:11 +0000 Message-Id: <20220302205230.2122390-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::430 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Shengtan Mao Reviewed-by: Hao Wu Reviewed-by: Chris Rauer Signed-off-by: Shengtan Mao Signed-off-by: Patrick Venture Message-id: 20220225174451.192304-1-wuhaotsh@google.com Signed-off-by: Peter Maydell --- tests/qtest/npcm7xx_sdhci-test.c | 215 +++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 216 insertions(+) create mode 100644 tests/qtest/npcm7xx_sdhci-test.c diff --git a/tests/qtest/npcm7xx_sdhci-test.c b/tests/qtest/npcm7xx_sdhci-test.c new file mode 100644 index 00000000000..c1f496fb29b --- /dev/null +++ b/tests/qtest/npcm7xx_sdhci-test.c @@ -0,0 +1,215 @@ +/* + * QTests for NPCM7xx SD-3.0 / MMC-4.51 Host Controller + * + * Copyright (c) 2022 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "hw/sd/npcm7xx_sdhci.h" + +#include "libqos/libqtest.h" +#include "libqtest-single.h" +#include "libqos/sdhci-cmd.h" + +#define NPCM7XX_REG_SIZE 0x100 +#define NPCM7XX_MMC_BA 0xF0842000 +#define NPCM7XX_BLK_SIZE 512 +#define NPCM7XX_TEST_IMAGE_SIZE (1 << 30) + +char *sd_path; + +static QTestState *setup_sd_card(void) +{ + QTestState *qts = qtest_initf( + "-machine kudo-bmc " + "-device sd-card,drive=drive0 " + "-drive id=drive0,if=none,file=%s,format=raw,auto-read-only=off", + sd_path); + + qtest_writew(qts, NPCM7XX_MMC_BA + SDHC_SWRST, SDHC_RESET_ALL); + qtest_writew(qts, NPCM7XX_MMC_BA + SDHC_CLKCON, + SDHC_CLOCK_SDCLK_EN | SDHC_CLOCK_INT_STABLE | + SDHC_CLOCK_INT_EN); + sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_APP_CMD); + sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x41200000, 0, (41 << 8)); + sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_ALL_SEND_CID); + sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_SEND_RELATIVE_ADDR); + sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x45670000, 0, + SDHC_SELECT_DESELECT_CARD); + + return qts; +} + +static void write_sdread(QTestState *qts, const char *msg) +{ + int fd, ret; + size_t len = strlen(msg); + char *rmsg = g_malloc(len); + + /* write message to sd */ + fd = open(sd_path, O_WRONLY); + g_assert(fd >= 0); + ret = write(fd, msg, len); + close(fd); + g_assert(ret == len); + + /* read message using sdhci */ + ret = sdhci_read_cmd(qts, NPCM7XX_MMC_BA, rmsg, len); + g_assert(ret == len); + g_assert(!memcmp(rmsg, msg, len)); + + g_free(rmsg); +} + +/* Check MMC can read values from sd */ +static void test_read_sd(void) +{ + QTestState *qts = setup_sd_card(); + + write_sdread(qts, "hello world"); + write_sdread(qts, "goodbye"); + + qtest_quit(qts); +} + +static void sdwrite_read(QTestState *qts, const char *msg) +{ + int fd, ret; + size_t len = strlen(msg); + char *rmsg = g_malloc(len); + + /* write message using sdhci */ + sdhci_write_cmd(qts, NPCM7XX_MMC_BA, msg, len, NPCM7XX_BLK_SIZE); + + /* read message from sd */ + fd = open(sd_path, O_RDONLY); + g_assert(fd >= 0); + ret = read(fd, rmsg, len); + close(fd); + g_assert(ret == len); + + g_assert(!memcmp(rmsg, msg, len)); + + g_free(rmsg); +} + +/* Check MMC can write values to sd */ +static void test_write_sd(void) +{ + QTestState *qts = setup_sd_card(); + + sdwrite_read(qts, "hello world"); + sdwrite_read(qts, "goodbye"); + + qtest_quit(qts); +} + +/* Check SDHCI has correct default values. */ +static void test_reset(void) +{ + QTestState *qts = qtest_init("-machine kudo-bmc"); + uint64_t addr = NPCM7XX_MMC_BA; + uint64_t end_addr = addr + NPCM7XX_REG_SIZE; + uint16_t prstvals_resets[] = {NPCM7XX_PRSTVALS_0_RESET, + NPCM7XX_PRSTVALS_1_RESET, + 0, + NPCM7XX_PRSTVALS_3_RESET, + 0, + 0}; + int i; + uint32_t mask; + + while (addr < end_addr) { + switch (addr - NPCM7XX_MMC_BA) { + case SDHC_PRNSTS: + /* + * ignores bits 20 to 24: they are changed when reading registers + */ + mask = 0x1f00000; + g_assert_cmphex(qtest_readl(qts, addr) | mask, ==, + NPCM7XX_PRSNTS_RESET | mask); + addr += 4; + break; + case SDHC_BLKGAP: + g_assert_cmphex(qtest_readb(qts, addr), ==, NPCM7XX_BLKGAP_RESET); + addr += 1; + break; + case SDHC_CAPAB: + g_assert_cmphex(qtest_readq(qts, addr), ==, NPCM7XX_CAPAB_RESET); + addr += 8; + break; + case SDHC_MAXCURR: + g_assert_cmphex(qtest_readq(qts, addr), ==, NPCM7XX_MAXCURR_RESET); + addr += 8; + break; + case SDHC_HCVER: + g_assert_cmphex(qtest_readw(qts, addr), ==, NPCM7XX_HCVER_RESET); + addr += 2; + break; + case NPCM7XX_PRSTVALS: + for (i = 0; i < NPCM7XX_PRSTVALS_SIZE; ++i) { + g_assert_cmphex(qtest_readw(qts, addr + 2 * i), ==, + prstvals_resets[i]); + } + addr += NPCM7XX_PRSTVALS_SIZE * 2; + break; + default: + g_assert_cmphex(qtest_readb(qts, addr), ==, 0); + addr += 1; + } + } + + qtest_quit(qts); +} + +static void drive_destroy(void) +{ + unlink(sd_path); + g_free(sd_path); +} + +static void drive_create(void) +{ + int fd, ret; + GError *error = NULL; + + /* Create a temporary raw image */ + fd = g_file_open_tmp("sdhci_XXXXXX", &sd_path, &error); + if (fd == -1) { + fprintf(stderr, "unable to create sdhci file: %s\n", error->message); + g_error_free(error); + } + g_assert(sd_path != NULL); + + ret = ftruncate(fd, NPCM7XX_TEST_IMAGE_SIZE); + g_assert_cmpint(ret, ==, 0); + g_message("%s", sd_path); + close(fd); +} + +int main(int argc, char **argv) +{ + int ret; + + drive_create(); + + g_test_init(&argc, &argv, NULL); + + qtest_add_func("npcm7xx_sdhci/reset", test_reset); + qtest_add_func("npcm7xx_sdhci/write_sd", test_write_sd); + qtest_add_func("npcm7xx_sdhci/read_sd", test_read_sd); + + ret = g_test_run(); + drive_destroy(); + return ret; +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index f33d84d19bc..721eafad125 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -190,6 +190,7 @@ qtests_npcm7xx = \ 'npcm7xx_gpio-test', 'npcm7xx_pwm-test', 'npcm7xx_rng-test', + 'npcm7xx_sdhci-test', 'npcm7xx_smbus-test', 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] + \ From patchwork Wed Mar 2 20:52:12 2022 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/26] hw/registerfields: Add FIELD_SEX and FIELD_SDP Date: Wed, 2 Mar 2022 20:52:12 +0000 Message-Id: <20220302205230.2122390-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32b (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Add new macros to manipulate signed fields within the register. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-2-richard.henderson@linaro.org Suggested-by: Peter Maydell Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- include/hw/registerfields.h | 48 ++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index f2a3c9c41f7..3a88e135d02 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -59,6 +59,19 @@ extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_SEX8(storage, reg, field) \ + sextract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_SEX16(storage, reg, field) \ + sextract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_SEX32(storage, reg, field) \ + sextract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_SEX64(storage, reg, field) \ + sextract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) + /* Extract a field from an array of registers */ #define ARRAY_FIELD_EX32(regs, reg, field) \ FIELD_EX32((regs)[R_ ## reg], reg, field) @@ -95,7 +108,40 @@ _d; }) #define FIELD_DP64(storage, reg, field, val) ({ \ struct { \ - uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \ + uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \ + } _v = { .v = val }; \ + uint64_t _d; \ + _d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ + _d; }) + +#define FIELD_SDP8(storage, reg, field, val) ({ \ + struct { \ + signed int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } _v = { .v = val }; \ + uint8_t _d; \ + _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ + _d; }) +#define FIELD_SDP16(storage, reg, field, val) ({ \ + struct { \ + signed int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } _v = { .v = val }; \ + uint16_t _d; \ + _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ + _d; }) +#define FIELD_SDP32(storage, reg, field, val) ({ \ + struct { \ + signed int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } _v = { .v = val }; \ + uint32_t _d; \ + _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ + _d; }) +#define FIELD_SDP64(storage, reg, field, val) ({ \ + struct { \ + int64_t v:R_ ## reg ## _ ## field ## _LENGTH; \ } _v = { .v = val }; \ uint64_t _d; \ _d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ From patchwork Wed Mar 2 20:52:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547532 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp39864imq; Wed, 2 Mar 2022 13:12:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJwmsJkztoj7fGHbV5msxwR5zTq/tYh+86vfB99xGd4k+LO5p2je8FSQR1OQD8fOuc1IYVQk X-Received: by 2002:a05:6808:138f:b0:2d5:1e15:1be2 with SMTP id c15-20020a056808138f00b002d51e151be2mr1736445oiw.32.1646255534505; Wed, 02 Mar 2022 13:12:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646255534; cv=none; d=google.com; s=arc-20160816; b=xiTJ/XzhbPabos+o6f+g3vZRNBvzxWXpO7Rhha7Pw0mBKouYeCNbjwH8khPVZ/a9mI IZJ7oq+gdDfmxX8338oDlnF8q8am3kB1OcKZvX/PgYHaT/jxwz1EycPHlqVbks5gxePD OTWzCd3O0LSksla7HeB2Pswz3iWf7hGpczeoIaXkITDKFoPfovAVCsToaSJnh7viaHyj rNQllrXhtfHSqwreAxku1I7IzI82Tm/lBXWGhLxZ5iUVTBRUUUjbBMsFSoOpTDuy5lvu G7G1qkP1GcQQcCDHK9Mi4a7cl/Sa0e/mUUZkAmLRM0TE3Q/eTRuTDP4P6jTDojOwvkcn CepA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=h5vb/qPkkLSubI4hynyldV/6P4vM61yCn9qANZFywlI=; b=IzfW0HLn/j/xKgVJXlV0SdxpgqMqZIcK7an4FaSUH6OUHq4jtYAtQbrXh6R7YM6kvw JxkCpcmUpPe8wpMPthxTqCEHd2nExLiP+zBSJZhEnHX1gQiHh2amWFIS93SJjdiuOUGk TloGT/JTuLPfYCHGXeqFSbP+328n2F9S3dTqoQGHmLUlZSXbLp77+tqkcTih2CO07SRt 31fgsrnS6YcF6nwUULZ61vV8Pgp7odpQOfU1g131/eId/FqigzzocTpPOxgIrElYdwWc nUuEkhvCvfrp4OE0lyhC/NEPbL2CrqbddlrRob+RQOB9WWiRcIemmIraLt5f6eiLvT/b Hb3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g2CMi0me; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/26] target/arm: Set TCR_EL1.TSZ for user-only Date: Wed, 2 Mar 2022 20:52:13 +0000 Message-Id: <20220302205230.2122390-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::334 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Set this as the kernel would, to 48 bits, to keep the computation of the address space correct for PAuth. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index dd64d178e2e..7091684a16d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -206,10 +206,11 @@ static void arm_cpu_reset(DeviceState *dev) aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); } /* + * Enable 48-bit address space (TODO: take reserved_va into account). * Enable TBI0 but not TBI1. * Note that this must match useronly_clean_ptr. */ - env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); + env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); /* Enable MTE */ if (cpu_isar_feature(aa64_mte, cpu)) { From patchwork Wed Mar 2 20:52:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547531 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp37430imq; Wed, 2 Mar 2022 13:09:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJxRRSAxagRD26D4/oFI6+z1ZxDpH8+phhQ5fWrZsKdYyw98RTiyQCJ+XltqSzmvzMSykBAA X-Received: by 2002:a0d:fa81:0:b0:2d6:faee:cbc4 with SMTP id k123-20020a0dfa81000000b002d6faeecbc4mr32314205ywf.388.1646255348683; Wed, 02 Mar 2022 13:09:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646255348; cv=none; d=google.com; s=arc-20160816; b=OncJK5hfBCwmEmWN+b2GUv/iO44dVD8zyOCgF161/Hd7iK1nS0Rhq3t+cWH9wAOTS3 QsShhyk1mPPXWtF/FZKNekycb+21abUVwdSQ/WvmIxIf5SPS2WziOtw1/fsglZ3jpGZW JAXjRFU9ByQZBhJuK6u553tJlyOOrbJ/DPNm2s+xid+yEONOceDIWpmH4wfNOQL2l4Pq 6VETPr/jekmzfze337cJION8gcQN/Cv+xYoSJ93vJoWPIPQnzU0Auc2Zbe3UBG+dPM1B eqH2kFIpmobISI5DMmj1Xt4VGqg/GKs1CLMCFJ8s/nJWmMEL2TK2ieC2+1GNzu0pbcPB 14RA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rHPHxW6sljpCsakcbokrQfQC++We7xXTK+2WDhtOUL0=; b=pMT8ciFeI+/iE0P0HzhdelRB3i5+FxsGwa4aJolZNljhVcRxO5rZzundiGjY+frYG4 viKqxEMHMSh7S8DZDd/VkPUo0ijFz3jbgIGLvwXgCFoz/7O4o7LcOPsyN461F71Vfhe3 YTq3MMJ8A1S/uw2J35JDS2dgeYfC1qb1hbqyCXHsUMDVmDcAuJajbDwjFVtscxCJ05LO TrTU5JMKu3vvhi2y7IcK8b3/9vLSUuDifoWWndVSKbijmxtu1/ON3KT+9Z0KCPydWg0H l3WA0H6IuujsI4jEVgQNjV6YEeTYW23kfXov4EexppZGZxcgzLdSC6717+ORxEGT6Skj iuGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N67SYiPl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/26] target/arm: Fault on invalid TCR_ELx.TxSZ Date: Wed, 2 Mar 2022 20:52:14 +0000 Message-Id: <20220302205230.2122390-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42d (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Without FEAT_LVA, the behaviour of programming an invalid value is IMPLEMENTATION DEFINED. With FEAT_LVA, programming an invalid minimum value requires a Translation fault. It is most self-consistent to choose to generate the fault always. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 1 + target/arm/helper.c | 32 ++++++++++++++++++++++++++++---- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3f05748ea47..ef6c25d8cb7 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1055,6 +1055,7 @@ typedef struct ARMVAParameters { bool hpd : 1; bool using16k : 1; bool using64k : 1; + bool tsz_oob : 1; /* tsz has been clamped to legal range */ } ARMVAParameters; ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, diff --git a/target/arm/helper.c b/target/arm/helper.c index 7bf50fdd76f..dd4d95bda24 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11190,8 +11190,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; - bool epd, hpd, using16k, using64k; - int select, tsz, tbi, max_tsz; + bool epd, hpd, using16k, using64k, tsz_oob; + int select, tsz, tbi, max_tsz, min_tsz; if (!regime_has_2_ranges(mmu_idx)) { select = 0; @@ -11232,9 +11232,17 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, } else { max_tsz = 39; } + min_tsz = 16; /* TODO: ARMv8.2-LVA */ - tsz = MIN(tsz, max_tsz); - tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ + if (tsz > max_tsz) { + tsz = max_tsz; + tsz_oob = true; + } else if (tsz < min_tsz) { + tsz = min_tsz; + tsz_oob = true; + } else { + tsz_oob = false; + } /* Present TBI as a composite with TBID. */ tbi = aa64_va_parameter_tbi(tcr, mmu_idx); @@ -11251,6 +11259,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, .hpd = hpd, .using16k = using16k, .using64k = using64k, + .tsz_oob = tsz_oob, }; } @@ -11374,6 +11383,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, param = aa64_va_parameters(env, address, mmu_idx, access_type != MMU_INST_FETCH); level = 0; + + /* + * If TxSZ is programmed to a value larger than the maximum, + * or smaller than the effective minimum, it is IMPLEMENTATION + * DEFINED whether we behave as if the field were programmed + * within bounds, or if a level 0 Translation fault is generated. + * + * With FEAT_LVA, fault on less than minimum becomes required, + * so our choice is to always raise the fault. + */ + if (param.tsz_oob) { + fault_type = ARMFault_Translation; + goto do_fault; + } + addrsize = 64 - 8 * param.tbi; inputsize = 64 - param.tsz; } else { From patchwork Wed Mar 2 20:52:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547534 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp41251imq; Wed, 2 Mar 2022 13:14:25 -0800 (PST) X-Google-Smtp-Source: ABdhPJzg59cC2sd6gaBiyHPKR/dybjU6211bWecBTcLyaL6uTFTKfQ2NFeG5o+NTBEVQo4Gia0AU X-Received: by 2002:a25:5187:0:b0:623:e9ba:ba13 with SMTP id f129-20020a255187000000b00623e9baba13mr30908975ybb.311.1646255665257; Wed, 02 Mar 2022 13:14:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646255665; cv=none; d=google.com; s=arc-20160816; b=NV6R7PwSUHCrV7Z31yAYKTmtoYZNmZ35XWnMVYBcWEKT48xdXzQyE7x6u8E0uHFotW EjnE6RK2jBKmlfAL6OwARrewkncKShW5t8L9BQgZSJlUwNTvEUa8CihbBNPIvqWFLmbO 6Jo9DdotiI4Y7aTWiAdhDoNI0RaQY93ga2E8pMBJLwUAiKj7DcdHqmf5nWSodE5aUXTM /5ZrExPmOf68rxIcWib/ZwFr23j86c0jWnHqFoeetakgfQLGUSAosI4pIdBTKf4LZ/1Q 0K3FAKs5mU8pVmMWVox2tSrsTYBIsiySaAd6agjkUkq2ZVF1XXxFOVDFiugQweS3RHQN brKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/jMvBmS05a6AvX2w8GLIu2n1iO4O8JPmoPPf/h/6b0c=; b=plMm6hNOg6o2OMru/jJ97FeK9xFPdrukxE0uGwOURNn++0AG8tN5jghXLxZXkIPkEa GAxTOFxceIV56h/Vf/Adr/ScXJ2Ln48ZZDVarLhbwRSMP0E6I0cXiD0KNNT+ZiA7BrlX i8hdyPmj2fZu5OFY+2qpjWXIddEBEG/e4+KXQ4psmeBcKksfYUp8CcTmiUZu6m3ZpbUi 6jn8lIDsaLECF4ZnhaBxXjQO3rcp5j6zo0STqCcAPk9YfJCBVdDffd8P9YyFolEyAIM3 6em+UHxCo+K2maC9cw4bJa8HZgcjWP3dEc/DpMaOm5ShDR5kuKW0cRJdICnc8zlwlTSj 1uAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cl5h83Nw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/26] target/arm: Move arm_pamax out of line Date: Wed, 2 Mar 2022 20:52:15 +0000 Message-Id: <20220302205230.2122390-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::334 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We will shortly share parts of this function with other portions of address translation. Reviewed-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 19 +------------------ target/arm/helper.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 18 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index ef6c25d8cb7..fefd1fb8d88 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -243,24 +243,7 @@ static inline void update_spsel(CPUARMState *env, uint32_t imm) * Returns the implementation defined bit-width of physical addresses. * The ARMv8 reference manuals refer to this as PAMax(). */ -static inline unsigned int arm_pamax(ARMCPU *cpu) -{ - static const unsigned int pamax_map[] = { - [0] = 32, - [1] = 36, - [2] = 40, - [3] = 42, - [4] = 44, - [5] = 48, - }; - unsigned int parange = - FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); - - /* id_aa64mmfr0 is a read-only register so values outside of the - * supported mappings can be considered an implementation error. */ - assert(parange < ARRAY_SIZE(pamax_map)); - return pamax_map[parange]; -} +unsigned int arm_pamax(ARMCPU *cpu); /* Return true if extended addresses are enabled. * This is always the case if our translation regime is 64 bit, diff --git a/target/arm/helper.c b/target/arm/helper.c index dd4d95bda24..71e575f352e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11152,6 +11152,28 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) } #endif /* !CONFIG_USER_ONLY */ +/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ +unsigned int arm_pamax(ARMCPU *cpu) +{ + static const unsigned int pamax_map[] = { + [0] = 32, + [1] = 36, + [2] = 40, + [3] = 42, + [4] = 44, + [5] = 48, + }; + unsigned int parange = + FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + + /* + * id_aa64mmfr0 is a read-only register so values outside of the + * supported mappings can be considered an implementation error. + */ + assert(parange < ARRAY_SIZE(pamax_map)); + return pamax_map[parange]; +} + static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) { if (regime_has_2_ranges(mmu_idx)) { From patchwork Wed Mar 2 20:52:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547533 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp40196imq; Wed, 2 Mar 2022 13:12:42 -0800 (PST) X-Google-Smtp-Source: ABdhPJw0VyF+ZccGuxVTURRucjoM+BRDNXumlA0Ku3XSvGxqp4iB7+1q1cQl+8/kE3zVsXEKf+rR X-Received: by 2002:a81:b89:0:b0:2db:c3d0:ae32 with SMTP id 131-20020a810b89000000b002dbc3d0ae32mr12721093ywl.436.1646255561927; Wed, 02 Mar 2022 13:12:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646255561; cv=none; d=google.com; s=arc-20160816; b=r7yOQDFseBX7YQ94iK2UzjfHOGODl8Jo5HeHhVnKZsHCb7ymHbM8MsyjEQ9e4oO4BZ J29tggBZgOOLcPkik6qZcKrQQ8WDkw8LqXeIxlXcGUWv2UVa3EyNpDle+WvLDiekrpBP l4qQYXk8rG7s4E9UF4+5V23Zk8DBPnjHw1I8r496HmqkFMJ8HT48G9atdYQic+gOXkpA MSif0eqdB2GHToZnsHmLs9xbWLu7r9hLK+WiLbdYd6cWtkSDF1tTrt6s+GoAU/Y2uPHp dEdKDu+Mmo3M99F28rES7VvXydQIr0dYNsBKkW7PF1SnTOdDWfUBjJI4SbS3S7EAS/IT T4nA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+cFrQ0gYtD+BMJbyD47IQWGJju9cN+yG8odvU6RxmJ4=; b=ODwNd5nv4ZA0XNyOijRUGaoT5NcP9bxbG1vDOfXvBNWLyMoBtyWrsfdX3lFfFRYwl3 yNhusO81AG6Mk5bAjoPrJiRMhiDGcfEjvz+1gC6o9zPKuOEETeE4ZdQt0xGe+O/SDkVY lvPZtu/zSJNw/PKRcdjebIul3AwJLHvq4UcDcoo+gVaY6vDk/so4oq4ektNxXiByMwPM 1zNRmhjK/etfD54UCy0NWG4b2VxtlRU2TwwyXQlUy1Kh4nGalFQnKnSGGtG0rtY0OEum 2nqZGRoPSXtRP6OVT1+FqOgn8lvZbF8N8Gl7xyNuH+1EA3fA8/FzCOLNtFN91fNzA2w2 74Tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=boiE02vl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/26] target/arm: Pass outputsize down to check_s2_mmu_setup Date: Wed, 2 Mar 2022 20:52:16 +0000 Message-Id: <20220302205230.2122390-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::432 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Pass down the width of the output address from translation. For now this is still just PAMax, but a subsequent patch will compute the correct value from TCR_ELx.{I}PS. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 71e575f352e..431b0c14052 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11065,7 +11065,7 @@ do_fault: * false otherwise. */ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, - int inputsize, int stride) + int inputsize, int stride, int outputsize) { const int grainsize = stride + 3; int startsizecheck; @@ -11081,22 +11081,19 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, } if (is_aa64) { - CPUARMState *env = &cpu->env; - unsigned int pamax = arm_pamax(cpu); - switch (stride) { case 13: /* 64KB Pages. */ - if (level == 0 || (level == 1 && pamax <= 42)) { + if (level == 0 || (level == 1 && outputsize <= 42)) { return false; } break; case 11: /* 16KB Pages. */ - if (level == 0 || (level == 1 && pamax <= 40)) { + if (level == 0 || (level == 1 && outputsize <= 40)) { return false; } break; case 9: /* 4KB Pages. */ - if (level == 0 && pamax <= 42) { + if (level == 0 && outputsize <= 42) { return false; } break; @@ -11105,8 +11102,8 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, } /* Inputsize checks. */ - if (inputsize > pamax && - (arm_el_is_aa64(env, 1) || inputsize > 40)) { + if (inputsize > outputsize && + (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) { /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ return false; } @@ -11392,7 +11389,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, target_ulong page_size; uint32_t attrs; int32_t stride; - int addrsize, inputsize; + int addrsize, inputsize, outputsize; TCR *tcr = regime_tcr(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el = regime_el(env, mmu_idx); @@ -11422,11 +11419,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, addrsize = 64 - 8 * param.tbi; inputsize = 64 - param.tsz; + outputsize = arm_pamax(cpu); } else { param = aa32_va_parameters(env, address, mmu_idx); level = 1; addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32); inputsize = addrsize - param.tsz; + outputsize = 40; } /* @@ -11511,7 +11510,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* Check that the starting level is valid. */ ok = check_s2_mmu_setup(cpu, aarch64, startlevel, - inputsize, stride); + inputsize, stride, outputsize); if (!ok) { fault_type = ARMFault_Translation; goto do_fault; From patchwork Wed Mar 2 20:52:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547536 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp42804imq; Wed, 2 Mar 2022 13:16:53 -0800 (PST) X-Google-Smtp-Source: ABdhPJwDugtI4+FbphOS4Ijvun0HoryZLeaWVmf7nJLC105HxNquCNAh8+cvaI7RIel+Oka7syYF X-Received: by 2002:a05:6130:388:b0:342:b8e5:15c2 with SMTP id az8-20020a056130038800b00342b8e515c2mr15421903uab.85.1646255813773; Wed, 02 Mar 2022 13:16:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646255813; cv=none; d=google.com; s=arc-20160816; b=TZbd/fSjAAu9jW7NDSJTNvGm7Nzb9oXdyRqjdc15/P4iXByN28UcOQrucpLaPd2h67 TbEKrrnYAmEQZrZF+d67Ojo+X8GhhkmHf6kTigvp6bQozbDThKTSGIMr4K53FOgtUzQl KAs/h0mQfKRokyCxUFDke3odhe+ytWcepOMCic7OSmE/6TU7syPoiymWlp3GXDmcGNQo Lve3j2EiXNru8UBspYPQIBxcIvr+4Lzy5C3zR+dg/XnrpkN8ekNSmZFkokXoYxXBzssA THN32/3GDJj67OqHYLr5XmvJSvLD+RG2igfBVexE70SSam0c0LsGWivPnoCPZ+gScScz HY9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cRu0ONP9iJRS52TXzF5kbcfgXqfx58WUEunHKG1fNWY=; b=VlJdD0z51PxNEhVMFgudNtI5T397a3IxdkckecImM7pjug3L7Lxx0MvfjTNoXjG4XZ I7gP2NjsfJaRcr0+9ma+dVR9AiHU6g42X2Mr+Fd9edApm41b+i2VOdHPuL0vK8W9gn0y 7dAcx8Y5Op9S6Fn6gdDo4jkroNbziGmcEDznksK+xcoMhNRl7G5D3KQLsqmym2/6QV4S CwMLH67dPMNEr8i39/KODWWAOXTGzUj64H7CHp03tBjTf+w1xpvoMVF5Xz7Khx3lvBfW 8ce/l4zOeghe/P6smff7wA5WWMmyS3njBOP4Sr4OlR9aZB3WJtCctyRJLUJRAUEgT2yT OPIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g9wsUoT7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/26] target/arm: Use MAKE_64BIT_MASK to compute indexmask Date: Wed, 2 Mar 2022 20:52:17 +0000 Message-Id: <20220302205230.2122390-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::432 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The macro is a bit more readable than the inlined computation. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 431b0c14052..675aec4bf30 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11518,8 +11518,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, level = startlevel; } - indexmask_grainsize = (1ULL << (stride + 3)) - 1; - indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; + indexmask_grainsize = MAKE_64BIT_MASK(0, stride + 3); + indexmask = MAKE_64BIT_MASK(0, inputsize - (stride * (4 - level))); /* Now we can extract the actual base address from the TTBR */ descaddr = extract64(ttbr, 0, 48); From patchwork Wed Mar 2 20:52:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547537 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp43263imq; Wed, 2 Mar 2022 13:17:39 -0800 (PST) X-Google-Smtp-Source: ABdhPJyMfP5gY1G8ijZx5TyE86N1OYadNJVn4XJk1jfZZkCFyEU2ONJgBxOsLcvygIFnd333LHgm X-Received: by 2002:a67:f7d6:0:b0:31c:1ffc:8a91 with SMTP id a22-20020a67f7d6000000b0031c1ffc8a91mr14354468vsp.66.1646255859394; Wed, 02 Mar 2022 13:17:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646255859; cv=none; d=google.com; s=arc-20160816; b=Pz/sWnzhA1ii70bXGwlaPwE1FNLCmyazcqdLmaeZUj3dPmPxR3inqlG+84jKGN7D8P UkiWXIFGNXOTlnrMjAQ3KChTAqIadE6mkhLmDiBBeMEe2Yib7OMQE9vCRYnrjlO8lmI/ 1XGLTixC7OOXGa5vdWJY1o65r2bQU/fmccnesb1M9cZf4BQbqSyR2GPVwl8GrakaWsOO A87YXTIw1QsvrAw8K69BugSR1/TnTHbSGzy54zHr+7jgINi4jcZGgLhg6uUR9/0S9pDO 8X9c+aoVmpysb9IrTBX9JF0aUgCfSwEM8Ve9aBmF5ErjzbuEmzk7R4dVsQ/RRw/C/HcL af+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ktp5JrOUqDuz2WM1tRsh4muMal7IsNgv1POHAYYvYgA=; b=OLQlvsvY+7PK9whuLrWzQ0d4+4l0Fc0irXFtAPHpRFtzSq/1vxPF/EnhgHXBkSaQtL +g35uMfLE2cE/zvQ/cyiapRDu7ycHdwB/IpZganacQLO8GEvlOTwhmYheVZMoSZL5PF8 +wl858TNjWKJ92OcZkHrC1xClk/LOEVYNvwmNlJAjjAvUbqaqXGCY7pM1Av6NOKp3n0S P2x17HFQ273qvd3NSo0Ci6iLSFyztEwQtJo/XxUAx4YydBq+2WZ6Gpq5uvz1uorZibWi 92Ac8Oj3H1MN6rB7DYaomBcUAhD5XrQR4n4KPOJL3OMociHnBIfFfYRpIknH0Vjj7Tt2 G6cA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="lYkS/cYo"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/26] target/arm: Honor TCR_ELx.{I}PS Date: Wed, 2 Mar 2022 20:52:18 +0000 Message-Id: <20220302205230.2122390-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42d (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This field controls the output (intermediate) physical address size of the translation process. V8 requires to raise an AddressSize fault if the page tables are programmed incorrectly, such that any intermediate descriptor address, or the final translated address, is out of range. Add a PS field to ARMVAParameters, and properly compute outputsize in get_phys_addr_lpae. Test the descaddr as extracted from TTBR and from page table entries. Restrict descaddrmask so that we won't raise the fault for v7. Reviewed-by: Peter Maydell Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 1 + target/arm/helper.c | 72 ++++++++++++++++++++++++++++++++---------- 2 files changed, 57 insertions(+), 16 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fefd1fb8d88..3d3d41ba2b7 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1032,6 +1032,7 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) */ typedef struct ARMVAParameters { unsigned tsz : 8; + unsigned ps : 3; unsigned select : 1; bool tbi : 1; bool epd : 1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 675aec4bf30..c002100979f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11149,17 +11149,19 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) } #endif /* !CONFIG_USER_ONLY */ +/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ +static const uint8_t pamax_map[] = { + [0] = 32, + [1] = 36, + [2] = 40, + [3] = 42, + [4] = 44, + [5] = 48, +}; + /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ unsigned int arm_pamax(ARMCPU *cpu) { - static const unsigned int pamax_map[] = { - [0] = 32, - [1] = 36, - [2] = 40, - [3] = 42, - [4] = 44, - [5] = 48, - }; unsigned int parange = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); @@ -11210,7 +11212,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; bool epd, hpd, using16k, using64k, tsz_oob; - int select, tsz, tbi, max_tsz, min_tsz; + int select, tsz, tbi, max_tsz, min_tsz, ps; if (!regime_has_2_ranges(mmu_idx)) { select = 0; @@ -11224,6 +11226,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, hpd = extract32(tcr, 24, 1); } epd = false; + ps = extract32(tcr, 16, 3); } else { /* * Bit 55 is always between the two regions, and is canonical for @@ -11244,6 +11247,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, epd = extract32(tcr, 23, 1); hpd = extract64(tcr, 42, 1); } + ps = extract64(tcr, 32, 3); } if (cpu_isar_feature(aa64_st, env_archcpu(env))) { @@ -11272,6 +11276,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, return (ARMVAParameters) { .tsz = tsz, + .ps = ps, .select = select, .tbi = tbi, .epd = epd, @@ -11399,6 +11404,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* TODO: This code does not support shareability levels. */ if (aarch64) { + int ps; + param = aa64_va_parameters(env, address, mmu_idx, access_type != MMU_INST_FETCH); level = 0; @@ -11419,7 +11426,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, addrsize = 64 - 8 * param.tbi; inputsize = 64 - param.tsz; - outputsize = arm_pamax(cpu); + + /* + * Bound PS by PARANGE to find the effective output address size. + * ID_AA64MMFR0 is a read-only register so values outside of the + * supported mappings can be considered an implementation error. + */ + ps = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + ps = MIN(ps, param.ps); + assert(ps < ARRAY_SIZE(pamax_map)); + outputsize = pamax_map[ps]; } else { param = aa32_va_parameters(env, address, mmu_idx); level = 1; @@ -11523,19 +11539,38 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* Now we can extract the actual base address from the TTBR */ descaddr = extract64(ttbr, 0, 48); + + /* + * If the base address is out of range, raise AddressSizeFault. + * In the pseudocode, this is !IsZero(baseregister<47:outputsize>), + * but we've just cleared the bits above 47, so simplify the test. + */ + if (descaddr >> outputsize) { + level = 0; + fault_type = ARMFault_AddressSize; + goto do_fault; + } + /* * We rely on this masking to clear the RES0 bits at the bottom of the TTBR * and also to mask out CnP (bit 0) which could validly be non-zero. */ descaddr &= ~indexmask; - /* The address field in the descriptor goes up to bit 39 for ARMv7 - * but up to bit 47 for ARMv8, but we use the descaddrmask - * up to bit 39 for AArch32, because we don't need other bits in that case - * to construct next descriptor address (anyway they should be all zeroes). + /* + * For AArch32, the address field in the descriptor goes up to bit 39 + * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0 + * or an AddressSize fault is raised. So for v8 we extract those SBZ + * bits as part of the address, which will be checked via outputsize. + * For AArch64, the address field always goes up to bit 47 (with extra + * bits for FEAT_LPA placed elsewhere). AArch64 implies v8. */ - descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & - ~indexmask_grainsize; + if (arm_feature(env, ARM_FEATURE_V8)) { + descaddrmask = MAKE_64BIT_MASK(0, 48); + } else { + descaddrmask = MAKE_64BIT_MASK(0, 40); + } + descaddrmask &= ~indexmask_grainsize; /* Secure accesses start with the page table in secure memory and * can be downgraded to non-secure at any step. Non-secure accesses @@ -11560,7 +11595,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* Invalid, or the Reserved level 3 encoding */ goto do_fault; } + descaddr = descriptor & descaddrmask; + if (descaddr >> outputsize) { + fault_type = ARMFault_AddressSize; + goto do_fault; + } if ((descriptor & 2) && (level < 3)) { /* Table entry. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/26] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA Date: Wed, 2 Mar 2022 20:52:19 +0000 Message-Id: <20220302205230.2122390-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42b (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The original A.a revision of the AArch64 ARM required that we force-extend the addresses in these registers from 49 bits. This language has been loosened via a combination of IMPLEMENTATION DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of the entire aligned address. This means that we do not have to consider whether or not FEAT_LVA is enabled, and decide from which bit an address might need to be extended. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c002100979f..2eff30d18c6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6423,11 +6423,18 @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, ARMCPU *cpu = env_archcpu(env); int i = ri->crm; - /* Bits [63:49] are hardwired to the value of bit [48]; that is, the - * register reads and behaves as if values written are sign extended. + /* * Bits [1:0] are RES0. + * + * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA) + * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if + * they contain the value written. It is CONSTRAINED UNPREDICTABLE + * whether the RESS bits are ignored when comparing an address. + * + * Therefore we are allowed to compare the entire register, which lets + * us avoid considering whether or not FEAT_LVA is actually enabled. */ - value = sextract64(value, 0, 49) & ~3ULL; + value &= ~3ULL; raw_write(env, ri, value); hw_watchpoint_update(cpu, i); @@ -6473,10 +6480,19 @@ void hw_breakpoint_update(ARMCPU *cpu, int n) case 0: /* unlinked address match */ case 1: /* linked address match */ { - /* Bits [63:49] are hardwired to the value of bit [48]; that is, - * we behave as if the register was sign extended. Bits [1:0] are - * RES0. The BAS field is used to allow setting breakpoints on 16 - * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether + /* + * Bits [1:0] are RES0. + * + * It is IMPLEMENTATION DEFINED whether bits [63:49] + * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit + * of the VA field ([48] or [52] for FEAT_LVA), or whether the + * value is read as written. It is CONSTRAINED UNPREDICTABLE + * whether the RESS bits are ignored when comparing an address. + * Therefore we are allowed to compare the entire register, which + * lets us avoid considering whether FEAT_LVA is actually enabled. + * + * The BAS field is used to allow setting breakpoints on 16-bit + * wide instructions; it is CONSTRAINED UNPREDICTABLE whether * a bp will fire if the addresses covered by the bp and the addresses * covered by the insn overlap but the insn doesn't start at the * start of the bp address range. We choose to require the insn and @@ -6489,7 +6505,7 @@ void hw_breakpoint_update(ARMCPU *cpu, int n) * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). */ int bas = extract64(bcr, 5, 4); - addr = sextract64(bvr, 0, 49) & ~3ULL; + addr = bvr & ~3ULL; if (bas == 0) { return; } From patchwork Wed Mar 2 20:52:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547535 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp41562imq; Wed, 2 Mar 2022 13:14:57 -0800 (PST) X-Google-Smtp-Source: ABdhPJwV3BnyUajxuDZIl6CydONOAmKz0JHCq51abQNfEMmZXZHfQvcVwZtYzqRrkQjIQHRHUJw3 X-Received: by 2002:a05:6102:ec6:b0:31b:4882:8685 with SMTP id m6-20020a0561020ec600b0031b48828685mr14203616vst.70.1646255697641; Wed, 02 Mar 2022 13:14:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646255697; cv=none; d=google.com; s=arc-20160816; b=Q1cH3oqMB8bY9zKue9TQHXyYk3Os6UjpQ5B+ocSHu4o+XV359uCv7kcbDHu7+zFtGs 9NgwM8FHThQOhTZbbFh0U6+n15KeqUjhVyO006giGaarTktuwaw3oECpngppfGUc5Ale ZUfC/MNBT7Fq8/wKwMWy4NbRdgs0GxAcD5MVBwWZ3C4zCihB9Ct+nV2IqUG+TyhGpG9p A2XuspE38Vt2sYWiiHJmkkKjKnp4fuIHl7gr+mj2A0PWYc7IPi28VvjosusPhSb6XmIP YiQsM5dOTtCVxVzsXMY5ukAxhzmpgCpAddwSg1lKg7hKPRVOp/x4R1G3vGu/gBI2JBTi Ydiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=a6BM5prJChWZqJQTT1PzTDgjTHURzpRa12/wyNIbx18=; b=LHh/ipcP0v+GzLmmaw5jb7MQhlQWCATjt96VycbWLDhLMqdf0cFmxvbPMfhB3/5jv1 R2f47S5L7C2bUTPf+CW2m4pNnFm+RxeXIRaX1E/uMg9fcN7faQdo58ljIq6TQCtwlQVJ Jve3H/V5vIit+YLoy55POTTpmr6EvZC0MeReEGnbTV6tcuYel/7gF6Gon9G+5tkBK7qv qkWMgzLPNWBLcgoWNNMXyVoeHIQUb0CjJRPjZawFj9/sWnOkG0a07vSoD8P3VG6Nl4+4 BgJUC5UPinOvfRomiyg9/SdlpGdMgTH2Fz4nhB7/DyMTwl6lvitbPn2iNb9rQHPHXSA6 unGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DDAlN3Cb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/26] target/arm: Implement FEAT_LVA Date: Wed, 2 Mar 2022 20:52:20 +0000 Message-Id: <20220302205230.2122390-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32f (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This feature is relatively small, as it applies only to 64k pages and thus requires no additional changes to the table descriptor walking algorithm, only a change to the minimum TSZ (which is the inverse of the maximum virtual address space size). Note that this feature widens VBAR_ELx, but we already treat the register as being 64 bits wide. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 5 +++++ target/arm/cpu64.c | 1 + target/arm/helper.c | 9 ++++++++- 5 files changed, 16 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 144dc491d95..f3eabddfb5a 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -27,6 +27,7 @@ the following architecture extensions: - FEAT_LRCPC (Load-acquire RCpc instructions) - FEAT_LRCPC2 (Load-acquire RCpc instructions v2) - FEAT_LSE (Large System Extensions) +- FEAT_LVA (Large Virtual Address space) - FEAT_MTE (Memory Tagging Extension) - FEAT_MTE2 (Memory Tagging Extension) - FEAT_MTE3 (MTE Asymmetric Fault Handling) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 7f38d33b8ea..5f9c288b1a6 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -11,7 +11,7 @@ #ifdef TARGET_AARCH64 # define TARGET_LONG_BITS 64 # define TARGET_PHYS_ADDR_SPACE_BITS 48 -# define TARGET_VIRT_ADDR_SPACE_BITS 48 +# define TARGET_VIRT_ADDR_SPACE_BITS 52 #else # define TARGET_LONG_BITS 32 # define TARGET_PHYS_ADDR_SPACE_BITS 40 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6a4d50e821..c52d56f6699 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4289,6 +4289,11 @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; } +static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; +} + static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1171ab16b94..1de31ffb406 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -811,6 +811,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ + t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ cpu->isar.id_aa64mmfr2 = t; t = cpu->isar.id_aa64zfr0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 2eff30d18c6..28b43472131 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11271,7 +11271,14 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, } else { max_tsz = 39; } - min_tsz = 16; /* TODO: ARMv8.2-LVA */ + + min_tsz = 16; + if (using64k) { + if (cpu_isar_feature(aa64_lva, env_archcpu(env))) { + min_tsz = 12; + } + } + /* TODO: FEAT_LPA2 */ if (tsz > max_tsz) { tsz = max_tsz; From patchwork Wed Mar 2 20:52:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547539 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp44462imq; Wed, 2 Mar 2022 13:19:35 -0800 (PST) X-Google-Smtp-Source: ABdhPJyGHZbBx8crsmtP1obZkEluhWjnNyhXceSXbyXjSZKlnwkyQZlFCGAB2TF0poMU1qwLzbs6 X-Received: by 2002:a25:af92:0:b0:628:b791:281b with SMTP id g18-20020a25af92000000b00628b791281bmr2188042ybh.87.1646255975171; Wed, 02 Mar 2022 13:19:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646255975; cv=none; d=google.com; s=arc-20160816; b=YULr4KZG1Nj5K1hNZn2GNZIav/OCifHA7bKu1jSCLO8eCOkPm8yAm9HC0zqX6D7TCK WW7KYFt2OwfT++AyMBroAl2b86LB+x4g+NPvavDT/6L8tzk33sSYBGNrwV+FE/sFCUfS 2EroE9I0aeiYVv1r2nFPRBIOoMeAw1cucIVxn6svRLxrqWLNkfYfBZ7jFfiDkPCz9jAF sFieg4Q4X/U9kWH/s7h/p3yBoyYS3pKCCcNNNkMPHPHTGZAuvwUxj+tALzUmUVbtH78N SxzpLNidWWszcs6nORyO2JlHpeH/DzRmNUBTgABZ46G3b54ES4bQW6HoTcO5gL7yZpgG EzfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CRKzi8an4EM1SJfqwBg52hhLiM5AICaglyAbFT7p8Tc=; b=wqFDZdOQVvRTL/sRUgbAQtjLmrWsJaVU5mUwQEQLQzuAaaxRDXtFWKhOyD4ZXSvBjn Ys1HKMWuWtauRnwisR6T41V2wgepeeOAs5vsWOqZgTusnwsmj4JiuQg4pcYh6T5K9gRi j37SqLXWv+/yVJfTOIjVwSUDH9XtCC1c88679+MpU2sZlBGPSn7JWqq/En3BYvtuVf7D aIhgJ8//kJP8lfKx6qz+o0jpTpXQ7SUQsZdJqLgudiF4U2OMcrqlBPR62fJjzHNykcV7 6zdcVKgmTfFvjn918JAmMRfrQIgbPKUyFb4nnScdYGx/NeJB3V8qnRBTjREYIOkWazwJ Xylw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MAPESj58; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/26] target/arm: Implement FEAT_LPA Date: Wed, 2 Mar 2022 20:52:21 +0000 Message-Id: <20220302205230.2122390-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::429 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This feature widens physical addresses (and intermediate physical addresses for 2-stage translation) from 48 to 52 bits, when using 64k pages. The only thing left at this point is to handle the extra bits in the TTBR and in the table descriptors. Note that PAR_EL1 and HPFAR_EL2 are nominally extended, but we don't mask out the high bits when writing to those registers, so no changes are required there. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-param.h | 2 +- target/arm/cpu64.c | 2 +- target/arm/helper.c | 19 ++++++++++++++++--- 4 files changed, 19 insertions(+), 5 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index f3eabddfb5a..0053ddce208 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -24,6 +24,7 @@ the following architecture extensions: - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) - FEAT_JSCVT (JavaScript conversion instructions) - FEAT_LOR (Limited ordering regions) +- FEAT_LPA (Large Physical Address space) - FEAT_LRCPC (Load-acquire RCpc instructions) - FEAT_LRCPC2 (Load-acquire RCpc instructions v2) - FEAT_LSE (Large System Extensions) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 5f9c288b1a6..b59d505761c 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -10,7 +10,7 @@ #ifdef TARGET_AARCH64 # define TARGET_LONG_BITS 64 -# define TARGET_PHYS_ADDR_SPACE_BITS 48 +# define TARGET_PHYS_ADDR_SPACE_BITS 52 # define TARGET_VIRT_ADDR_SPACE_BITS 52 #else # define TARGET_LONG_BITS 32 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1de31ffb406..d88662cef68 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -795,7 +795,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64pfr1 = t; t = cpu->isar.id_aa64mmfr0; - t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */ + t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ cpu->isar.id_aa64mmfr0 = t; t = cpu->isar.id_aa64mmfr1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 28b43472131..950f56599e2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11173,6 +11173,7 @@ static const uint8_t pamax_map[] = { [3] = 42, [4] = 44, [5] = 48, + [6] = 52, }; /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ @@ -11564,11 +11565,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, descaddr = extract64(ttbr, 0, 48); /* - * If the base address is out of range, raise AddressSizeFault. + * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR. + * + * Otherwise, if the base address is out of range, raise AddressSizeFault. * In the pseudocode, this is !IsZero(baseregister<47:outputsize>), * but we've just cleared the bits above 47, so simplify the test. */ - if (descaddr >> outputsize) { + if (outputsize > 48) { + descaddr |= extract64(ttbr, 2, 4) << 48; + } else if (descaddr >> outputsize) { level = 0; fault_type = ARMFault_AddressSize; goto do_fault; @@ -11620,7 +11625,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, } descaddr = descriptor & descaddrmask; - if (descaddr >> outputsize) { + + /* + * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12] + * of descriptor. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/26] target/arm: Extend arm_fi_to_lfsc to level -1 Date: Wed, 2 Mar 2022 20:52:22 +0000 Message-Id: <20220302205230.2122390-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::431 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson With FEAT_LPA2, rather than introducing translation level 4, we introduce level -1, below the current level 0. Extend arm_fi_to_lfsc to handle these faults. Assert that this new translation level does not leak into fault types for which it is not defined, which allows some masking of fi->level to be removed. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3d3d41ba2b7..00af41d7925 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -462,28 +462,51 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) case ARMFault_None: return 0; case ARMFault_AddressSize: - fsc = fi->level & 3; + assert(fi->level >= -1 && fi->level <= 3); + if (fi->level < 0) { + fsc = 0b101001; + } else { + fsc = fi->level; + } break; case ARMFault_AccessFlag: - fsc = (fi->level & 3) | (0x2 << 2); + assert(fi->level >= 0 && fi->level <= 3); + fsc = 0b001000 | fi->level; break; case ARMFault_Permission: - fsc = (fi->level & 3) | (0x3 << 2); + assert(fi->level >= 0 && fi->level <= 3); + fsc = 0b001100 | fi->level; break; case ARMFault_Translation: - fsc = (fi->level & 3) | (0x1 << 2); + assert(fi->level >= -1 && fi->level <= 3); + if (fi->level < 0) { + fsc = 0b101011; + } else { + fsc = 0b000100 | fi->level; + } break; case ARMFault_SyncExternal: fsc = 0x10 | (fi->ea << 12); break; case ARMFault_SyncExternalOnWalk: - fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12); + assert(fi->level >= -1 && fi->level <= 3); + if (fi->level < 0) { + fsc = 0b010011; + } else { + fsc = 0b010100 | fi->level; + } + fsc |= fi->ea << 12; break; case ARMFault_SyncParity: fsc = 0x18; break; case ARMFault_SyncParityOnWalk: - fsc = (fi->level & 3) | (0x7 << 2); + assert(fi->level >= -1 && fi->level <= 3); + if (fi->level < 0) { + fsc = 0b011011; + } else { + fsc = 0b011100 | fi->level; + } break; case ARMFault_AsyncParity: fsc = 0x19; From patchwork Wed Mar 2 20:52:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547525 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp34704imq; Wed, 2 Mar 2022 13:05:37 -0800 (PST) X-Google-Smtp-Source: ABdhPJxPE3Zqh0lWJCbCQZn4b1WEv9heAy8J2hwmLs+z/uFHDXBcBu0+KtisotCpxe4Eff3ErO5m X-Received: by 2002:a05:6870:1244:b0:ce:c0c9:620 with SMTP id 4-20020a056870124400b000cec0c90620mr1457410oao.114.1646255137303; Wed, 02 Mar 2022 13:05:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646255137; cv=none; d=google.com; s=arc-20160816; b=iNXztDTa0mVIUxvLKRo8JvxHC1bOC5wpqxUW8GtOIRwYxMPn4jNtnq+PFyc5X3y5Or buCLBKkUSFdsCqEtQJYWxKkfxcIASu3QpW+sbKIO2oRcAgd1Vc8J2JlAFHApab258Cxm eKDO2cDqmdh2S/09cJ2tJFAYbLJ1LRdOBFzaf8xXt5yWA3BHj0fQHIuHGWPVgHMVvhhE Z2Dmc5xOL4LTC3hnyFyme+5j3WYxM7kTanYZr8V77mK64aT8iQiCyBs45UHbWbmz2XEd XPUH6Hw+BZUexeZs0m5FADL/lU2OMKtH9iwlnRCee6rL9F5FOEFO74xt7BTBL0SLwm02 9g7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=i7la0k2eorJda0aIicEx+aLSW513Xo/ZYfhT/cVR5VI=; b=cQ5TfKa/xCDqGPwv6OLv1BkWi+vCy60iFpFWd/89Q4/KlAqvGTcJKfS9nwrEwZuWPn +LOq1lbR7IJaprMtS5XCIk8NXRdBRg9Awv2BZvtf4IRWb3YJi4RdMWfMlh109hnPTYnJ NGuFQEJedi2CnDofa0W9hs2nGMC99cojTrf692jlxMcgAhYg807zsF7gB+CP5KMz2AU6 x6Ha5VN1a4sQHFAdhCAlU8n9S02ByQ+oAWumfTPNTSMaOJhxQJ4kRszbXPmtbkGhepLE 7ZcqW4b4qbqIwAEgn4/khZk0KXmODpVw0p6Kvz9M+5SD6PfzV+qTjaBWUav9IFZA6LnI XySg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aO7EcNo1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/26] target/arm: Introduce tlbi_aa64_get_range Date: Wed, 2 Mar 2022 20:52:23 +0000 Message-Id: <20220302205230.2122390-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::432 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Merge tlbi_aa64_range_get_length and tlbi_aa64_range_get_base, returning a structure containing both results. Pass in the ARMMMUIdx, rather than the digested two_ranges boolean. This is in preparation for FEAT_LPA2, where the interpretation of 'value' depends on the effective value of DS for the regime. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 58 +++++++++++++++++++-------------------------- 1 file changed, 24 insertions(+), 34 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 950f56599e2..31c2a716f2a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4511,70 +4511,60 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, } #ifdef TARGET_AARCH64 -static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, - uint64_t value) -{ - unsigned int page_shift; - unsigned int page_size_granule; - uint64_t num; - uint64_t scale; - uint64_t exponent; +typedef struct { + uint64_t base; uint64_t length; +} TLBIRange; + +static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, + uint64_t value) +{ + unsigned int page_size_granule, page_shift, num, scale, exponent; + TLBIRange ret = { }; - num = extract64(value, 39, 5); - scale = extract64(value, 44, 2); page_size_granule = extract64(value, 46, 2); if (page_size_granule == 0) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", page_size_granule); - return 0; + return ret; } page_shift = (page_size_granule - 1) * 2 + 12; - + num = extract64(value, 39, 5); + scale = extract64(value, 44, 2); exponent = (5 * scale) + 1; - length = (num + 1) << (exponent + page_shift); - return length; -} + ret.length = (num + 1) << (exponent + page_shift); -static uint64_t tlbi_aa64_range_get_base(CPUARMState *env, uint64_t value, - bool two_ranges) -{ - /* TODO: ARMv8.7 FEAT_LPA2 */ - uint64_t pageaddr; - - if (two_ranges) { - pageaddr = sextract64(value, 0, 37) << TARGET_PAGE_BITS; + if (regime_has_2_ranges(mmuidx)) { + ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS; } else { - pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS; + ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS; } - return pageaddr; + return ret; } static void do_rvae_write(CPUARMState *env, uint64_t value, int idxmap, bool synced) { ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap); - bool two_ranges = regime_has_2_ranges(one_idx); - uint64_t baseaddr, length; + TLBIRange range; int bits; - baseaddr = tlbi_aa64_range_get_base(env, value, two_ranges); - length = tlbi_aa64_range_get_length(env, value); - bits = tlbbits_for_regime(env, one_idx, baseaddr); + range = tlbi_aa64_get_range(env, one_idx, value); + bits = tlbbits_for_regime(env, one_idx, range.base); if (synced) { tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), - baseaddr, - length, + range.base, + range.length, idxmap, bits); } else { - tlb_flush_range_by_mmuidx(env_cpu(env), baseaddr, - length, idxmap, bits); + tlb_flush_range_by_mmuidx(env_cpu(env), range.base, + range.length, idxmap, bits); } } From patchwork Wed Mar 2 20:52:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547521 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp31379imq; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/26] target/arm: Fix TLBIRange.base for 16k and 64k pages Date: Wed, 2 Mar 2022 20:52:24 +0000 Message-Id: <20220302205230.2122390-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::429 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The shift of the BaseADDR field depends on the translation granule in use. Fixes: 84940ed8255 ("target/arm: Add support for FEAT_TLBIRANGE") Reported-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 31c2a716f2a..e455397fb57 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4538,10 +4538,11 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, ret.length = (num + 1) << (exponent + page_shift); if (regime_has_2_ranges(mmuidx)) { - ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS; + ret.base = sextract64(value, 0, 37); } else { - ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS; + ret.base = extract64(value, 0, 37); } + ret.base <<= page_shift; return ret; } From patchwork Wed Mar 2 20:52:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547530 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp37174imq; Wed, 2 Mar 2022 13:08:50 -0800 (PST) X-Google-Smtp-Source: ABdhPJwyljLVIDmymOd8wrbFUe+LbJkbPWRr/d9h61+pICuRyh+T4Juy+PTJZguOTYxneCEBO+BG X-Received: by 2002:a25:7407:0:b0:628:97bf:39e5 with SMTP id p7-20020a257407000000b0062897bf39e5mr6141245ybc.597.1646255329968; Wed, 02 Mar 2022 13:08:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646255329; cv=none; d=google.com; s=arc-20160816; b=xoFllG+DwpWI53WOfcfRVj3+PK2hM52Eoifh3SVqBJBAp/1FMzCIpX2sZmIQH589Wn q24qsQf8VGQJSi7mKC6PZIs3elTAf2Rxyu3OASV2RMWN1u8cLgG7PSsescgiABZiZgGi gufW6JQ4RJ5+z+yxIqcTAs+3IhlXmIiKKD9PvMPrP9GM2FkT0AceSY6eIDouoLlw6OGR Xm0HXbJHqjO6ZzuGsZ/5Ok7H1Y1u1uoGz/pL65nzPoeN8mSTzKAG5URmdlCow2bwv9TV k3bDIEfLLUFxBWxVjfHhMFHlUq/6OsIdBqc2t4NzPYgpO9vE8CoEW+dpv1RzjCM/fHW0 GVAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SM320yQbplZVI8Mj8lk3kp4hv9BTspAqO+QUiQG4O/o=; b=XI/hDuDs6/l0hm15vVmIVIZcJHaRhk7gd/EOktm7mi3Jy8Sb96JQ+YgkJmnDn9qdKi L7ASvpG9YyPTHhz6ZaczAmZVmXgyzfLrPiepOt7MDo97pTUI/ttntmp9NEbQL7G/5zlE KLDsUEWLmD9jJ09OdzqyYsxhMgYYyJjBxJvPk8gCNwKKvn6U7cBixpr/bn73FQnaMAPx tlLMaSIF+ktibWuIhvH8zjZPuTybbopvs0+QoF/LcttRTnYQL3f/vZr1VFbNpuUTbVXP ixop7XrdVsBsINfN0aA55fGdHoJjyE+KpZgFDS6G9PS+nqIsNbBqpuU3HWZa9fd8pHq6 8yKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NkLPESjW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/26] target/arm: Validate tlbi TG matches translation granule in use Date: Wed, 2 Mar 2022 20:52:25 +0000 Message-Id: <20220302205230.2122390-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42d (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson For FEAT_LPA2, we will need other ARMVAParameters, which themselves depend on the translation granule in use. We might as well validate that the given TG matches; the architecture "does not require that the instruction invalidates any entries" if this is not true. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e455397fb57..3a7f5cf6f08 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4520,12 +4520,16 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, uint64_t value) { unsigned int page_size_granule, page_shift, num, scale, exponent; + /* Extract one bit to represent the va selector in use. */ + uint64_t select = sextract64(value, 36, 1); + ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true); TLBIRange ret = { }; page_size_granule = extract64(value, 46, 2); - if (page_size_granule == 0) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", + /* The granule encoded in value must match the granule in use. */ + if (page_size_granule != (param.using64k ? 3 : param.using16k ? 2 : 1)) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n", page_size_granule); return ret; } @@ -4537,7 +4541,7 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, ret.length = (num + 1) << (exponent + page_shift); - if (regime_has_2_ranges(mmuidx)) { + if (param.select) { ret.base = sextract64(value, 0, 37); } else { ret.base = extract64(value, 0, 37); From patchwork Wed Mar 2 20:52:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547538 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp44201imq; Wed, 2 Mar 2022 13:19:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJz6z9fBoC77mMHJkRFx7DATLPNXI0ik4oEmEWgHf9+rWy4BKAasGlsGWMp4S0xM/95ZrIVo X-Received: by 2002:a25:c103:0:b0:628:99a4:8af1 with SMTP id r3-20020a25c103000000b0062899a48af1mr5904669ybf.122.1646255947351; Wed, 02 Mar 2022 13:19:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646255947; cv=none; d=google.com; s=arc-20160816; b=KIGRZXxhHydl3jK+S6ulo0G0SOMQeyicNk5mgUMQQLQG5PA2rpdHduxBBK7StR7nNI +xEPHMNbIUzwD7FzZYxkRO2KnN20PVo56WrKNtDVj6bDJ3vTiZoz0W6CL0CXOMLDoISZ jcSAceP1Dy4zIoFcQtHvYSqI/veOR05JVTF+Ngq+X2htu+jAyM6mIKo8dGVeUv8S3hnJ x4yYjdpofXG1SgyesPu3/EzJFa4v/7E1ESX5ejsNPhZeXt989xAONJ94miwdoqbzOGPP RqPAb1anXAtJPOP519dx1iijLvejP4EDKtOoEH9QzT78k2Mrm1f/XT81G5rs7yIVUfkB j1xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=I6iTHbTYl4zCFK0q1Q7m/0Mob7a5vYQevNvaNiwiXcI=; b=Nsno2lDE3KWd28ZfXvg7WTtoxgu4FH1AP5knOMPw5hdpBkP+XtqDSgsF9ux5kpgPvE Xa5GD3xp1mvq+2FuyMvDVLBZCJqHSQH5xlcwAqw1S/EVRZcpeHGsNOBtQpwQU67uzZ5w RiNtzxlfFcSUZCibLUZpdzJ/qu9kQ0TFrKJ9gLMuzepJTn1WoNqVMsj8za+Nr/obhKyi pkD/FQlipdQ8l/auH2264XDRIMkBDr7PgwxnLeYNQf7AjhuI87Ktg0CKIo/975PGsTD7 3Y2PaFwCnkpVqz5ohthmo0vUJCncg44y8NblRYFppCtgViupOY1nJIgGfPuLzhfecDMA 2twQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RCUOuRjY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/26] target/arm: Advertise all page sizes for -cpu max Date: Wed, 2 Mar 2022 20:52:26 +0000 Message-Id: <20220302205230.2122390-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::434 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We support 16k pages, but do not advertize that in ID_AA64MMFR0. The value 0 in the TGRAN*_2 fields indicates that stage2 lookups defer to the same support as stage1 lookups. This setting is deprecated, so indicate support for all stage2 page sizes directly. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220301215958.157011-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d88662cef68..2fdc16bf182 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -796,6 +796,10 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64mmfr0; t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ cpu->isar.id_aa64mmfr0 = t; t = cpu->isar.id_aa64mmfr1; From patchwork Wed Mar 2 20:52:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547541 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp47293imq; Wed, 2 Mar 2022 13:24:24 -0800 (PST) X-Google-Smtp-Source: ABdhPJztu/HqdYhNy22HOUI1jT+3xN8gYEUelLjnKBakSoIbajIWv9zdw8y+un++x1EqxhoGja76 X-Received: by 2002:a81:48ca:0:b0:2dc:211e:b534 with SMTP id v193-20020a8148ca000000b002dc211eb534mr3307927ywa.84.1646256263967; Wed, 02 Mar 2022 13:24:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646256263; cv=none; d=google.com; s=arc-20160816; b=PqujH9T6TSreXa9lg2O/026NOxDj3y2Adew9qArWjXnyQYDRQr3Jn+mUMHvVrM5x8t HwG5EjqptyZqQU/c0uEpl76+9Eo8C0iUUtzXnQn2N1XQwcXa5lMcABUhJ8cWJIyQ/pZz adEfDjueG+7Hzj4RIVzLBEJKAFkAbkeOBvVWa/7taagNSX5eIXXHWveP3woMvMN0EN5S r8OCFmAQyVTvUs/shMP7LQt5K+LHIyATqxvj3V5yQ7OFYBhmND2ek/nQwyOVJ+hun2uJ 96N8Ttr3hJPxj4h15XyBP3kWlRc+xmudC6f9mx6SfR8G0l1qUcvsXlR9VSsx6LgphvZd UDtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/7Vp2M9cs0sUqfL04/OQn8hXX+h842EPxz0wSYudyes=; b=I3sW9Gk4XOI0O0QHR5XAAIS7ThklYUcSSoOmZtCeltXynQq7hMb+E+XdHI5yz99pTq OMHuKXdIpb8RxvIqVP5iIBF5FnwZc9wuAs3ulYbdE4MRF0T/oKY55Ic+kJSv2omhrGk/ PvQsRuVP2Sd+woAFWV98+9g9w/fbZUxG7iJecKHoAV9HV3AApIxO/IlhLVOXBMdwgh8C Q0eCHmKTPKtDR9fR9IFutUFxqmB1NQ/abVzuUXzMYaQ2qKuRld1q3YTHYpHSvhJlekWi pRe6Nkq+fKFpQOJdk6XsLe0w57oBakY6vWOLKLaxZUPC78fSOtKEedLDLXIQTsufWJH3 lTqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K5RVJ7KR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/26] target/arm: Implement FEAT_LPA2 Date: Wed, 2 Mar 2022 20:52:27 +0000 Message-Id: <20220302205230.2122390-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::436 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This feature widens physical addresses (and intermediate physical addresses for 2-stage translation) from 48 to 52 bits, when using 4k or 16k pages. This introduces the DS bit to TCR_ELx, which is RES0 unless the page size is enabled and supports LPA2, resulting in the effective value of DS for a given table walk. The DS bit changes the format of the page table descriptor slightly, moving the PS field out to TCR so that all pages have the same sharability and repurposing those bits of the page table descriptor for the highest bits of the output address. Do not yet enable FEAT_LPA2; we need extra plumbing to avoid tickling an old kernel bug. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 22 ++++++++ target/arm/internals.h | 2 + target/arm/helper.c | 102 +++++++++++++++++++++++++++++----- 4 files changed, 112 insertions(+), 15 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 0053ddce208..520fd39071e 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -25,6 +25,7 @@ the following architecture extensions: - FEAT_JSCVT (JavaScript conversion instructions) - FEAT_LOR (Limited ordering regions) - FEAT_LPA (Large Physical Address space) +- FEAT_LPA2 (Large Physical and virtual Address space v2) - FEAT_LRCPC (Load-acquire RCpc instructions) - FEAT_LRCPC2 (Load-acquire RCpc instructions v2) - FEAT_LSE (Large System Extensions) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c52d56f6699..24d9fff1705 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4284,6 +4284,28 @@ static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; } +static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; +} + +static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); +} + +static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; +} + +static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); +} + static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; diff --git a/target/arm/internals.h b/target/arm/internals.h index 00af41d7925..a34be2e4595 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1056,6 +1056,7 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) typedef struct ARMVAParameters { unsigned tsz : 8; unsigned ps : 3; + unsigned sh : 2; unsigned select : 1; bool tbi : 1; bool epd : 1; @@ -1063,6 +1064,7 @@ typedef struct ARMVAParameters { bool using16k : 1; bool using64k : 1; bool tsz_oob : 1; /* tsz has been clamped to legal range */ + bool ds : 1; } ARMVAParameters; ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, diff --git a/target/arm/helper.c b/target/arm/helper.c index 3a7f5cf6f08..088956eecf0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4546,6 +4546,14 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, } else { ret.base = extract64(value, 0, 37); } + if (param.ds) { + /* + * With DS=1, BaseADDR is always shifted 16 so that it is able + * to address all 52 va bits. The input address is perforce + * aligned on a 64k boundary regardless of translation granule. + */ + page_shift = 16; + } ret.base <<= page_shift; return ret; @@ -11081,8 +11089,13 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, const int grainsize = stride + 3; int startsizecheck; - /* Negative levels are never allowed. */ - if (level < 0) { + /* + * Negative levels are usually not allowed... + * Except for FEAT_LPA2, 4k page table, 52-bit address space, which + * begins with level -1. Note that previous feature tests will have + * eliminated this combination if it is not enabled. + */ + if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) { return false; } @@ -11223,8 +11236,9 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; - bool epd, hpd, using16k, using64k, tsz_oob; - int select, tsz, tbi, max_tsz, min_tsz, ps; + bool epd, hpd, using16k, using64k, tsz_oob, ds; + int select, tsz, tbi, max_tsz, min_tsz, ps, sh; + ARMCPU *cpu = env_archcpu(env); if (!regime_has_2_ranges(mmu_idx)) { select = 0; @@ -11238,7 +11252,9 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, hpd = extract32(tcr, 24, 1); } epd = false; + sh = extract32(tcr, 12, 2); ps = extract32(tcr, 16, 3); + ds = extract64(tcr, 32, 1); } else { /* * Bit 55 is always between the two regions, and is canonical for @@ -11248,6 +11264,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, if (!select) { tsz = extract32(tcr, 0, 6); epd = extract32(tcr, 7, 1); + sh = extract32(tcr, 12, 2); using64k = extract32(tcr, 14, 1); using16k = extract32(tcr, 15, 1); hpd = extract64(tcr, 41, 1); @@ -11257,24 +11274,51 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, using64k = tg == 3; tsz = extract32(tcr, 16, 6); epd = extract32(tcr, 23, 1); + sh = extract32(tcr, 28, 2); hpd = extract64(tcr, 42, 1); } ps = extract64(tcr, 32, 3); + ds = extract64(tcr, 59, 1); } - if (cpu_isar_feature(aa64_st, env_archcpu(env))) { + if (cpu_isar_feature(aa64_st, cpu)) { max_tsz = 48 - using64k; } else { max_tsz = 39; } + /* + * DS is RES0 unless FEAT_LPA2 is supported for the given page size; + * adjust the effective value of DS, as documented. + */ min_tsz = 16; if (using64k) { - if (cpu_isar_feature(aa64_lva, env_archcpu(env))) { + if (cpu_isar_feature(aa64_lva, cpu)) { + min_tsz = 12; + } + ds = false; + } else if (ds) { + switch (mmu_idx) { + case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: + if (using16k) { + ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu); + } else { + ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu); + } + break; + default: + if (using16k) { + ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu); + } else { + ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu); + } + break; + } + if (ds) { min_tsz = 12; } } - /* TODO: FEAT_LPA2 */ if (tsz > max_tsz) { tsz = max_tsz; @@ -11296,6 +11340,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, return (ARMVAParameters) { .tsz = tsz, .ps = ps, + .sh = sh, .select = select, .tbi = tbi, .epd = epd, @@ -11303,6 +11348,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, .using16k = using16k, .using64k = using64k, .tsz_oob = tsz_oob, + .ds = ds, }; } @@ -11528,10 +11574,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * VTCR_EL2.SL0 field (whose interpretation depends on the page size) */ uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); + uint32_t sl2 = extract64(tcr->raw_tcr, 33, 1); uint32_t startlevel; bool ok; - if (!aarch64 || stride == 9) { + /* SL2 is RES0 unless DS=1 & 4kb granule. */ + if (param.ds && stride == 9 && sl2) { + if (sl0 != 0) { + level = 0; + fault_type = ARMFault_Translation; + goto do_fault; + } + startlevel = -1; + } else if (!aarch64 || stride == 9) { /* AArch32 or 4KB pages */ startlevel = 2 - sl0; @@ -11585,10 +11640,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0 * or an AddressSize fault is raised. So for v8 we extract those SBZ * bits as part of the address, which will be checked via outputsize. - * For AArch64, the address field always goes up to bit 47 (with extra - * bits for FEAT_LPA placed elsewhere). AArch64 implies v8. + * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2; + * the highest bits of a 52-bit output are placed elsewhere. */ - if (arm_feature(env, ARM_FEATURE_V8)) { + if (param.ds) { + descaddrmask = MAKE_64BIT_MASK(0, 50); + } else if (arm_feature(env, ARM_FEATURE_V8)) { descaddrmask = MAKE_64BIT_MASK(0, 48); } else { descaddrmask = MAKE_64BIT_MASK(0, 40); @@ -11623,11 +11680,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12] - * of descriptor. Otherwise, if descaddr is out of range, raise - * AddressSizeFault. + * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of + * descaddr are in [9:8]. Otherwise, if descaddr is out of range, + * raise AddressSizeFault. */ if (outputsize > 48) { - descaddr |= extract64(descriptor, 12, 4) << 48; + if (param.ds) { + descaddr |= extract64(descriptor, 8, 2) << 50; + } else { + descaddr |= extract64(descriptor, 12, 4) << 48; + } } else if (descaddr >> outputsize) { fault_type = ARMFault_AddressSize; goto do_fault; @@ -11721,7 +11783,17 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, assert(attrindx <= 7); cacheattrs->attrs = extract64(mair, attrindx * 8, 8); } - cacheattrs->shareability = extract32(attrs, 6, 2); + + /* + * For FEAT_LPA2 and effective DS, the SH field in the attributes + * was re-purposed for output address bits. The SH attribute in + * that case comes from TCR_ELx, which we extracted earlier. + */ + if (param.ds) { + cacheattrs->shareability = param.sh; + } else { + cacheattrs->shareability = extract32(attrs, 6, 2); + } *phys_ptr = descaddr; *page_size_ptr = page_size; From patchwork Wed Mar 2 20:52:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547526 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp34737imq; Wed, 2 Mar 2022 13:05:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJyiLgxChAXGbI0whr0N9yiK2/SyqnVTFvVC/79xyA4Tlc8NTkU9mHBTPBFGxeDS1LjgtK95 X-Received: by 2002:a9d:2f61:0:b0:5af:5d99:29ed with SMTP id h88-20020a9d2f61000000b005af5d9929edmr17473542otb.142.1646255140253; Wed, 02 Mar 2022 13:05:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646255140; cv=none; d=google.com; s=arc-20160816; b=DV8VdJ24fE05DAF3uEunumuLW2aBFztjFLMeGxd9nZPw6FVXi85FPI3yl2BJvsINIp 7Fy6LTJ7CTwBfcIHS7Mw24dPU4Ov1kObQVd53zA0tWTu7QQoxs/Aq3gF3azqoVNYeFD1 h74lzLAZQiATDHgCrjaivma/oRVvUTKOW7MkUNjVcIpjqTpkpR7zzCbyXhGNnNXFHuuN 0UAz9XBpa3MVKbH+J5oE44ZtxgKGanHsMm8q3jnvYfRR6nHTq1rCksORM4ccAaXGsm4A npFwpQULaWUvv8/MIQeuIp6PjnzECqMaIFzi3QbM59yQ+OMDnUUKhxGmBnVheoGUXNbN cj/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=l/7EADgfQiDC7fxjtgYtq9X1xBlDjXtx1HGr/ZG8QYc=; b=UQ7/coYrGZTbUo/38IO9W/vgSvS3E7zrBcjx5+2YPcsM0eJAcOcrdsyVoxYAUDc2RR D1zQLtlNdogNulvzCtvcH0az4pHuockJ3QMqKngtO+3aoQ2tb96RDaXvyMpp/gx8qdxA WGOCO4x6hH0Xl4axlexT8j07y0ed4f5hK95kwT3najPW6ddg0ZKh2lWXR8N/38vdQeWM miiLndTmJo+Y4ewXvpU45K81YvwJy5Ddb8S6NYT2JS9I60CD/r5G3t0X/9loMqJIuNeM nR4Vr8xvUl1WSS+maHm86etOVH9Yi9Iu5Y1P0xscUWQ82yqX7Q3gm/7qTwpXNCbzzKH1 w4pA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ykA8VvGE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/26] target/arm: Report KVM's actual PSCI version to guest in dtb Date: Wed, 2 Mar 2022 20:52:28 +0000 Message-Id: <20220302205230.2122390-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::432 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When we're using KVM, the PSCI implementation is provided by the kernel, but QEMU has to tell the guest about it via the device tree. Currently we look at the KVM_CAP_ARM_PSCI_0_2 capability to determine if the kernel is providing at least PSCI 0.2, but if the kernel provides a newer version than that we will still only tell the guest it has PSCI 0.2. (This is fairly harmless; it just means the guest won't use newer parts of the PSCI API.) The kernel exposes the specific PSCI version it is implementing via the ONE_REG API; use this to report in the dtb that the PSCI implementation is 1.0-compatible if appropriate. (The device tree binding currently only distinguishes "pre-0.2", "0.2-compatible" and "1.0-compatible".) Signed-off-by: Peter Maydell Reviewed-by: Marc Zyngier Reviewed-by: Akihiko Odaki Reviewed-by: Richard Henderson Reviewed-by: Andrew Jones Message-id: 20220224134655.1207865-1-peter.maydell@linaro.org --- target/arm/kvm-consts.h | 1 + hw/arm/boot.c | 5 ++--- target/arm/kvm64.c | 12 ++++++++++++ 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index e770921ddc2..faacf96fdc7 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -95,6 +95,7 @@ MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_FN_PSCI_FEATURES); #define QEMU_PSCI_VERSION_0_1 0x00001 #define QEMU_PSCI_VERSION_0_2 0x00002 +#define QEMU_PSCI_VERSION_1_0 0x10000 #define QEMU_PSCI_VERSION_1_1 0x10001 MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP); diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 0eeef94ceb5..a47f38dfc90 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -488,9 +488,8 @@ static void fdt_add_psci_node(void *fdt) } qemu_fdt_add_subnode(fdt, "/psci"); - if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2 || - armcpu->psci_version == QEMU_PSCI_VERSION_1_1) { - if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2) { + if (armcpu->psci_version >= QEMU_PSCI_VERSION_0_2) { + if (armcpu->psci_version < QEMU_PSCI_VERSION_1_0) { const char comp[] = "arm,psci-0.2\0arm,psci"; qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); } else { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 64d48bfb19d..ccadfbbe72b 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -849,6 +849,7 @@ int kvm_arch_init_vcpu(CPUState *cs) uint64_t mpidr; ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + uint64_t psciver; if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE || !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { @@ -904,6 +905,17 @@ int kvm_arch_init_vcpu(CPUState *cs) } } + /* + * KVM reports the exact PSCI version it is implementing via a + * special sysreg. If it is present, use its contents to determine + * what to report to the guest in the dtb (it is the PSCI version, + * in the same 15-bits major 16-bits minor format that PSCI_VERSION + * returns). + */ + if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) { + cpu->psci_version = psciver; + } + /* * When KVM is in use, PSCI is emulated in-kernel and not by qemu. * Currently KVM has its own idea about MPIDR assignment, so we From patchwork Wed Mar 2 20:52:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547529 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp37125imq; Wed, 2 Mar 2022 13:08:46 -0800 (PST) X-Google-Smtp-Source: ABdhPJzw9I5IDKuGnHDoCwpMN0lvK8SScYXfSvkfHWzI9QJsQLRLjNFBEiy2/0KyDMwKgyvobwx7 X-Received: by 2002:a25:8243:0:b0:628:a926:38ff with SMTP id d3-20020a258243000000b00628a92638ffmr3491001ybn.36.1646255326589; Wed, 02 Mar 2022 13:08:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646255326; cv=none; d=google.com; s=arc-20160816; b=PWcWzTB6WDwgjrbU34FQLMhk6X0m1XbCL6iprUWRFDMdu5Yo9nDxh5itt2T6WRnGie TduE2rzC8zDvn+yAFbNowtncQPAwdAPodMeLQI8zyrAnuy6zbzbKpiybE0syvfl/QhHw 32kl4AzgoKy8yhpaysX5XkUh8f+mFD1GtFUR6U2SO8aeaNlehCIyDdT/ZEslauqOe7sW D/X37gqCkGso3VG56nzVGtNe6XSvTYK43602Wtj34Anc+rZ/qFIxgivddf4EJLoBP9lH QrQFFTeoYlQUDMMmVKGNI0NBrf0z4NSGPeDd8Q1VD9InOZUV/g7Wd/0OeDfJMIUX4ly7 tzEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1SN1vpTnpt9IXjnMGc+qCvooXM94wtAW18+rqDaYSkU=; b=HMwyDsW5likczgHxShxR/QJY+DLkm8AMOpKcE/3h9MLf3FlR2JSB2Ervoa1GVCAa6s HYNUOFj5Z47hi7bI2c9Yotcv0JMKvqYT4jKo2lVu7QA37giww0Rc44Vu7Hvmv/MZWN87 ffQcJBluXmBWofXsds3j+3dP6NoKJh5GkBqZh2IEGYtUO+b8CJa9uAaQlP+bBCgr/xbX Sngzd9twjgmeWb5Kh+0xOkF0pVQDuXALxpMTBaYKf+SJWd+3mlbnNDQA63WRmztG3SSR EPxOWuZtVa8svKd7dzw9l/sTRI2TCs4qIE895iswwCwVG8Z+GHbR0UDc0aFhvok4UBr4 0hRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=riUauh98; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/26] ui/cocoa.m: Fix updateUIInfo threading issues Date: Wed, 2 Mar 2022 20:52:29 +0000 Message-Id: <20220302205230.2122390-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::429 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The updateUIInfo method makes Cocoa API calls. It also calls back into QEMU functions like dpy_set_ui_info(). To do this safely, we need to follow two rules: * Cocoa API calls are made on the Cocoa UI thread * When calling back into QEMU we must hold the iothread lock Fix the places where we got this wrong, by taking the iothread lock while executing updateUIInfo, and moving the call in cocoa_switch() inside the dispatch_async block. Some of the Cocoa UI methods which call updateUIInfo are invoked as part of the initial application startup, while we're still doing the little cross-thread dance described in the comment just above call_qemu_main(). This meant they were calling back into the QEMU UI layer before we'd actually finished initializing our display and registered the DisplayChangeListener, which isn't really valid. Once updateUIInfo takes the iothread lock, we no longer get away with this, because during this startup phase the iothread lock is held by the QEMU main-loop thread which is waiting for us to finish our display initialization. So we must suppress updateUIInfo until applicationDidFinishLaunching allows the QEMU main-loop thread to continue. Signed-off-by: Peter Maydell Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Message-id: 20220224101330.967429-2-peter.maydell@linaro.org --- ui/cocoa.m | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/ui/cocoa.m b/ui/cocoa.m index a8f1cdaf926..5ed1495552a 100644 --- a/ui/cocoa.m +++ b/ui/cocoa.m @@ -522,8 +522,9 @@ QemuCocoaView *cocoaView; } } -- (void) updateUIInfo +- (void) updateUIInfoLocked { + /* Must be called with the iothread lock, i.e. via updateUIInfo */ NSSize frameSize; QemuUIInfo info; @@ -554,6 +555,25 @@ QemuCocoaView *cocoaView; dpy_set_ui_info(dcl.con, &info, TRUE); } +- (void) updateUIInfo +{ + if (!allow_events) { + /* + * Don't try to tell QEMU about UI information in the application + * startup phase -- we haven't yet registered dcl with the QEMU UI + * layer, and also trying to take the iothread lock would deadlock. + * When cocoa_display_init() does register the dcl, the UI layer + * will call cocoa_switch(), which will call updateUIInfo, so + * we don't lose any information here. + */ + return; + } + + with_iothread_lock(^{ + [self updateUIInfoLocked]; + }); +} + - (void)viewDidMoveToWindow { [self updateUIInfo]; @@ -1985,8 +2005,6 @@ static void cocoa_switch(DisplayChangeListener *dcl, COCOA_DEBUG("qemu_cocoa: cocoa_switch\n"); - [cocoaView updateUIInfo]; - // The DisplaySurface will be freed as soon as this callback returns. // We take a reference to the underlying pixman image here so it does // not disappear from under our feet; the switchSurface method will @@ -1994,6 +2012,7 @@ static void cocoa_switch(DisplayChangeListener *dcl, pixman_image_ref(image); dispatch_async(dispatch_get_main_queue(), ^{ + [cocoaView updateUIInfo]; [cocoaView switchSurface:image]; }); [pool release]; From patchwork Wed Mar 2 20:52:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 547542 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp48719imq; Wed, 2 Mar 2022 13:26:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJwzMpdg8/4eOzjAFxGOdR92U0ixiXGYZikNfiysZx50rjN9pVmjR2vZaPFt5JU+zr/1nonJ X-Received: by 2002:a81:cf02:0:b0:2d0:b68c:cf30 with SMTP id u2-20020a81cf02000000b002d0b68ccf30mr32697119ywi.510.1646256388745; Wed, 02 Mar 2022 13:26:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646256388; cv=none; d=google.com; s=arc-20160816; b=ZIyMCMSsR9q6hLCqkccdXsTeBFo0FPHi8VQaW8oNpXBiFsFJ9Fc6ZRZPdfzDQWTQT3 umRZPQVxALWxJCMPKFl+1pqBTVgd1LducG2a38N2p7HUpsIPwJRUbXev8VumxZO4A3aW U2l5uiW1aWGxIPS1tLUH20km9qrs4EDkb1n9QiaVHWU8PEKGH4E6HAmwlFEWh8LlMfz2 M4FwYEUw+QcoQfQHh95t08ioIlGtw2aSvB/iVU8B8frC+TNIPpHtiIW5xAHvR8RQAhgZ qs/40Vtud8OAT9vn6XUGOy4Zyfv4LDBbjkZOnJhozz4CTl6eICjGLEX6xDqvjyuttQnc m8Gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CZ5TYYnUc0e1hEuIV2ZzXVXaht7eB3zPn5/u5sClZ4M=; b=q2QxuZLhb+WSY9BW2adgZW3v/7A1JrIjrmtbRfHUNV/TLEUxO7+ZdiZ1L06ufaSCJt Dr02JS1wLb+vkyVBIYpN0j8G5/vgugkwjVx3nGVvwqi9G8Mv92zsF709cUqPo0ROOgEQ eI9M2a43r2Qadihot04ViD25Yok5m7KB/Z9yxYAI6V0EXuVuVlE3fSLYrjLT7LWsMwwF /yUELL3A/HZrdLY3vqcmUwlXsUL/3Lrr1miqF0b1W9sjW3Z+7bk30YkLP0FvrikvhVya 7ZeRGKqZvR9XzUspkrJC5h8+Frlwe07lQYtqnyKZsQZRieIR7jYd6AdPL8iA7eHUBjaF DT8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OscOzPwP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/26] ui/cocoa.m: Remove unnecessary NSAutoreleasePools Date: Wed, 2 Mar 2022 20:52:30 +0000 Message-Id: <20220302205230.2122390-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::436 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In commit 6e657e64cdc478 in 2013 we added some autorelease pools to deal with complaints from macOS when we made calls into Cocoa from threads that didn't have automatically created autorelease pools. Later on, macOS got stricter about forbidding cross-thread Cocoa calls, and in commit 5588840ff77800e839d8 we restructured the code to avoid them. This left the autorelease pool creation in several functions without any purpose; delete it. We still need the pool in cocoa_refresh() for the clipboard related code which is called directly there. Signed-off-by: Peter Maydell Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Message-id: 20220224101330.967429-3-peter.maydell@linaro.org --- ui/cocoa.m | 6 ------ 1 file changed, 6 deletions(-) diff --git a/ui/cocoa.m b/ui/cocoa.m index 5ed1495552a..b6e70e9134d 100644 --- a/ui/cocoa.m +++ b/ui/cocoa.m @@ -1976,8 +1976,6 @@ int main (int argc, char **argv) { static void cocoa_update(DisplayChangeListener *dcl, int x, int y, int w, int h) { - NSAutoreleasePool * pool = [[NSAutoreleasePool alloc] init]; - COCOA_DEBUG("qemu_cocoa: cocoa_update\n"); dispatch_async(dispatch_get_main_queue(), ^{ @@ -1993,14 +1991,11 @@ static void cocoa_update(DisplayChangeListener *dcl, } [cocoaView setNeedsDisplayInRect:rect]; }); - - [pool release]; } static void cocoa_switch(DisplayChangeListener *dcl, DisplaySurface *surface) { - NSAutoreleasePool * pool = [[NSAutoreleasePool alloc] init]; pixman_image_t *image = surface->image; COCOA_DEBUG("qemu_cocoa: cocoa_switch\n"); @@ -2015,7 +2010,6 @@ static void cocoa_switch(DisplayChangeListener *dcl, [cocoaView updateUIInfo]; [cocoaView switchSurface:image]; }); - [pool release]; } static void cocoa_refresh(DisplayChangeListener *dcl)