From patchwork Mon Dec 3 18:33:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 152721 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp7146069ljp; Mon, 3 Dec 2018 10:35:51 -0800 (PST) X-Google-Smtp-Source: AFSGD/XWrRAtKKqK3s1sNAG961ucdsw2jMi8CR2eo6mpgrvTn1guhDC/GrwMWNUkLo5v+VrPjxjM X-Received: by 2002:a17:902:2868:: with SMTP id e95mr17010178plb.317.1543862151047; Mon, 03 Dec 2018 10:35:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543862151; cv=none; d=google.com; s=arc-20160816; b=cQON5xHoiOFrkInEVWSdbdxvaFb6QujVfTRbd6UdMN0c7TLQ9XLJ9nfJblSTjg4JZl 4rRxb9m2GNQBSoCrjZrhv4IH49A+rIg3rWkyH6Z2arYoFTYzGVX30wcWi8Kox0vEZtWQ ljPjTAN/lmW+HWkjEBsuP6cLDKtSC6AWu2ZcazMkOFiW5uS7gwYS0PRnM/Dww5gzh2IR AhcPcBSMBc7Z4aLwHl5HHAcHdP+MqJdigvW1clBb8GDMQQorbZktXVqWt7GpM/zO9dKT pWki48HDoRuEZYgmhCsR6Up+3GmKugYhbGA4+S8ttAQaBk3hDQQFvckFi3po0WsdajWV 9jow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=bxN1Bkl0sGb272jZKTW/rlZvTSKF7fLwHr1tSNNpIkc=; b=SvVStIvOrdgFdXevkHiFOVqRS31KZmdeIa2EfCzWgFvCANiUYRTxe1pGZ6NYBLiemn QsPIJcqBUVW1nQIy9TZYet6mbsHVyPDXT2FlSBCvNMZ5RJoJzwIihGjjcvn2055fK45J uDkfVZjUCRnZDErBz9I2qMl8PtROVWvr87mnHnN00S5T+aqhm/YJ9cUwGTcSveyCvsEX pYLJtC+ijiACGkLsA+bKWAnqkEgfyWnClldqtWDjxja/jZWSgbb6tr4FOqbFWr8/+rGF LqOHhtv7IhAM0rrbt6yvLhT4/GWDBFiq2hb+TLBZoCURrEweDyGz2oHD+TgIJnNh/F/V ZpTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=esrzBH+T; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id f6sm20180969pfg.188.2018.12.03.10.35.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Dec 2018 10:35:35 -0800 (PST) From: Bjorn Andersson To: Michael Turquette , Stephen Boyd Cc: Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Marc Gonzalez , Amit Kucheria Subject: [PATCH v2 2/3] clk: qcom: gcc-msm8998: Disable halt check of UFS clocks Date: Mon, 3 Dec 2018 10:33:29 -0800 Message-Id: <20181203183330.2073-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181203183330.2073-1-bjorn.andersson@linaro.org> References: <20181203183330.2073-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Drop the halt check of the UFS symbol clocks, in accordance with other platforms. This makes clk_disable_unused() happy and makes it possible to turn the clocks on again without an error. Signed-off-by: Bjorn Andersson --- Changes since v1: - None drivers/clk/qcom/gcc-msm8998.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.18.0 diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index aed7f1f92614..792b431f9945 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2375,7 +2375,7 @@ static struct clk_branch gcc_ufs_phy_aux_clk = { static struct clk_branch gcc_ufs_rx_symbol_0_clk = { .halt_reg = 0x75014, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x75014, .enable_mask = BIT(0), @@ -2388,7 +2388,7 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = { static struct clk_branch gcc_ufs_rx_symbol_1_clk = { .halt_reg = 0x7605c, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x7605c, .enable_mask = BIT(0), @@ -2401,7 +2401,7 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = { static struct clk_branch gcc_ufs_tx_symbol_0_clk = { .halt_reg = 0x75010, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x75010, .enable_mask = BIT(0), From patchwork Mon Dec 3 18:33:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 152720 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp7145888ljp; Mon, 3 Dec 2018 10:35:41 -0800 (PST) X-Google-Smtp-Source: AFSGD/VWrLW5dZ9HcSq2Zi0BPhDF94TMjp+dOLTnmof+MpKj8SFDuoLebYMc2x10ZOERugkJi3jo X-Received: by 2002:a62:d148:: with SMTP id t8mr17366221pfl.52.1543862141155; Mon, 03 Dec 2018 10:35:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543862141; cv=none; d=google.com; s=arc-20160816; b=rRrA4s6lzCvVgu5uK488ZWLjdmaM3Z1FQC8kmmdIeuVdL+sioQFPo8mQemko0ICPdY 4ZtOIjgpAaFVY2iB+d5eBKGNMXoPpEQUfuVawdttQJThnUWfXqCnWnpZXZfao8TQVMdR vwlakR38hGK5K3iSqKC4CgxYzfAWHPWw4m2/cWw7xo9P4bkFNB9BaQMO7S5wBAvQiNJU IGEIW8erzblPQkPjxtY8goTmICA/nAL0PoY2ZPSjqQzR3kw2Ctz8vatZAeB4NdMv5YGr IblGhMRPEWUl1kCol3C2CwxYgb8jfvSCeAYpm2L8dt7aQfUoai3kxxn8R2ESsCB6fVEW Ux2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=OgjejpvvybYqYgPgu9pyioScdhfquILFMatsfrKQqTQ=; b=V7+MtnKDkRSVUNBrOFeAkVEiGOZ5LTeNUKO45HUQ1+OQsDWt7UXefbrufSr+hmggoV 6MdStnihI83FNaVG2q396lMu3/rvJjTEQq4wdraUpSrKGnDSLAKKseFovqKKuhc8bEG6 UmerOX2f8i4nzIghdJX0BQhChRBpfKq80XyJ0lM9gSBvCDAPdEbMV4FJ63ctkVwt9BPR o4Rqx7+8vn4UXFCBMHivKWoFJbkU1NslNmOXLdksBTMMOVbsWD4hewxq0AR6a6VL1Cb5 2YyiF+Z2sThhsKv4y7sYB+ORWM9zljzlJe1J2eKgjCsG9/T+qJOqg5SJtvjDOydU2GfC pXMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VMfCEGWv; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id f6sm20180969pfg.188.2018.12.03.10.35.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Dec 2018 10:35:36 -0800 (PST) From: Bjorn Andersson To: Michael Turquette , Stephen Boyd Cc: Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Marc Gonzalez , Amit Kucheria Subject: [PATCH v2 3/3] clk: qcom: gcc-msm8998: Add clkref clocks Date: Mon, 3 Dec 2018 10:33:30 -0800 Message-Id: <20181203183330.2073-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181203183330.2073-1-bjorn.andersson@linaro.org> References: <20181203183330.2073-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add clkref clocks for usb3, hdmi, ufs, pcie, and usb2. They are all sourced off CXO_IN, so parent them off "xo" until a proper link to the rpmcc can be described in DT. Signed-off-by: Bjorn Andersson --- Changes since v1: - None drivers/clk/qcom/gcc-msm8998.c | 75 ++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-msm8998.h | 5 ++ 2 files changed, 80 insertions(+) -- 2.18.0 diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index 792b431f9945..717210f61d27 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2515,6 +2515,76 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { }, }; +static struct clk_branch gcc_hdmi_clkref_clk = { + .halt_reg = 0x88000, + .clkr = { + .enable_reg = 0x88000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_hdmi_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_clkref_clk = { + .halt_reg = 0x88004, + .clkr = { + .enable_reg = 0x88004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_clkref_clk = { + .halt_reg = 0x88008, + .clkr = { + .enable_reg = 0x88008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_clkref_clk = { + .halt_reg = 0x8800c, + .clkr = { + .enable_reg = 0x8800c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_rx1_usb2_clkref_clk = { + .halt_reg = 0x88014, + .clkr = { + .enable_reg = 0x88014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rx1_usb2_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc pcie_0_gdsc = { .gdscr = 0x6b004, .gds_hw_ctrl = 0x0, @@ -2705,6 +2775,11 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, + [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr, + [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, + [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, + [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr, + [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, }; static struct gdsc *gcc_msm8998_gdscs[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 58a242e656b1..b3448800980a 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -180,6 +180,11 @@ #define USB30_MASTER_CLK_SRC 163 #define USB30_MOCK_UTMI_CLK_SRC 164 #define USB3_PHY_AUX_CLK_SRC 165 +#define GCC_USB3_CLKREF_CLK 166 +#define GCC_HDMI_CLKREF_CLK 167 +#define GCC_UFS_CLKREF_CLK 168 +#define GCC_PCIE_CLKREF_CLK 169 +#define GCC_RX1_USB2_CLKREF_CLK 170 #define PCIE_0_GDSC 0 #define UFS_GDSC 1