From patchwork Tue Mar 1 06:14:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 547373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93EFCC433F5 for ; Tue, 1 Mar 2022 06:15:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232541AbiCAGPr (ORCPT ); Tue, 1 Mar 2022 01:15:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232501AbiCAGPp (ORCPT ); Tue, 1 Mar 2022 01:15:45 -0500 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 859005AEE2 for ; Mon, 28 Feb 2022 22:15:04 -0800 (PST) Received: by mail-lj1-x22e.google.com with SMTP id l12so8572299ljh.12 for ; Mon, 28 Feb 2022 22:15:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3Nw/PZZp9GfNSMIv9549XL/wsJXLsQ4Ptmoo4mdy4Oc=; b=g24I4eMqi1idwcPMehHy9foDfLPbpl+cYj0LR9HAzhi4n5dfqjTX+c9+244EqqgXc5 9lH0AQb4I+w+N2rOI9nvFkJQUSsZoUkfGcbe1Hpwd6QnDFPCIfRfVV+q+tfrse4huSdv 2wfP2LGeuhL6mm0A3bWX/0h7zeOUuUMRGFJTzUbotIxbxx4+6LreMSRjW16r0kfY9cfB PW7GDuxYAy2fluS3bthj/FpaE/2HVjXD2C48ZdxeY0MnIinrBNSj0G6ipJCId/Bg6FNQ ROvZ4PNgsaKqC3zV72/EKR3Asas50Gtvihgt3C8aGnCtvFqwJXmMCH8TmblM8Pk3jqTD VM5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3Nw/PZZp9GfNSMIv9549XL/wsJXLsQ4Ptmoo4mdy4Oc=; b=rxflKB+5dB3fe94/EdP6yINobqgo1EBMSBHq86l6hq5gVwRZUJWntBjk0nX6hEt8bb 80U0ZNODHP4hgVGY5EqKAkCFA/HheGrPMk+gb6Ib83lALE92vVj0iYZXOev+zNhQGGEv e/DG2+42/pUIToQAlkqTpGLP8zu83RMTSgN9YKfERmXu2/z0UXFHLrW+v9sPqyHlKBfe BF04LjVam/vdiefDxuAuKccx9TsnpknsEmWtcyCQWCX62NstdcL6Z4yzqQnNmWb92daV hw0VCZYK6Zo5+8W6PvQdw/KFNf1N8LETjXVcoxqmeMRv0GEsUyByyrPiuH4HrVY6hlzh Inhg== X-Gm-Message-State: AOAM53090wGNpIKlNJOELBorp/OaOmQJi4CYGpGdVS9qz6KVtIFxxmRw 8eiOtZ2s1wrpZdPcJtX4v8iz9MFD992JFg== X-Google-Smtp-Source: ABdhPJzsQ0E0rw3ZMRuifY5Li+BTwUggXDTG0WBfDdc+B8oqGzQ1giP47k4nvkXV3YyiO9pkJQDL9A== X-Received: by 2002:a05:651c:1a29:b0:246:40e7:6360 with SMTP id by41-20020a05651c1a2900b0024640e76360mr16654441ljb.61.1646115302864; Mon, 28 Feb 2022 22:15:02 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id f15-20020ac25ccf000000b004442220c67fsm1318898lfq.27.2022.02.28.22.15.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 22:15:02 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/7] arm64: dts: qcom: sm8450: add PCIe0 PHY node Date: Tue, 1 Mar 2022 09:14:54 +0300 Message-Id: <20220301061500.2110569-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220301061500.2110569-1-dmitry.baryshkov@linaro.org> References: <20220301061500.2110569-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree node for the first PCIe PHY device found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 42 ++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 934e29b9e153..38ff1bb532cd 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -683,8 +683,12 @@ gcc: clock-controller@100000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clock-names = "bi_tcxo", "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&pcie0_lane>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "pcie_0_pipe_clk", + "sleep_clk"; }; qupv3_id_0: geniqup@9c0000 { @@ -750,6 +754,40 @@ i2c14: i2c@a98000 { }; }; + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; + reg = <0 0x01c06000 0 0x200>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: lanes@1c06200 { + reg = <0 0x1c06e00 0 0x200>, /* tx */ + <0 0x1c07000 0 0x200>, /* rx */ + <0 0x1c06200 0 0x200>, /* pcs */ + <0 0x1c06600 0 0x200>; /* pcs_pcie */ + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + }; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sm8450-config-noc"; reg = <0 0x01500000 0 0x1c000>; From patchwork Tue Mar 1 06:14:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 547372 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20FB2C433EF for ; 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Mon, 28 Feb 2022 22:15:03 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 3/7] arm64: dts: qcom: sm8450: add PCIe1 PHY node Date: Tue, 1 Mar 2022 09:14:56 +0300 Message-Id: <20220301061500.2110569-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220301061500.2110569-1-dmitry.baryshkov@linaro.org> References: <20220301061500.2110569-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree node for the second PCIe PHY device found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 38 ++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 47db7759e543..45c0bf2b7fd2 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -685,9 +685,11 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&pcie0_lane>, + <&pcie1_lane>, <&sleep_clk>; clock-names = "bi_tcxo", "pcie_0_pipe_clk", + "pcie_1_pipe_clk", "sleep_clk"; }; @@ -863,6 +865,42 @@ pcie0_lane: lanes@1c06200 { }; }; + pcie1_phy: phy@1c0f000 { + compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; + reg = <0 0x01c0f000 0 0x200>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie1_lane: lanes@1c0e000 { + reg = <0 0x1c0e000 0 0x200>, /* tx */ + <0 0x1c0e200 0 0x300>, /* rx */ + <0 0x1c0f200 0 0x200>, /* pcs */ + <0 0x1c0e800 0 0x200>, /* tx */ + <0 0x1c0ea00 0 0x300>, /* rx */ + <0 0x1c0f400 0 0xc00>; /* pcs_pcie */ + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + }; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sm8450-config-noc"; reg = <0 0x01500000 0 0x1c000>; From patchwork Tue Mar 1 06:14:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 547371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D383C433EF for ; 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Mon, 28 Feb 2022 22:15:05 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 5/7] arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY device Date: Tue, 1 Mar 2022 09:14:58 +0300 Message-Id: <20220301061500.2110569-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220301061500.2110569-1-dmitry.baryshkov@linaro.org> References: <20220301061500.2110569-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable PCIe0 PHY on the SM8450 QRD device. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 9526632d4029..7b6324969a4e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -342,6 +342,12 @@ vreg_l6e_1p2: ldo6 { }; }; +&pcie0_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Tue Mar 1 06:15:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 547370 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95FDCC43219 for ; Tue, 1 Mar 2022 06:15:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232550AbiCAGPx (ORCPT ); Tue, 1 Mar 2022 01:15:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232554AbiCAGPt (ORCPT ); Tue, 1 Mar 2022 01:15:49 -0500 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B52866210 for ; Mon, 28 Feb 2022 22:15:09 -0800 (PST) Received: by mail-lf1-x129.google.com with SMTP id t13so13142159lfd.9 for ; Mon, 28 Feb 2022 22:15:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h+L3faZOti6LGcPoY6+HqkRU/QXPVzbe+S6GftVJRjc=; b=jC2WabLPwyJ9Uixvql18TZWriXIK6G6CebSQJRe2lm9hiXdDBiRk8pz2zKAdC0XhZD qexQ5pTK0OCbHT6Tv+jhjNnE7PRiK8Py1tTWdfB7r4ADwzHIKWyfS1eOSfFWKr0YhGXd ZfyhWmfYjTtsAFcMEAxUplb7O+m9WG2Y/rRGim/tnFHAV6N/lKHZmGwUrhFTP1m36Pi/ HMl3MQFBtxKkDDMU42maXaGX/ZzoF2AtAay3I5iHzL1NNSwe1UNZEDqnJacqfR9b0lW7 DedHh5jVY0oAhvBG+ukQH8nVD+CtNz+gwvrzSUlnvD1BUX9s6UoZV+4cbEFiHwUDJzFP 0rOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h+L3faZOti6LGcPoY6+HqkRU/QXPVzbe+S6GftVJRjc=; b=fq2MpPZ6U5/k1Dwb2leR0o8FQYAwTyT+AIrI+cU3s2N3DtV3OVhDUs/ONJHCuB5Ny1 SeuVfKVpnOg18uvGgIk+VznGpUQO2zRBgDKsU+cs1ejtSew95qlO9yhUu4i2mGDaqRnM OaiBuxcHZVREbwb/RuP9RKnc/T+Fd5Fhz4JMTvlF0HjqOukLh0i9JfE3BgT0dPYi/VNo D9tnzCGkh6R2Y3Ou1/zVrtLwus/y0qfPZr6FD/isC4XQOJIVpyyV+Kr9Z5FNQ9XJYfCO nWsHdpucVyT3kbd1FyaQ9YTcb4BAT3xtYhhTRHCJZ2CqrzELn1ZSGvexynT0JmD/WnAd B5UA== X-Gm-Message-State: AOAM531Wc9YlTG+bNtblbyuNKDM9hgmCVm2s8321pDOPGvY3Ahh7dLKO Ync49985O7w9bG4EGGtosBYbqw== X-Google-Smtp-Source: ABdhPJzVG2+ic7rlCnFSlHvY5KJREy6Zh9cKvS8YgzMjT/BUdo7wp2HTchOJBqjVJ6VaI76BZpTx6A== X-Received: by 2002:a05:6512:34d4:b0:442:a9c5:8e37 with SMTP id w20-20020a05651234d400b00442a9c58e37mr14925102lfr.362.1646115307434; Mon, 28 Feb 2022 22:15:07 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id f15-20020ac25ccf000000b004442220c67fsm1318898lfq.27.2022.02.28.22.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 22:15:07 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: qcom: sm8450-hdk: add pcie nodes Date: Tue, 1 Mar 2022 09:15:00 +0300 Message-Id: <20220301061500.2110569-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220301061500.2110569-1-dmitry.baryshkov@linaro.org> References: <20220301061500.2110569-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree nodes for PCIe0/PCIe1 controllers and corresponding PHYs. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index f0fcb1428449..5d6de95a3a84 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -349,6 +349,27 @@ vreg_l7e_2p8: ldo7 { }; }; +&pcie0 { + status = "okay"; + max-link-speed = <2>; +}; + +&pcie0_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l2h_0p91>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + &qupv3_id_0 { status = "okay"; };