From patchwork Mon Dec 3 13:18:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 152699 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6801598ljp; Mon, 3 Dec 2018 05:19:06 -0800 (PST) X-Google-Smtp-Source: AFSGD/VlSE2jx8kYu426CtzbRidjtSd7I6/91oE+2r5MKUsZwbundblJ8IySHj+etm4bXk0pYTTw X-Received: by 2002:a63:f111:: with SMTP id f17mr13217273pgi.236.1543843146727; Mon, 03 Dec 2018 05:19:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543843146; cv=none; d=google.com; s=arc-20160816; b=DFKqgWdXWuOp1eTXfYRrk4iVwTd4XLtrFOmvnAZsb6HD43tvcdE8TP43/fVYcj8B5W QorxZ4YdMf5TEH6O2ghha0ZpYYECI3GzZB9mKpdg7GU651RmlgzoEXaSGbrlxbpbn1ab yYugkDgwVn8bgnLI7+2ieef5860mxtOEzU68/ZBlN3Xi1nuBRhErf64FkPITQlTX4W70 vrMuapZ/bJP57k473TY2cmGhA0kL/ci961ieHCMal9WCUHD+bPJyjUaz5yni9MS7XzBp BmV4238hJx4RQyslUBMG8aLQXkhA9U1KtKIF1YaZkvtbRQBNxN7nN8AX0uVQQRE8/ZD0 0Ujg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nPWsn16HihaqS/gJnLipzT9xenTcdp/r8TBEXkQVJFg=; b=o4l6dWBDyEUx7O4eIptdfmy8EtMJgQ4j/8e19C417G5DeAoAfrlFBGQaFOOaAqrAdJ Kpmp2bhwyrPyGXc8QO6FsbJ67200knJEDqmJeo+S3MwPgfneFwBTCu6I3t+Yu+UQPyzg 12kF4Y+ol++iOpNGzLrwI0JOft7B82zsDfkA0F4SvYHGYk3ZngMxsYW1htbAwpxMrdJD oHS9bDis4Oq9xnVqQnwpRe0vzBvSak+BxUlJcApOS45Qay0mClygXhPQxboH4OXGlMzw LW1/ehgDLS++jBKiBjFzfxyRlOuibUApBMKM1iv6qlU+h+3C2Qbci7WyzHKxCuH4ovHj bX4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b="vNGt/j06"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Mon, 03 Dec 2018 05:19:01 -0800 (PST) Received: from boomer.local ([2a01:e34:eeb6:4690:106b:bae3:31ed:7561]) by smtp.googlemail.com with ESMTPSA id n19sm6371063wmh.26.2018.12.03.05.19.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 05:19:01 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Carlo Caione , Kevin Hilman Cc: Jerome Brunet , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] dt-bindings: clk: meson: add ao controller clock inputs Date: Mon, 3 Dec 2018 14:18:48 +0100 Message-Id: <20181203131850.31388-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181203131850.31388-1-jbrunet@baylibre.com> References: <20181203131850.31388-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the clock inputs of amlogic AO clock controller Reviewed-by: Stephen Boyd Signed-off-by: Jerome Brunet --- .../devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.19.1 diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt index 3a880528030e..c480db8f4793 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt @@ -11,6 +11,11 @@ Required Properties: - GXM (S912) : "amlogic,meson-gxm-aoclkc" - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" followed by the common "amlogic,meson-gx-aoclkc" +- clocks: list of clock phandle, one for each entry clock-names. +- clock-names: should contain the following: + * "xtal" : the platform xtal + * "mpeg-clk" : the main clock controller mother clock (aka clk81) + * "ext-32k" : external 32kHz reference if any (optional) - #clock-cells: should be 1. @@ -40,8 +45,9 @@ ao_sysctrl: sys-ctrl@0 { compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; -}; Example: UART controller node that consumes the clock and reset generated by the clock controller: From patchwork Mon Dec 3 13:18:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 152701 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6801750ljp; Mon, 3 Dec 2018 05:19:16 -0800 (PST) X-Google-Smtp-Source: AFSGD/XkkbqPKxIKAmRapP44IabWHv1wZrpXAg8IQsXszjikfUiM0Q7UCYgc1ncM40+MbFPhrR+P X-Received: by 2002:a17:902:4222:: with SMTP id g31mr15823197pld.240.1543843155929; Mon, 03 Dec 2018 05:19:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543843155; cv=none; d=google.com; s=arc-20160816; b=HAIxnASJCJTUuxmIpcviCx2w9aZjvNo6hg/GAxhXVQ6G/HT29uTeUZS+fSPHvkbnOP 4JWJ9wlgty4jG2nkXoHjv74M3AkL4n8tMGH0Hrrsi6kUhZZIbQFyAV15m78ZXHUm7jaB uSoqslLfwZGcRS7+UVtJG3akZ8+egpgpR9ELuGxiwoFRhrhmB+2Amei1fcaSMmzIafWn IhtEqKGUtdVcAHfa1GNFAAi+omrzcqHEzgoeryxrnNGr+EiK5bOt6GvOw9P83jEGtNTT o93HEctY2m2Rw9jvUBTVx3QIeQLFt7iG98h9TDrAXD0qRWkwnkT0oVtnDH4njemJFyZv zzsA== ARC-Message-Signature: i=1; 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Mon, 03 Dec 2018 05:19:03 -0800 (PST) Received: from boomer.local ([2a01:e34:eeb6:4690:106b:bae3:31ed:7561]) by smtp.googlemail.com with ESMTPSA id n19sm6371063wmh.26.2018.12.03.05.19.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 05:19:02 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Carlo Caione , Kevin Hilman Cc: Jerome Brunet , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] dt-bindings: clk: meson: add main controller clock input Date: Mon, 3 Dec 2018 14:18:49 +0100 Message-Id: <20181203131850.31388-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181203131850.31388-1-jbrunet@baylibre.com> References: <20181203131850.31388-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the clock input of the main clock controller Signed-off-by: Jerome Brunet --- .../devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 5 +++++ 1 file changed, 5 insertions(+) -- 2.19.1 diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e950599566a9..a6871953bf04 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -9,6 +9,9 @@ Required Properties: "amlogic,gxbb-clkc" for GXBB SoC, "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. +- clocks : list of clock phandle, one for each entry clock-names. +- clock-names : should contain the following: + * "xtal": the platform xtal - #clock-cells: should be 1. @@ -31,6 +34,8 @@ sysctrl: system-controller@0 { clkc: clock-controller { #clock-cells = <1>; compatible = "amlogic,gxbb-clkc"; + clocks = <&xtal>; + clock-names = "xtal"; }; }; From patchwork Mon Dec 3 13:18:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 152700 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6801667ljp; Mon, 3 Dec 2018 05:19:11 -0800 (PST) X-Google-Smtp-Source: AFSGD/XEhtrf96Sw67LujiN1Db/Vopln4NADjSk22QPPHnfz04oBAMjigKEfSwQXKb/m9taqEKUI X-Received: by 2002:a17:902:5a86:: with SMTP id r6mr15283152pli.301.1543843151397; Mon, 03 Dec 2018 05:19:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543843151; cv=none; d=google.com; s=arc-20160816; b=toUDt86g+2gnX4FAR6ebUYwLHhLv87oQxicv9vxn4hpNLSLqGsQoWuxZKSdMsg0kze EhS8O8CZQj1zyNbjSGWT+0fGJEHOgZHBb6YllWDEdd1EuugOBkCtwIiskWyvugivmdac dEpjky80cfRG1iMAHeX+icYYD54Mmj32GYO64rt5c5vH+wOgXDVIbvtooLgzCIjXXXLB Ro5G4XdJ+sjPLABSNsaO1/tMfWnSgaIdA2KWR6drT1vSNQMomxmU4Zl4z4XLSVwDjri4 nVoWVTbHN/uFpYMVI0OuMywzObBj7nYqCsHh1M/U3ytasJ59bfyDM97mxHCdYIwO7Y6Z oBVw== ARC-Message-Signature: i=1; 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Mon, 03 Dec 2018 05:19:04 -0800 (PST) Received: from boomer.local ([2a01:e34:eeb6:4690:106b:bae3:31ed:7561]) by smtp.googlemail.com with ESMTPSA id n19sm6371063wmh.26.2018.12.03.05.19.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 05:19:04 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Carlo Caione , Kevin Hilman Cc: Jerome Brunet , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] arm64: dts: meson: add clock controller clock inputs Date: Mon, 3 Dec 2018 14:18:50 +0100 Message-Id: <20181203131850.31388-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181203131850.31388-1-jbrunet@baylibre.com> References: <20181203131850.31388-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the clock inputs of the clock controllers Signed-off-by: Jerome Brunet --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 4 ++++ 3 files changed, 12 insertions(+) -- 2.19.1 diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 5f512c91471e..5f3ac275f1ab 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1089,6 +1089,8 @@ clkc: clock-controller { compatible = "amlogic,axg-clkc"; #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; }; }; }; @@ -1334,6 +1336,8 @@ compatible = "amlogic,meson-axg-aoclkc"; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 6796d250985a..a7b883ced0a8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -299,6 +299,8 @@ &clkc_AO { compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; &efuse { @@ -334,6 +336,8 @@ clkc: clock-controller { compatible = "amlogic,gxbb-clkc"; #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index ed278097825b..d5c3d78aafeb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -260,6 +260,8 @@ &clkc_AO { compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc"; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; &gpio_intc { @@ -284,6 +286,8 @@ clkc: clock-controller { compatible = "amlogic,gxl-clkc"; #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; }; };