From patchwork Mon Feb 28 09:42:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 546805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A67BCC433FE for ; Mon, 28 Feb 2022 09:42:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234396AbiB1JnY (ORCPT ); Mon, 28 Feb 2022 04:43:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234403AbiB1JnY (ORCPT ); Mon, 28 Feb 2022 04:43:24 -0500 Received: from mail-ot1-x329.google.com (mail-ot1-x329.google.com [IPv6:2607:f8b0:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F8446302 for ; Mon, 28 Feb 2022 01:42:46 -0800 (PST) Received: by mail-ot1-x329.google.com with SMTP id l21-20020a056830239500b005afd2a7eaa2so6170553ots.9 for ; Mon, 28 Feb 2022 01:42:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZOaq/RArOsIMDEytI6Sz1pnZYzBz3vUl5NUCRG67IW0=; b=tCKMHUU8QAqKTHwdEi5K8/K7yjrn7fm6WB/AaoaEQI6tkUpy5tW0WXN0c+xY9Wi4eJ x/2DwjrGbGUG4RKEmxOeEP4UJzXT31aFaGSjO3VDmZ41dPnA9lA4DvyCwFiroyue0Wus MiQrRH9NTjxL2rZt9GcERXjF19Gsjh6UQp9jwYgjC9F/0Ph+2RIEYnGOFkDZYlmeZPcu ZXWbxA09SAsx3NXpdUNxEaQvxuMSGUWI062WthWWaQnnZ4bBVaGfgClQmNDOGu9U6Dh/ GK7TtuNQPyPZV2nGKSASb82XI4sjsqO9G4g7dLQ3Xgp/+VRD49LbiOgfd+2V9amTc/kJ 2SwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZOaq/RArOsIMDEytI6Sz1pnZYzBz3vUl5NUCRG67IW0=; b=U7N3RYiZS/K5ZRe2gjw9dK+11ABPpQPKxyeFLCqlpiJb+k3eKmfeNQp+lZOgMUdWaj lEzGb5F3pF/OzQP0dtHaZx56vAcq0Hm+qBe18h5EHlWnehFsnSv80Vo1zDVPFo3eFa0i 0nK1tJ7WHXg2GXECbGzVP+r4SdV9HiFShhnwioA03WN/7JQr73uPBb206EOQd2y4OPnr tbxIPrR/a4DTraWHGfJ8bTR6HE0FikwIrtewHJPCFVT+MUqMeQX8fxLwzOZRSvBJWQCl BsOXXMk1vxVtYrTc7uJZJRzs+DLBcKclkHCYXft7WOK0z49g92q+9V8UAQkomJMK1kPk ZIMg== X-Gm-Message-State: AOAM530Hkv8Ep8T5J+dD5AQ8ZpKyJT3mjKOUFHv1sjFiIpo41gztg+Lz Hh/1QpZKDfHOWFJQEYoekaPyKw== X-Google-Smtp-Source: ABdhPJxEMD3OsXSa/J6FmMVubYEnSdaZt/5m8UwSnv4J/cr7HnlImwQ9KxEgWcFI2v0cqErwRyFD0Q== X-Received: by 2002:a05:6830:1d92:b0:5af:4018:c8bf with SMTP id y18-20020a0568301d9200b005af4018c8bfmr8397412oti.349.1646041365638; Mon, 28 Feb 2022 01:42:45 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id bx10-20020a0568081b0a00b002d70da1ac54sm5936852oib.19.2022.02.28.01.42.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 01:42:45 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , kvm-riscv@lists.infradead.org, Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [RFC PATCH 2/6] RISC-V: Enable sstc extension parsing from DT Date: Mon, 28 Feb 2022 01:42:29 -0800 Message-Id: <20220228094234.3773153-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220228094234.3773153-1-atishp@rivosinc.com> References: <20220228094234.3773153-1-atishp@rivosinc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ISA extension framework now allows parsing any multi-letter ISA extension. Enable that for sstc extension. Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 4 +++- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 691fc9c8099b..7335e9138fb7 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -51,6 +51,7 @@ extern unsigned long elf_hwcap; * available logical extension id. */ enum riscv_isa_ext_id { + RISCV_ISA_EXT_SSTC = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 031ad15a059f..7568c7084a52 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -71,6 +71,7 @@ int riscv_of_parent_hartid(struct device_node *node) } static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index f3a4b0619aa0..1d8a06575cea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -192,8 +192,10 @@ void __init riscv_fill_hwcap(void) if (!ext_long) { this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; set_bit(*ext - 'a', this_isa); - } + } else { + SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); #undef SET_ISA_EXT_MAP + } } /* From patchwork Mon Feb 28 09:42:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 546804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 822C9C433F5 for ; Mon, 28 Feb 2022 09:43:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234464AbiB1Jng (ORCPT ); Mon, 28 Feb 2022 04:43:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234421AbiB1Jnb (ORCPT ); Mon, 28 Feb 2022 04:43:31 -0500 Received: from mail-oo1-xc2c.google.com (mail-oo1-xc2c.google.com [IPv6:2607:f8b0:4864:20::c2c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E095BBF5B for ; Mon, 28 Feb 2022 01:42:49 -0800 (PST) Received: by mail-oo1-xc2c.google.com with SMTP id s203-20020a4a3bd4000000b003191c2dcbe8so18103092oos.9 for ; Mon, 28 Feb 2022 01:42:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OFx1LkRnyPSZoRPt++yRCZ/X7QAcbDXb7DbJRNFpb9w=; b=E/WAf0za9GRV++42YJoQEmv1RWq2LbVhjKreactOPjFdu6G631daU/9dPqnPLVnznt bCPt1pXZMtrMRJIMbxTHeVyRydO7cNrFhuYktKG/FE9DMUiPVA12wYyRxQ++M6on2BoY DteC19AIVn6jX9jfv5nHAPQmgPq5N+QIDpFqbxK0wczRdEZd0XLuxYwP9Ko1mO88TsA5 ZuDp+MRF0MLr4nb9P9dxN0lqLo+B6ZqrWGNfvweHqem44F6PsgKg0XkVMcr5gstVSY6q cFwCu8x2HfVezTQ6JqnF0weCzK0oytliORDfkuUHSK/fN+sRqUbkpVDfbYiQd4X/ZykY lYwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OFx1LkRnyPSZoRPt++yRCZ/X7QAcbDXb7DbJRNFpb9w=; b=pyU8g/nL18tVgHplzFptkce+BbI2ECqvbbLDE1jnd9I2UFq8b3x1JIZvaHlN4gqgRH JfHanoH96cKIeYfdqpZfb0ONEHYY2YbMfkat22+dMTgTWNNgllaDNmFoSQAF2IvOws9i p+/4afc43rNUOdFq1oAIwsbEmrfM/4WlqIVpLWAQCliBF4DK+I1a0GhfOFqnKe9u917l GpZbc+jdo1fZdU3hOqpObCqBdLRc3r9EuoSfUsGDWY6VpPsTpicQKmSGz4zGO/Z4csPQ yRnQvcoQuSBhPhHXoXP0iXKxW0+1+gBwBt81ygEr69aFXgNJIcMGxOxLbGSek140ZmfV 9Yuw== X-Gm-Message-State: AOAM530pSon1UEsY2le48CdmSDOjE3cfpjlP7NCreUPrcwNiQCrtu223 jH9B6meMMiKJqLyqM82lhjxKog== X-Google-Smtp-Source: ABdhPJzhIKtfZEIAafRI4JUqKJcTAu7eH4KpEJ6cvcqwvvcRPwCt5Hxo74efVrqx/IfP4dRTJdimiw== X-Received: by 2002:a05:6870:b7b4:b0:d6:e56e:b85c with SMTP id ed52-20020a056870b7b400b000d6e56eb85cmr7507039oab.327.1646041369323; Mon, 28 Feb 2022 01:42:49 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id bx10-20020a0568081b0a00b002d70da1ac54sm5936852oib.19.2022.02.28.01.42.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 01:42:48 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , kvm-riscv@lists.infradead.org, Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [RFC PATCH 4/6] RISC-V: Restrict the isa field in config register to base extensions Date: Mon, 28 Feb 2022 01:42:31 -0800 Message-Id: <20220228094234.3773153-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220228094234.3773153-1-atishp@rivosinc.com> References: <20220228094234.3773153-1-atishp@rivosinc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The isa field in config register is meant only for single letter base ISA extensions. Multi-letter extensions can not be encoded here as it will exceed the size of ULONG easily in future. Only allow single letter extensions (0-25) to be encoded in that field. Signed-off-by: Atish Patra --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu.c | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index f808ad1ce500..aa9f5a5c57d8 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -47,6 +47,7 @@ struct kvm_sregs { /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ struct kvm_riscv_config { + /* This is a bitmap of all the single letter base ISA extensions */ unsigned long isa; }; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 624166004e36..7a07dba504f8 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -182,13 +182,14 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu, KVM_REG_SIZE_MASK | KVM_REG_RISCV_CONFIG); unsigned long reg_val; + unsigned long isa_mask = GENMASK(25, 0); if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) return -EINVAL; switch (reg_num) { case KVM_REG_RISCV_CONFIG_REG(isa): - reg_val = vcpu->arch.isa; + reg_val = vcpu->arch.isa & isa_mask; break; default: return -EINVAL; @@ -209,6 +210,7 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, KVM_REG_SIZE_MASK | KVM_REG_RISCV_CONFIG); unsigned long reg_val; + unsigned long isa_mask = GENMASK(25, 0); if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) return -EINVAL; @@ -219,7 +221,7 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, switch (reg_num) { case KVM_REG_RISCV_CONFIG_REG(isa): if (!vcpu->arch.ran_atleast_once) { - vcpu->arch.isa = reg_val; + vcpu->arch.isa = reg_val & isa_mask; vcpu->arch.isa &= riscv_isa_extension_base(NULL); vcpu->arch.isa &= KVM_RISCV_ISA_ALLOWED; kvm_riscv_vcpu_fp_reset(vcpu); From patchwork Mon Feb 28 09:42:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 546803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFC84C433FE for ; Mon, 28 Feb 2022 09:43:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232877AbiB1Jnn (ORCPT ); Mon, 28 Feb 2022 04:43:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234457AbiB1Jnf (ORCPT ); Mon, 28 Feb 2022 04:43:35 -0500 Received: from mail-oi1-x234.google.com (mail-oi1-x234.google.com [IPv6:2607:f8b0:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6C8A13D2F for ; Mon, 28 Feb 2022 01:42:53 -0800 (PST) Received: by mail-oi1-x234.google.com with SMTP id q5so12650665oij.6 for ; Mon, 28 Feb 2022 01:42:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G0qKKKRBgRaNdfPc1uehv7o+JmYHFw6tz68sq2JtWhM=; b=LWEQsBbo0uuMsIqIyvljJA9+TbP+mkMr4T0oW+c6sdKdUCVhfLia2668el+/EC7L/J 8mPxHKLVNSjfchNi4UtYsZkeMMztoi2FeQ6TRYpg0fj6DILrGNVW5BluJ7OqS/2VAwfE zsXBTA0/C0f0RGHA9RAAIO2Wt+LiAp/OhmobBmlnGbcdC5P9wgjywYvYHFvkrOEOZLA3 r7mZZIWiGIjF9qqN8N8jRocOHd4A6V33+GObtULOkYp3ctRvWgTSxy+2w4WpWRzfAtAs 8fsWDKuzQyDEz8xQ2JYD5oZB3uByf7KywDW5DWOWWx0hqYIfvhX9PuNu5Ni2260qQeNH NJRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G0qKKKRBgRaNdfPc1uehv7o+JmYHFw6tz68sq2JtWhM=; b=bbMpBLXTZ86puCk5N8yBMBni3eKXAiULxwhbzcIERMCSf29lI/Nwfa/ynlI4EEBnEs mz3wWZx2cnacvW2ZiegRKCI7nqQR2hSM3jbUoiPtRPv24J43IY9k9kAe1NS8b6waHAVc xA6RnLcTURcUrublbS1gMrKj3MIoDBXfkRykUVg6S8wzEePlnbRuZEjjmfqa2856XFH4 ZykrJ4gY+HpcjCXHN5JbOQXi/IfkvxeaHhm6C4v5WzFaYQfbuUkf8Y5vS40n7sqf/dwJ y6YShArUQTfrowZ9rVQsULurOnOA/4uTb3p4lqJQV73IfZg0SQnhvC9400oR2AzQfS2/ 4uHA== X-Gm-Message-State: AOAM532y4fuaqLWPNEx4GTBRN017NFKyFWe4qO9sU7szW07Q9VguSJCJ I50yha7o1+pDlfUJ+PeTRglJNg== X-Google-Smtp-Source: ABdhPJwCT4OOGCBVqoqEjhLyOO7deop4I2mzez1Gsk8u3FyUguLbTB0XXtcw1JMXni+YNEOE3B13gQ== X-Received: by 2002:a05:6808:20a9:b0:2d4:b8de:887d with SMTP id s41-20020a05680820a900b002d4b8de887dmr9718414oiw.33.1646041372765; Mon, 28 Feb 2022 01:42:52 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id bx10-20020a0568081b0a00b002d70da1ac54sm5936852oib.19.2022.02.28.01.42.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 01:42:52 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , kvm-riscv@lists.infradead.org, Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [RFC PATCH 6/6] RISC-V: KVM: Support sstc extension Date: Mon, 28 Feb 2022 01:42:33 -0800 Message-Id: <20220228094234.3773153-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220228094234.3773153-1-atishp@rivosinc.com> References: <20220228094234.3773153-1-atishp@rivosinc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Sstc extension allows the guest to program the vstimecmp CSR directly instead of making an SBI call to the hypervisor to program the next event. The timer interrupt is also directly injected to the guest by the hardware in this case. To maintain backward compatibility, the hypervisors also update the vstimecmp in an SBI set_time call if the hardware supports it. Thus, the older kernels in guest also take advantage of the sstc extension. Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_host.h | 4 + arch/riscv/include/asm/kvm_vcpu_timer.h | 3 +- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/main.c | 8 ++ arch/riscv/kvm/vcpu.c | 4 +- arch/riscv/kvm/vcpu_sbi_replace.c | 10 +- arch/riscv/kvm/vcpu_timer.c | 136 +++++++++++++++++++++++- 7 files changed, 158 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 99ef6a120617..fb8c993ba022 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -135,6 +135,7 @@ struct kvm_vcpu_csr { unsigned long hvip; unsigned long vsatp; unsigned long scounteren; + u64 vstimecmp; }; struct kvm_vcpu_arch { @@ -179,6 +180,9 @@ struct kvm_vcpu_arch { /* VCPU Timer */ struct kvm_vcpu_timer timer; + /* VCPU Timer for vstimecmp */ + struct kvm_vcpu_timer vstimer; + /* MMIO instruction details */ struct kvm_mmio_decode mmio_decode; diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/asm/kvm_vcpu_timer.h index 375281eb49e0..10715b81db86 100644 --- a/arch/riscv/include/asm/kvm_vcpu_timer.h +++ b/arch/riscv/include/asm/kvm_vcpu_timer.h @@ -39,6 +39,7 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu); int kvm_riscv_guest_timer_init(struct kvm *kvm); - +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu); #endif diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index e01678aa2a55..c7c313272c0b 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -97,6 +97,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_H, KVM_RISCV_ISA_EXT_I, KVM_RISCV_ISA_EXT_M, + KVM_RISCV_ISA_EXT_SSTC, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index 2e5ca43c8c49..8485f59d2db3 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -13,6 +13,7 @@ #include #include #include +#include long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) @@ -50,6 +51,13 @@ int kvm_arch_hardware_enable(void) csr_write(CSR_HIDELEG, hideleg); csr_write(CSR_HCOUNTEREN, -1UL); + if (cpu_sstc_ext_available) { +#ifdef CONFIG_64BIT + csr_write(CSR_HENVCFG, 1UL<arch.isa); kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); + kvm_riscv_vcpu_timer_save(vcpu); csr_write(CSR_HGATP, 0); csr->vsstatus = csr_read(CSR_VSSTATUS); diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c index 1bc0608a5bfd..e34fc9e1f41b 100644 --- a/arch/riscv/kvm/vcpu_sbi_replace.c +++ b/arch/riscv/kvm/vcpu_sbi_replace.c @@ -30,7 +30,15 @@ static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, #else next_cycle = (u64)cp->a0; #endif - kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle); + if (cpu_sstc_ext_available) { +#if __riscv_xlen == 32 + csr_write(CSR_VSTIMECMP, next_cycle & 0xFFFFFFFF); + csr_write(CSR_VSTIMECMPH, next_cycle >> 32); +#else + csr_write(CSR_VSTIMECMP, next_cycle); +#endif + } else + kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle); return ret; } diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c index 5c4c37ff2d48..5647c234fea3 100644 --- a/arch/riscv/kvm/vcpu_timer.c +++ b/arch/riscv/kvm/vcpu_timer.c @@ -14,6 +14,7 @@ #include #include #include +#include static u64 kvm_riscv_current_cycles(struct kvm_guest_timer *gt) { @@ -88,10 +89,66 @@ int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles) return 0; } +static enum hrtimer_restart kvm_riscv_vcpu_vstimer_expired(struct hrtimer *h) +{ + u64 delta_ns; + struct kvm_vcpu_timer *vst = container_of(h, struct kvm_vcpu_timer, hrt); + struct kvm_vcpu *vcpu = container_of(vst, struct kvm_vcpu, arch.vstimer); + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; + + if (kvm_riscv_current_cycles(gt) < vst->next_cycles) { + delta_ns = kvm_riscv_delta_cycles2ns(vst->next_cycles, gt, vst); + hrtimer_forward_now(&vst->hrt, ktime_set(0, delta_ns)); + return HRTIMER_RESTART; + } + + vst->next_set = false; + kvm_vcpu_kick(vcpu); + + return HRTIMER_NORESTART; +} + +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *vst = &vcpu->arch.vstimer; + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; + u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp; + + if (!kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, vst) || + kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER)) + return true; + else + return false; +} + +static void kvm_riscv_vcpu_timer_blocking(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *vst = &vcpu->arch.vstimer; + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; + u64 delta_ns; + u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp; + + if (!vst->init_done) + return; + + delta_ns = kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, vst); + if (delta_ns) { + vst->next_cycles = vstimecmp_val; + hrtimer_start(&vst->hrt, ktime_set(0, delta_ns), HRTIMER_MODE_REL); + vst->next_set = true; + } +} + +static void kvm_riscv_vcpu_timer_unblocking(struct kvm_vcpu *vcpu) +{ + kvm_riscv_vcpu_timer_cancel(&vcpu->arch.vstimer); +} + int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { struct kvm_vcpu_timer *t = &vcpu->arch.timer; + struct kvm_vcpu_timer *vst = &vcpu->arch.vstimer; struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | @@ -112,7 +169,10 @@ int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu, reg_val = kvm_riscv_current_cycles(gt); break; case KVM_REG_RISCV_TIMER_REG(compare): - reg_val = t->next_cycles; + if (cpu_sstc_ext_available) + reg_val = vst->next_cycles; + else + reg_val = t->next_cycles; break; case KVM_REG_RISCV_TIMER_REG(state): reg_val = (t->next_set) ? KVM_RISCV_TIMER_STATE_ON : @@ -132,6 +192,7 @@ int kvm_riscv_vcpu_set_reg_timer(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { struct kvm_vcpu_timer *t = &vcpu->arch.timer; + struct kvm_vcpu_timer *vst = &vcpu->arch.vstimer; struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | @@ -156,7 +217,10 @@ int kvm_riscv_vcpu_set_reg_timer(struct kvm_vcpu *vcpu, gt->time_delta = reg_val - get_cycles64(); break; case KVM_REG_RISCV_TIMER_REG(compare): - t->next_cycles = reg_val; + if (cpu_sstc_ext_available) + vst->next_cycles = reg_val; + else + t->next_cycles = reg_val; break; case KVM_REG_RISCV_TIMER_REG(state): if (reg_val == KVM_RISCV_TIMER_STATE_ON) @@ -175,8 +239,9 @@ int kvm_riscv_vcpu_set_reg_timer(struct kvm_vcpu *vcpu, int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu) { struct kvm_vcpu_timer *t = &vcpu->arch.timer; + struct kvm_vcpu_timer *vst = &vcpu->arch.vstimer; - if (t->init_done) + if (t->init_done || vst->init_done) return -EINVAL; hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL); @@ -184,6 +249,11 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu) t->init_done = true; t->next_set = false; + hrtimer_init(&vst->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + vst->hrt.function = kvm_riscv_vcpu_vstimer_expired; + vst->init_done = true; + vst->next_set = false; + return 0; } @@ -194,15 +264,21 @@ int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu) ret = kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); vcpu->arch.timer.init_done = false; + ret = kvm_riscv_vcpu_timer_cancel(&vcpu->arch.vstimer); + vcpu->arch.vstimer.init_done = false; + return ret; } int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu) { - return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); + kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); + kvm_riscv_vcpu_timer_cancel(&vcpu->arch.vstimer); + + return 0; } -void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) +static void kvm_riscv_vcpu_update_timedelta(struct kvm_vcpu *vcpu) { struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; @@ -214,6 +290,56 @@ void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) #endif } +void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *vst; + struct kvm_vcpu_csr *csr; + + kvm_riscv_vcpu_update_timedelta(vcpu); + + if (!cpu_sstc_ext_available) + return; + + vst = &vcpu->arch.vstimer; + csr = &vcpu->arch.guest_csr; +#ifdef CONFIG_64BIT + csr_write(CSR_VSTIMECMP, csr->vstimecmp); +#else + csr_write(CSR_VSTIMECMP, (u32)csr->vstimecmp); + csr_write(CSR_VSTIMECMPH, (u32)(csr->vstimecmp >> 32)); +#endif + + /* vstimer should be enabled for the remaining operations */ + if (unlikely(!vst->init_done)) + return; + + if (kvm_vcpu_is_blocking(vcpu)) + kvm_riscv_vcpu_timer_blocking(vcpu); +} + +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr; + struct kvm_vcpu_timer *vst; + + if (!cpu_sstc_ext_available) + return; + + csr = &vcpu->arch.guest_csr; + vst = &vcpu->arch.vstimer; +#ifdef CONFIG_64BIT + csr->vstimecmp = csr_read(CSR_VSTIMECMP); +#else + csr->vstimecmp = csr_read(CSR_VSTIMECMP); + csr->vstimecmp |= (u64)csr_read(CSR_VSTIMECMPH) >> 32; +#endif + /* vstimer should be enabled for the remaining operations */ + if (unlikely(!vst->init_done)) + return; + + kvm_riscv_vcpu_timer_unblocking(vcpu); +} + int kvm_riscv_guest_timer_init(struct kvm *kvm) { struct kvm_guest_timer *gt = &kvm->arch.timer;