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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:31:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 01/17] hw/registerfields: Add FIELD_SEX and FIELD_SDP Date: Wed, 23 Feb 2022 12:31:21 -1000 Message-Id: <20220223223137.114264-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::430 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add new macros to manipulate signed fields within the register. Reviewed-by: Philippe Mathieu-Daudé Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- include/hw/registerfields.h | 48 ++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index f2a3c9c41f..3a88e135d0 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -59,6 +59,19 @@ extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_SEX8(storage, reg, field) \ + sextract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_SEX16(storage, reg, field) \ + sextract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_SEX32(storage, reg, field) \ + sextract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_SEX64(storage, reg, field) \ + sextract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) + /* Extract a field from an array of registers */ #define ARRAY_FIELD_EX32(regs, reg, field) \ FIELD_EX32((regs)[R_ ## reg], reg, field) @@ -95,7 +108,40 @@ _d; }) #define FIELD_DP64(storage, reg, field, val) ({ \ struct { \ - uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \ + uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \ + } _v = { .v = val }; \ + uint64_t _d; \ + _d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ + _d; }) + +#define FIELD_SDP8(storage, reg, field, val) ({ \ + struct { \ + signed int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } _v = { .v = val }; \ + uint8_t _d; \ + _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ + _d; }) +#define FIELD_SDP16(storage, reg, field, val) ({ \ + struct { \ + signed int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } _v = { .v = val }; \ + uint16_t _d; \ + _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ + _d; }) +#define FIELD_SDP32(storage, reg, field, val) ({ \ + struct { \ + signed int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } _v = { .v = val }; \ + uint32_t _d; \ + _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ + _d; }) +#define FIELD_SDP64(storage, reg, field, val) ({ \ + struct { \ + int64_t v:R_ ## reg ## _ ## field ## _LENGTH; \ } _v = { .v = val }; \ uint64_t _d; \ _d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ From patchwork Wed Feb 23 22:31:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545219 X-Google-Smtp-Source: ABdhPJxyKZ0qOwpC6me0mw+e5NZIH76zg3XoTgHclis4q2qjC4a9SSxj3EFMbP7LegIc9FEJc+I3 X-Received: by 2002:a37:713:0:b0:49b:7d7a:60cd with SMTP id 19-20020a370713000000b0049b7d7a60cdmr1322822qkh.28.1645655739672; Wed, 23 Feb 2022 14:35:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645655739; cv=none; d=google.com; s=arc-20160816; b=u7dIE8ijk8UtwvCKgbuvpQio2aEdKc+kJcX+tmK8IUluPVf6bBdJ4eLRydZHs5ffei 0ccP8rDsq0qqcuoAP84xhlZ+X1XpYtCVVhUMqDY2+mZjOPJtVRFpOlduX/5Dt9hPMZsU UkSXtNXpu6hQUJZJvWElgQC6pXMWY6RLqUA13xLPDYDZR3d88KioUuc18QbaQb36L585 W3RDDve4SG2xhJAQXEEKWTJgJWZ21dASou0acYlRTi/DAMgJnYy4sAfFPTzNnzEze6IA CsgPPuraqaK+YB8aPdoeqj+IKzeRFPNr+isORLr56DUYzCALcxd49BCh2WJn20xuWhVM 5F4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=E1rlJYYazfRdVeynNKa6RTb/vpD+L0sCNF3QpW/Zvp8=; b=MleRFkaTybfqm8CNS533+FOtFPg22To+lvfz1M9++D0oH1GkUBeWDw+8VfL+BbRMpI VgSA3prgnHOC6W7eLOcW/bBQN7GcDWtGiu2ErPX/hYtRp3FoFFrxlTt6xwm3DbWTbH5X XM1LieegGYiruw7RNUytGxqfSN15FBBrykjIzk7gVritF0x1kl2Yizfa8Zc12PQUls0e /ll/IEIMDfb3ScOZ1K2a9AW1DQJ4R1q0p9EIBrRdhB7BM8rzcmoMO6DHYJ7ekWxmLRva r76V+aP3DEulka3L02fdctTrgnETOGnPh19ZGL35QyjZz9MLjWU7oo6RSFnw6II4u+Lm VNVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Jb8iHIsI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.31.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:31:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 02/17] target/arm: Set TCR_EL1.TSZ for user-only Date: Wed, 23 Feb 2022 12:31:22 -1000 Message-Id: <20220223223137.114264-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1032 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Set this as the kernel would, to 48 bits, to keep the computation of the address space correct for PAuth. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c085dc10ee..e251f0df4b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -206,10 +206,11 @@ static void arm_cpu_reset(DeviceState *dev) aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); } /* + * Enable 48-bit address space (TODO: take reserved_va into account). * Enable TBI0 but not TBI1. * Note that this must match useronly_clean_ptr. */ - env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); + env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); /* Enable MTE */ if (cpu_isar_feature(aa64_mte, cpu)) { From patchwork Wed Feb 23 22:31:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545221 X-Google-Smtp-Source: ABdhPJwWPi7UgWVXOWxZS1gCRvu8UrQUml/M29S/funYTz3AM2c8e1Oy27IgtcT6+mxixjCWGHCz X-Received: by 2002:a05:620a:1103:b0:60d:e5c8:a597 with SMTP id o3-20020a05620a110300b0060de5c8a597mr1256976qkk.513.1645655908936; Wed, 23 Feb 2022 14:38:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645655908; cv=none; d=google.com; s=arc-20160816; b=r5/TN62nEkkedxjEgJ7iHeKPoP6afKDSpIy/s0S5Za0GD0/4oZihYxuQZPlVsxHQGw zCaRSlrneOIh4lx5pagcykyxhKPsKLnaOJIL5Maas1cTnajT8QoM1mF7BN/KCNYyzrD7 6N5FADUgwWwv/3gw9AfyDTRjwHkqUGTPHSAviPqwS6wbObeN3WfGKMUp4YZ3miBwGUsb 8JRHmNwYhGI6OpuOjftJ3R9KvogGXuvJbaHd3KHPQKIK74zEXC6rf2Tvtu8nJX/KZH2N H5KC/Q+zWUgzDOhhLCZ7hxXcIEFCPh1/xMb6AKPSDucYiaSzYiiV5JsGiNv1QQSAXvam nkQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8FniAxzNq9R5C3PUa8crK2rtgbWJQ/YT25+L7bxil2U=; b=dxiWofykPU0q44G/yB8cDHe7l51K0BInHz0yhhe6GJY/O3UL6k1yRz00bTlxkkfVZt 5QDoPq2Q03A1lVBOV3jEAXCjWVMUAuEPNGPmQId9c6GUCTdKl9U0gzxvnGf6iA3eZQ/p KF0jxiZNUR0/ML94X7CdzfQYQt08//KOMnofAviryIciNwfBM/pTmB0OXswyUwjz0Ed6 bS3juhjAlyX3cXvWTJ/0imfmBJWoITAgWM+/HLy9YXalBHkJYVYO/Jn8Ndmo0o8A3ofM 7OG+rSh2ScVDOgQXo+AXV4Pjd8ZvGZcj1ryn3wDMAU/keQ7gRdCCAmBT15wDWeQFxhP1 KcQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mMRtQwqR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.31.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:31:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 03/17] target/arm: Fault on invalid TCR_ELx.TxSZ Date: Wed, 23 Feb 2022 12:31:23 -1000 Message-Id: <20220223223137.114264-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1034 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Without FEAT_LVA, the behaviour of programming an invalid value is IMPLEMENTATION DEFINED. With FEAT_LVA, programming an invalid minimum value requires a Translation fault. It is most self-consistent to choose to generate the fault always. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Continue to bound in aa64_va_parameters, so that PAuth gets something it can use, but provide a flag for get_phys_addr_lpae to raise a fault. --- target/arm/internals.h | 1 + target/arm/helper.c | 32 ++++++++++++++++++++++++++++---- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3f05748ea4..ef6c25d8cb 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1055,6 +1055,7 @@ typedef struct ARMVAParameters { bool hpd : 1; bool using16k : 1; bool using64k : 1; + bool tsz_oob : 1; /* tsz has been clamped to legal range */ } ARMVAParameters; ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, diff --git a/target/arm/helper.c b/target/arm/helper.c index 7bf50fdd76..dd4d95bda2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11190,8 +11190,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; - bool epd, hpd, using16k, using64k; - int select, tsz, tbi, max_tsz; + bool epd, hpd, using16k, using64k, tsz_oob; + int select, tsz, tbi, max_tsz, min_tsz; if (!regime_has_2_ranges(mmu_idx)) { select = 0; @@ -11232,9 +11232,17 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, } else { max_tsz = 39; } + min_tsz = 16; /* TODO: ARMv8.2-LVA */ - tsz = MIN(tsz, max_tsz); - tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ + if (tsz > max_tsz) { + tsz = max_tsz; + tsz_oob = true; + } else if (tsz < min_tsz) { + tsz = min_tsz; + tsz_oob = true; + } else { + tsz_oob = false; + } /* Present TBI as a composite with TBID. */ tbi = aa64_va_parameter_tbi(tcr, mmu_idx); @@ -11251,6 +11259,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, .hpd = hpd, .using16k = using16k, .using64k = using64k, + .tsz_oob = tsz_oob, }; } @@ -11374,6 +11383,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, param = aa64_va_parameters(env, address, mmu_idx, access_type != MMU_INST_FETCH); level = 0; + + /* + * If TxSZ is programmed to a value larger than the maximum, + * or smaller than the effective minimum, it is IMPLEMENTATION + * DEFINED whether we behave as if the field were programmed + * within bounds, or if a level 0 Translation fault is generated. + * + * With FEAT_LVA, fault on less than minimum becomes required, + * so our choice is to always raise the fault. + */ + if (param.tsz_oob) { + fault_type = ARMFault_Translation; + goto do_fault; + } + addrsize = 64 - 8 * param.tbi; inputsize = 64 - param.tsz; } else { From patchwork Wed Feb 23 22:31:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545222 X-Google-Smtp-Source: ABdhPJwDwk8XonBXZmEMHf4VX67D6mmlekPAntXC86vP8v+vNqWZKGcvIRJw1fK3xY/sEFylfv55 X-Received: by 2002:a05:620a:126a:b0:648:a948:d0c8 with SMTP id b10-20020a05620a126a00b00648a948d0c8mr1355595qkl.652.1645655982164; Wed, 23 Feb 2022 14:39:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645655982; cv=none; d=google.com; s=arc-20160816; b=DC5nNqmYiiS+PXQAyyhukKab6LOs/O/SUtiJLfXfjXy0pHlLaS7WHa4AzxmQxCCm7T 7cS6rUlybiOVApRT01noiUhuIjNAG15HymbzoOzZXJJqVY9tsHuZ98fE+sOfwt+r58vm +MXlUEmxQqOHs0EfbAMquVal25SUp0zohIJpsAsP7TbwXql99EXyk4AqUovab+T9062t Bj8dlNiPDCby7a0ouhh0lS2ghyZ04OJyyKr4Ya/1PdPOnRe1lHuT35juAamtnaWuqggV tkP4qKWnxek7fUOE8UgvSfDuAuI55kXM3SrO4dcT9VJiYwS0L56qXcH5oIDfvNHsXJFq Wyfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+DAMlpqsE9DmBwY1s+cP0r+gi8rLuchADVNtgdDMW7U=; b=SuY5Wx9CJ/ffd+jHcROiKCdQSoDY4ZNyTsWjCoWFIgC5dk6jnioFBTx35x6TG69iqm tIiqcL5DgGzz/aHJZNHY7d+lt/PzLtNxtprHy0eW1Itjziv9310kgGVvIBqRU5wS+7HE BK0Dl7Ax3h0SydEseKQLurWGX950AKp3qYOHAbWCMh3lc7EI+YSaZAdsCk7wkoujNQvN yqhSIuZHe1Zp5KBCdbJhyquf49KxSj0aEhOrEUqe4J3S1FpuAsS8FcNQiyYJTD2rhtm+ zoB4groRJDrveupNetb/8JgK9GmKscU7GFE5x1f8ZGsWxiNAfABOkTmXSPnAlNenioQD lNYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gOBGPyjn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.31.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:31:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 04/17] target/arm: Move arm_pamax out of line Date: Wed, 23 Feb 2022 12:31:24 -1000 Message-Id: <20220223223137.114264-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will shortly share parts of this function with other portions of address translation. Reviewed-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/internals.h | 19 +------------------ target/arm/helper.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 18 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index ef6c25d8cb..fefd1fb8d8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -243,24 +243,7 @@ static inline void update_spsel(CPUARMState *env, uint32_t imm) * Returns the implementation defined bit-width of physical addresses. * The ARMv8 reference manuals refer to this as PAMax(). */ -static inline unsigned int arm_pamax(ARMCPU *cpu) -{ - static const unsigned int pamax_map[] = { - [0] = 32, - [1] = 36, - [2] = 40, - [3] = 42, - [4] = 44, - [5] = 48, - }; - unsigned int parange = - FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); - - /* id_aa64mmfr0 is a read-only register so values outside of the - * supported mappings can be considered an implementation error. */ - assert(parange < ARRAY_SIZE(pamax_map)); - return pamax_map[parange]; -} +unsigned int arm_pamax(ARMCPU *cpu); /* Return true if extended addresses are enabled. * This is always the case if our translation regime is 64 bit, diff --git a/target/arm/helper.c b/target/arm/helper.c index dd4d95bda2..71e575f352 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11152,6 +11152,28 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) } #endif /* !CONFIG_USER_ONLY */ +/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ +unsigned int arm_pamax(ARMCPU *cpu) +{ + static const unsigned int pamax_map[] = { + [0] = 32, + [1] = 36, + [2] = 40, + [3] = 42, + [4] = 44, + [5] = 48, + }; + unsigned int parange = + FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + + /* + * id_aa64mmfr0 is a read-only register so values outside of the + * supported mappings can be considered an implementation error. + */ + assert(parange < ARRAY_SIZE(pamax_map)); + return pamax_map[parange]; +} + static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) { if (regime_has_2_ranges(mmu_idx)) { From patchwork Wed Feb 23 22:31:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545223 X-Google-Smtp-Source: ABdhPJyqemjUjeoTALxcpCDuTdp7Ur1ZclFVBGTCUVQZPJ+ogwh90I7/OWGLP/57q9nclGoEi+F8 X-Received: by 2002:a0c:bf12:0:b0:42c:536d:52d7 with SMTP id m18-20020a0cbf12000000b0042c536d52d7mr1362836qvi.33.1645656163418; Wed, 23 Feb 2022 14:42:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645656163; cv=none; d=google.com; s=arc-20160816; b=CFEpBZ+za6E9fUcaW6MU6F5i+DML0i9Bn4ahpYldNpT7NhiX5/Yd0bqQjcE+Cl3HC1 wv/mjpBrv8rxMC+ib70gwDJZlcrVRm+cQGFfTijOs0opFo+AtZVxdsAwzT2rndJAQEOc QLo2Z9K1aRhT37tWure4DhwEa4X/3QiB+Xr0aG04D5Shg5xdNGr/8l1nE9Wdjki+gxe2 B5WVQSLAPH3aoj6A4UQzNTRMCPaKckDeey+8/XVpH/GpQIUI2K1/rhwxtWf/g8DhiR7n SRQ4CI3BQBr84scgf5gX/6iiqdhpjIO5Ca/Giv59SOELMdFQlRBE8/3e0HT36unhPwNQ e18g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=TAU62jUEHWqZmP/omH+DP65D27WXovgj7reF6QpCfzg=; b=OYlKTKF7zKYlUleJzx7rc/lg/CybZ2jF2N+7k9avP9MDRJfVyWKyJbxEi0r7spzAHK qN/zpyjkU6kAJw55oKpviRdGKKU/Ui3jGtLJmOe6+QECUaC8MqxJyj1nzjjLu8uRBj9J rB5Pu/K/8lNNlY4F3vuqO7irVoFslm8YNaX5V5NpDiJv2Na6hWWBKN0ABMfRdjuMxAh0 6ssqiIewPI19B3WNh0AxONdqCF6/Nup09Nck4fspUHz5LQ42EjKEY1D04AHalrUIRo0l 5HTYl5TTfdS7j9dsCuelz31iMfJwyr7Z0KfIrc1i6yiKsbcTUYYwLJ3VdQz3I6zaogBT anzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qci+ATQT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:31:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 05/17] target/arm: Pass outputsize down to check_s2_mmu_setup Date: Wed, 23 Feb 2022 12:31:25 -1000 Message-Id: <20220223223137.114264-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::431 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Pass down the width of the output address from translation. For now this is still just PAMax, but a subsequent patch will compute the correct value from TCR_ELx.{I}PS. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 71e575f352..431b0c1405 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11065,7 +11065,7 @@ do_fault: * false otherwise. */ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, - int inputsize, int stride) + int inputsize, int stride, int outputsize) { const int grainsize = stride + 3; int startsizecheck; @@ -11081,22 +11081,19 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, } if (is_aa64) { - CPUARMState *env = &cpu->env; - unsigned int pamax = arm_pamax(cpu); - switch (stride) { case 13: /* 64KB Pages. */ - if (level == 0 || (level == 1 && pamax <= 42)) { + if (level == 0 || (level == 1 && outputsize <= 42)) { return false; } break; case 11: /* 16KB Pages. */ - if (level == 0 || (level == 1 && pamax <= 40)) { + if (level == 0 || (level == 1 && outputsize <= 40)) { return false; } break; case 9: /* 4KB Pages. */ - if (level == 0 && pamax <= 42) { + if (level == 0 && outputsize <= 42) { return false; } break; @@ -11105,8 +11102,8 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, } /* Inputsize checks. */ - if (inputsize > pamax && - (arm_el_is_aa64(env, 1) || inputsize > 40)) { + if (inputsize > outputsize && + (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) { /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ return false; } @@ -11392,7 +11389,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, target_ulong page_size; uint32_t attrs; int32_t stride; - int addrsize, inputsize; + int addrsize, inputsize, outputsize; TCR *tcr = regime_tcr(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el = regime_el(env, mmu_idx); @@ -11422,11 +11419,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, addrsize = 64 - 8 * param.tbi; inputsize = 64 - param.tsz; + outputsize = arm_pamax(cpu); } else { param = aa32_va_parameters(env, address, mmu_idx); level = 1; addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32); inputsize = addrsize - param.tsz; + outputsize = 40; } /* @@ -11511,7 +11510,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* Check that the starting level is valid. */ ok = check_s2_mmu_setup(cpu, aarch64, startlevel, - inputsize, stride); + inputsize, stride, outputsize); if (!ok) { fault_type = ARMFault_Translation; goto do_fault; From patchwork Wed Feb 23 22:31:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545224 X-Google-Smtp-Source: ABdhPJyug8i1UQl3R0Bu205CN2ZKwb3T0pl05GLfMW89CZb/5cIa2Ub+p18RF0WwFeqcsWH5E2L2 X-Received: by 2002:a05:620a:9d8:b0:648:cdf7:936a with SMTP id y24-20020a05620a09d800b00648cdf7936amr1309941qky.337.1645656188073; Wed, 23 Feb 2022 14:43:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645656188; cv=none; d=google.com; s=arc-20160816; b=ymSZOGngornOburHoASW1JaP0R9Q6Hm5uNRmUCjGEBsDLZkW4f0VdE6Bn5Of7chBt1 +ztiGBcNRm4LW4y/Q1L4O1mXQl4c+E2alqK+OsZmkfFRaUl2gA7uUFJQTIhsnv2kuzB5 f78/9VSaGQGNMvFMxFHCkyBErP50mUY4VDjTbt94vGLUJcrSZt++t1RsnEqFLuyGAYco av+T+H0xEP2bS5uZsHb7YVenJh4QsXwqBaqFuWIsadeaY2RvHY5Js5X7zlS9sygQcdz4 Xrlf2rkgmGYK7zUUT+Jogoi+8SK8fPuTN6dJpcSS6jxCVAt5QFag9bhUeRU7qBv2Rntz NsrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gIGj1SBy99bk76FDyotKqntArH5MW9KjKA2GprTkmIQ=; b=yfzapoEPzYKzobsx320xvuWRedFtlDGzm3IHRloK3/OM4s/HM+p6qZce514/XV4pqH 9NkhSNDiK3PTc/bpgYQlPWewAZyb8KjQ/vQxClLg+BkES7vszyNMQNlHYDrYMsJCbrdT HenZpKN1jD8afeRswweDvsG6drccctS94PcTnmQGRR/C09u0XBTrRCimCG04hw2TvpQh Y2iLnrAqosWGJ4EJ0a7hSY01tWJ8dL6ec5v1H3gOs5o/a3TmwlVv1ABKh79aosq2f0p8 ed9rTd2zsZfcm2OWHN/YMPhSFpvKalT1VHXeu37e1sP51VCsep1iMwS9KTVLvUIYxIFV PaEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sLvusCfo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.31.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:31:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 06/17] target/arm: Use MAKE_64BIT_MASK to compute indexmask Date: Wed, 23 Feb 2022 12:31:26 -1000 Message-Id: <20220223223137.114264-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The macro is a bit more readable than the inlined computation. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 431b0c1405..675aec4bf3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11518,8 +11518,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, level = startlevel; } - indexmask_grainsize = (1ULL << (stride + 3)) - 1; - indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; + indexmask_grainsize = MAKE_64BIT_MASK(0, stride + 3); + indexmask = MAKE_64BIT_MASK(0, inputsize - (stride * (4 - level))); /* Now we can extract the actual base address from the TTBR */ descaddr = extract64(ttbr, 0, 48); From patchwork Wed Feb 23 22:31:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545225 X-Google-Smtp-Source: ABdhPJxs72b+bHMSF3SVlTHa8rI5klHTKIMystH8vxjio1txsvQRsvyWY2gFUUFqmTTIprVANxZD X-Received: by 2002:a05:6214:5293:b0:432:3071:e947 with SMTP id kj19-20020a056214529300b004323071e947mr1399721qvb.62.1645656189281; Wed, 23 Feb 2022 14:43:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645656189; cv=none; d=google.com; s=arc-20160816; b=KKKIuf8wtjpIFO+rBR64f20Lqh2QBG+8+WW/NaYMbEkVAc3u9MdXeOqdDbqFJfuzr1 bBMit2SMjVfe3y75ISn7pACbA5KkP9zshSEkwTkYyOBQT0GRbWbaBLTqXczRyTqvQiEM q+Rvd99gkVP26w2BdwrPA+PDDpdkEx+0pFphNmeKTI9Ms8vvdGHIhqmHlTB/hQTBCEYR K2N0HVqwwyDPHh+gtzIweufH4n1wNmUFDzzaXfFMTWqYGUAGqLz3HU5gtIejMIRdKin9 f4TJ9vKdex/NlNoV4FjOlIlB+SWCg/wwxE3m9IlT94NVpd83Fo7Z5mr/+0Yf0JjyucO1 gpIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4y89pQ0OdmVIqwd6NdNcqx8YrKd1GuWayeQiD4wW2NU=; b=H0IS2KoYFT3R16+pqeMAk0nzNp4wakd4ZmCWkbNGDxC1k1q3SgPA9vqI43NSfaTmY3 jv6umpZmlH4zztILaLGKrDag0SSGx/3A4fOD4Ea+5FdMtViN8jKdSS2ZcYZdKuxcNjPk 5iiiaJ53KNSsQk2Y3BKkTfVYYXb/1491622AIWb0MTDLrILGFrll6Cjyzx1JEINsyFGU lVntK+stxev572EvFWQuXYvShs45uFTDZZAWMO2bMtU5I9V/zDvIWiOfJCPUmOgsLGV1 G6v5gU6gHieGXIEqai8ooNZDmMjVmusPnCrWDhqCq3KPbbFI12avxzS4OA0s8bNLXKgZ fObw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Z8zPDZfP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.31.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:31:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 07/17] target/arm: Honor TCR_ELx.{I}PS Date: Wed, 23 Feb 2022 12:31:27 -1000 Message-Id: <20220223223137.114264-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This field controls the output (intermediate) physical address size of the translation process. V8 requires to raise an AddressSize fault if the page tables are programmed incorrectly, such that any intermediate descriptor address, or the final translated address, is out of range. Add a PS field to ARMVAParameters, and properly compute outputsize in get_phys_addr_lpae. Test the descaddr as extracted from TTBR and from page table entries. Restrict descaddrmask so that we won't raise the fault for v7. Reviewed-by: Peter Maydell Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + target/arm/helper.c | 72 ++++++++++++++++++++++++++++++++---------- 2 files changed, 57 insertions(+), 16 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fefd1fb8d8..3d3d41ba2b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1032,6 +1032,7 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) */ typedef struct ARMVAParameters { unsigned tsz : 8; + unsigned ps : 3; unsigned select : 1; bool tbi : 1; bool epd : 1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 675aec4bf3..c002100979 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11149,17 +11149,19 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) } #endif /* !CONFIG_USER_ONLY */ +/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ +static const uint8_t pamax_map[] = { + [0] = 32, + [1] = 36, + [2] = 40, + [3] = 42, + [4] = 44, + [5] = 48, +}; + /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ unsigned int arm_pamax(ARMCPU *cpu) { - static const unsigned int pamax_map[] = { - [0] = 32, - [1] = 36, - [2] = 40, - [3] = 42, - [4] = 44, - [5] = 48, - }; unsigned int parange = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); @@ -11210,7 +11212,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; bool epd, hpd, using16k, using64k, tsz_oob; - int select, tsz, tbi, max_tsz, min_tsz; + int select, tsz, tbi, max_tsz, min_tsz, ps; if (!regime_has_2_ranges(mmu_idx)) { select = 0; @@ -11224,6 +11226,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, hpd = extract32(tcr, 24, 1); } epd = false; + ps = extract32(tcr, 16, 3); } else { /* * Bit 55 is always between the two regions, and is canonical for @@ -11244,6 +11247,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, epd = extract32(tcr, 23, 1); hpd = extract64(tcr, 42, 1); } + ps = extract64(tcr, 32, 3); } if (cpu_isar_feature(aa64_st, env_archcpu(env))) { @@ -11272,6 +11276,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, return (ARMVAParameters) { .tsz = tsz, + .ps = ps, .select = select, .tbi = tbi, .epd = epd, @@ -11399,6 +11404,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* TODO: This code does not support shareability levels. */ if (aarch64) { + int ps; + param = aa64_va_parameters(env, address, mmu_idx, access_type != MMU_INST_FETCH); level = 0; @@ -11419,7 +11426,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, addrsize = 64 - 8 * param.tbi; inputsize = 64 - param.tsz; - outputsize = arm_pamax(cpu); + + /* + * Bound PS by PARANGE to find the effective output address size. + * ID_AA64MMFR0 is a read-only register so values outside of the + * supported mappings can be considered an implementation error. + */ + ps = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + ps = MIN(ps, param.ps); + assert(ps < ARRAY_SIZE(pamax_map)); + outputsize = pamax_map[ps]; } else { param = aa32_va_parameters(env, address, mmu_idx); level = 1; @@ -11523,19 +11539,38 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* Now we can extract the actual base address from the TTBR */ descaddr = extract64(ttbr, 0, 48); + + /* + * If the base address is out of range, raise AddressSizeFault. + * In the pseudocode, this is !IsZero(baseregister<47:outputsize>), + * but we've just cleared the bits above 47, so simplify the test. + */ + if (descaddr >> outputsize) { + level = 0; + fault_type = ARMFault_AddressSize; + goto do_fault; + } + /* * We rely on this masking to clear the RES0 bits at the bottom of the TTBR * and also to mask out CnP (bit 0) which could validly be non-zero. */ descaddr &= ~indexmask; - /* The address field in the descriptor goes up to bit 39 for ARMv7 - * but up to bit 47 for ARMv8, but we use the descaddrmask - * up to bit 39 for AArch32, because we don't need other bits in that case - * to construct next descriptor address (anyway they should be all zeroes). + /* + * For AArch32, the address field in the descriptor goes up to bit 39 + * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0 + * or an AddressSize fault is raised. So for v8 we extract those SBZ + * bits as part of the address, which will be checked via outputsize. + * For AArch64, the address field always goes up to bit 47 (with extra + * bits for FEAT_LPA placed elsewhere). AArch64 implies v8. */ - descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & - ~indexmask_grainsize; + if (arm_feature(env, ARM_FEATURE_V8)) { + descaddrmask = MAKE_64BIT_MASK(0, 48); + } else { + descaddrmask = MAKE_64BIT_MASK(0, 40); + } + descaddrmask &= ~indexmask_grainsize; /* Secure accesses start with the page table in secure memory and * can be downgraded to non-secure at any step. Non-secure accesses @@ -11560,7 +11595,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* Invalid, or the Reserved level 3 encoding */ goto do_fault; } + descaddr = descriptor & descaddrmask; + if (descaddr >> outputsize) { + fault_type = ARMFault_AddressSize; + goto do_fault; + } if ((descriptor & 2) && (level < 3)) { /* Table entry. The top five bits are attributes which may From patchwork Wed Feb 23 22:31:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545226 X-Google-Smtp-Source: ABdhPJxcXEHeN8VK4UpHfVUOtMxswYeb64o1neSQv3d15Zcqb+faKZ623LWzG1VynRtrl8EMoSyu X-Received: by 2002:a37:ad5:0:b0:4b2:a0b9:8307 with SMTP id 204-20020a370ad5000000b004b2a0b98307mr1387759qkk.544.1645656351517; Wed, 23 Feb 2022 14:45:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645656351; cv=none; d=google.com; s=arc-20160816; b=mvaukZnI+qapkFV5OkjqNn0u3ZtJ9dnDhBd9VB8/XatAilsKyd7fa1GEerLWf/0VgD Vsiuokv2anCsPdLlLHwThgxcaHio8UVpwJ4KDzdeRTu0U+Ii6qxI82Q6qZv1TwBlT3yg 9XEzMfB1wcIe0qHSeqjH7XhB1iaLS71bay+LzNMm/Gj+KQt8hvas7IWGsGiNHSnbkXqy YTOZixejuAyXSC5DtyAeFenSeU0AThipE8GRGlZtMxMsHzzI9meHKclRHWSo6SR+45lp Ewz+SXQS0XTybKX8QyQ3g0GoOW2MQBqydcSf6wz6mXSyijQwN4nWCanPAoSJpP+uQe4r hANw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=TmxawEn4TT//u8dncYbu6ycL9fZfNNpmMP+qU1HcQZ0=; b=lWEsM4eXZULiGJIMp8Wj9r+VjLVUX07L2KaaRuI82XEqR35Y3U2/rI0EvVEl+0kBdD 6pUP/7rz/6oNPxFQ+FPadvvKaIzg+u5PfpNpr8Wt4ylqCj4RL2nZ5z/KYtvSE0i1kmwx Et3afMAVEAkZVLHoR8xjr+BI7yfx89WjnEwGjOjxMdUJS6Qies/ImZs6qxS3T08zoLtE ojxxONkZG5Je82glcudkszECYP6LBPFLWzEoJJ6qb4TyvEuNdCQ5cc6noLUqA9vRtECy 3TCK7nLv7GF0Ia5TqosZ7ooBHRiB/b0Dpw+KbXlJ7rcAZkjmk0PsszK+/iE5YHR5nAZL m53A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WMB2Erux; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:31:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 08/17] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA Date: Wed, 23 Feb 2022 12:31:28 -1000 Message-Id: <20220223223137.114264-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::631 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The original A.a revision of the AArch64 ARM required that we force-extend the addresses in these registers from 49 bits. This language has been loosened via a combination of IMPLEMENTATION DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of the entire aligned address. This means that we do not have to consider whether or not FEAT_LVA is enabled, and decide from which bit an address might need to be extended. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c002100979..2eff30d18c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6423,11 +6423,18 @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, ARMCPU *cpu = env_archcpu(env); int i = ri->crm; - /* Bits [63:49] are hardwired to the value of bit [48]; that is, the - * register reads and behaves as if values written are sign extended. + /* * Bits [1:0] are RES0. + * + * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA) + * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if + * they contain the value written. It is CONSTRAINED UNPREDICTABLE + * whether the RESS bits are ignored when comparing an address. + * + * Therefore we are allowed to compare the entire register, which lets + * us avoid considering whether or not FEAT_LVA is actually enabled. */ - value = sextract64(value, 0, 49) & ~3ULL; + value &= ~3ULL; raw_write(env, ri, value); hw_watchpoint_update(cpu, i); @@ -6473,10 +6480,19 @@ void hw_breakpoint_update(ARMCPU *cpu, int n) case 0: /* unlinked address match */ case 1: /* linked address match */ { - /* Bits [63:49] are hardwired to the value of bit [48]; that is, - * we behave as if the register was sign extended. Bits [1:0] are - * RES0. The BAS field is used to allow setting breakpoints on 16 - * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether + /* + * Bits [1:0] are RES0. + * + * It is IMPLEMENTATION DEFINED whether bits [63:49] + * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit + * of the VA field ([48] or [52] for FEAT_LVA), or whether the + * value is read as written. It is CONSTRAINED UNPREDICTABLE + * whether the RESS bits are ignored when comparing an address. + * Therefore we are allowed to compare the entire register, which + * lets us avoid considering whether FEAT_LVA is actually enabled. + * + * The BAS field is used to allow setting breakpoints on 16-bit + * wide instructions; it is CONSTRAINED UNPREDICTABLE whether * a bp will fire if the addresses covered by the bp and the addresses * covered by the insn overlap but the insn doesn't start at the * start of the bp address range. We choose to require the insn and @@ -6489,7 +6505,7 @@ void hw_breakpoint_update(ARMCPU *cpu, int n) * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). */ int bas = extract64(bcr, 5, 4); - addr = sextract64(bvr, 0, 49) & ~3ULL; + addr = bvr & ~3ULL; if (bas == 0) { return; } From patchwork Wed Feb 23 22:31:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545220 X-Google-Smtp-Source: ABdhPJyecfNKcQ/K23ckWRF9AOj8Tdv9vYWoYJldYLHvJFX9WIwOvjMXsFMDXivpj3/FJDebaUYE X-Received: by 2002:a0c:8051:0:b0:42d:ef02:183c with SMTP id 75-20020a0c8051000000b0042def02183cmr1381846qva.28.1645655875289; Wed, 23 Feb 2022 14:37:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645655875; cv=none; d=google.com; s=arc-20160816; b=kduBZ3+WazRs7NTsiXvN3tQLKJ0ifPzVTP/jIL6c7EsH3Bwvh7eLrHo9fK4Pk+3lt+ CepC/lu6snTHF4CNydUZbQFKCvVP0Hm3Oq+XQSvTgrG4FdOg2d7tm+Rr/SKxVitnaQab Px+/J9OaYTpeX2KCFTo8mnLk+MxovBcHhcptc/2Q8GLkZl06grGKd9SAdVBiQaU8oSRk qyc24OuX96ys+ZGc+KCVfKBRh3rrzHlltXK5sSEDuUGqqCqcvZZxsZ/Gp9ffulCiYg5e brraSVmXP2Mqme8e9gzk+S5sqcua4Us4cSVRqAjoCv2mxTll2KQTH/My3zvFIQLCqvo5 Zd9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rots8gM6WyEhatQucngAjy7J8H2b6HMDpJoYQByRIgE=; b=FqIXCVxpz2Yr5dV7k1gSsLsq0bAEojLkEIqSQRj5fIzB/8eTHMlmCYJWnDzZnTtGr8 oP00135EnLokfzTBmHnW6qv1DUsIpt2w93mrDsGbz5cv3rtkPU9YffKFqwS1ywxTHE8U xQh49F2F4spZ5emiUbYBMvE3dil2dgoZdt5rpShm90Y/gfYjUuVhjJrsvxVZbWQ84GN4 UxjsxxYJQPvS0i2vp+dzp7B4ukOym3LykXgdjRTrFCzIX0AA/fLh1LvJjopN0kVue0bX 7SdD3xhxnArou5rNUx7/ZdU2bQFSpWuAC5M7kHF+pf2aEvcFcZc4nugR+RSyZylVyMEW MSvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZpoPYSDC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.31.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:31:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 09/17] target/arm: Implement FEAT_LVA Date: Wed, 23 Feb 2022 12:31:29 -1000 Message-Id: <20220223223137.114264-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1032 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This feature is relatively small, as it applies only to 64k pages and thus requires no additional changes to the table descriptor walking algorithm, only a change to the minimum TSZ (which is the inverse of the maximum virtual address space size). Note that this feature widens VBAR_ELx, but we already treat the register as being 64 bits wide. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 5 +++++ target/arm/cpu64.c | 1 + target/arm/helper.c | 9 ++++++++- 5 files changed, 16 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 144dc491d9..f3eabddfb5 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -27,6 +27,7 @@ the following architecture extensions: - FEAT_LRCPC (Load-acquire RCpc instructions) - FEAT_LRCPC2 (Load-acquire RCpc instructions v2) - FEAT_LSE (Large System Extensions) +- FEAT_LVA (Large Virtual Address space) - FEAT_MTE (Memory Tagging Extension) - FEAT_MTE2 (Memory Tagging Extension) - FEAT_MTE3 (MTE Asymmetric Fault Handling) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 7f38d33b8e..5f9c288b1a 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -11,7 +11,7 @@ #ifdef TARGET_AARCH64 # define TARGET_LONG_BITS 64 # define TARGET_PHYS_ADDR_SPACE_BITS 48 -# define TARGET_VIRT_ADDR_SPACE_BITS 48 +# define TARGET_VIRT_ADDR_SPACE_BITS 52 #else # define TARGET_LONG_BITS 32 # define TARGET_PHYS_ADDR_SPACE_BITS 40 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6a4d50e82..c52d56f669 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4289,6 +4289,11 @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; } +static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; +} + static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1171ab16b9..1de31ffb40 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -811,6 +811,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ + t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ cpu->isar.id_aa64mmfr2 = t; t = cpu->isar.id_aa64zfr0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 2eff30d18c..28b4347213 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11271,7 +11271,14 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, } else { max_tsz = 39; } - min_tsz = 16; /* TODO: ARMv8.2-LVA */ + + min_tsz = 16; + if (using64k) { + if (cpu_isar_feature(aa64_lva, env_archcpu(env))) { + min_tsz = 12; + } + } + /* TODO: FEAT_LPA2 */ if (tsz > max_tsz) { tsz = max_tsz; From patchwork Wed Feb 23 22:31:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545227 X-Google-Smtp-Source: ABdhPJxPj368o+eHApbtz/tzpRgwHy80a6HfKbEsqnfc8YTyekN3VJwIiouD7etOZrdUkUQvw70D X-Received: by 2002:a0c:c601:0:b0:42c:8d4:9e1 with SMTP id v1-20020a0cc601000000b0042c08d409e1mr1361722qvi.75.1645656361038; Wed, 23 Feb 2022 14:46:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645656361; cv=none; d=google.com; s=arc-20160816; b=Gnp9ZmRRzfzsVHHK5/Lej/71ggBVrqRHUs5HQ3EAbF1hP6zYcAkADL5gwMdISNm2m6 UHALgoksXyWDIq/5zKscm3ISHIOl5jcW6JrDbA0ZZ28j2zWn76f+xKkVzDtPxIZl/kKy TqzYD3cZHCVq+/mxW0l8c9+EpmPd3s6RbMOjFNFdNhuoYc2KVWq8o0YWIwIf1a5KqG/x ivczabfTUWFXaYnyQsAdiMRCWFLWxCIPnxXcXALaZ2q8kKUqpig3wykuOTm8QYJxfpCX uPtGp8evON1OFU8OoMRok5z87ZFdWdFrIDE4+KGDidDot9dGQL++qvrIwoVq7ao5wv9w YM2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DRWkLoJkIekxooE0yM1xnliLnzzt/ozTUB9sEE/E5Ow=; b=yfbGHuRa+MOpkz7d8YteixMJb7K8wUZainiGbJyjGGi3H0PzE+z/TIr/KpDw4nQOKF kRyHUZW95YnIrdqmtzWIx/OnBfKRDoqP88SlzUAa8bJjwwD6T4xLmHsYld4uGOOydrhW Wwr/NBCHqKkOfI+Oa6elNeT1/Ks2y22DgjrYtZ5NSczS+3V9r5bWy5K2GGukQWkA9NjU 0AHnlhvfrd2S88SeGnapnbshF0BC2NYLFAF9ZFw5a80d0AlSHW9iWVig8siKnhKya+3u XpKVN6b0nQ+jhmIe4PBy2nbzaVrDKNeBlOL+/h2p83fLepq9UFQYJl7miFdpYyK6oScg HzUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HsqqqynC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.31.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:31:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 10/17] target/arm: Implement FEAT_LPA Date: Wed, 23 Feb 2022 12:31:30 -1000 Message-Id: <20220223223137.114264-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This feature widens physical addresses (and intermediate physical addresses for 2-stage translation) from 48 to 52 bits, when using 64k pages. The only thing left at this point is to handle the extra bits in the TTBR and in the table descriptors. Note that PAR_EL1 and HPFAR_EL2 are nominally extended, but we don't mask out the high bits when writing to those registers, so no changes are required there. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-param.h | 2 +- target/arm/cpu64.c | 2 +- target/arm/helper.c | 19 ++++++++++++++++--- 4 files changed, 19 insertions(+), 5 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index f3eabddfb5..0053ddce20 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -24,6 +24,7 @@ the following architecture extensions: - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) - FEAT_JSCVT (JavaScript conversion instructions) - FEAT_LOR (Limited ordering regions) +- FEAT_LPA (Large Physical Address space) - FEAT_LRCPC (Load-acquire RCpc instructions) - FEAT_LRCPC2 (Load-acquire RCpc instructions v2) - FEAT_LSE (Large System Extensions) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 5f9c288b1a..b59d505761 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -10,7 +10,7 @@ #ifdef TARGET_AARCH64 # define TARGET_LONG_BITS 64 -# define TARGET_PHYS_ADDR_SPACE_BITS 48 +# define TARGET_PHYS_ADDR_SPACE_BITS 52 # define TARGET_VIRT_ADDR_SPACE_BITS 52 #else # define TARGET_LONG_BITS 32 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1de31ffb40..d88662cef6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -795,7 +795,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64pfr1 = t; t = cpu->isar.id_aa64mmfr0; - t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */ + t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ cpu->isar.id_aa64mmfr0 = t; t = cpu->isar.id_aa64mmfr1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 28b4347213..950f56599e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11173,6 +11173,7 @@ static const uint8_t pamax_map[] = { [3] = 42, [4] = 44, [5] = 48, + [6] = 52, }; /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ @@ -11564,11 +11565,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, descaddr = extract64(ttbr, 0, 48); /* - * If the base address is out of range, raise AddressSizeFault. + * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR. + * + * Otherwise, if the base address is out of range, raise AddressSizeFault. * In the pseudocode, this is !IsZero(baseregister<47:outputsize>), * but we've just cleared the bits above 47, so simplify the test. */ - if (descaddr >> outputsize) { + if (outputsize > 48) { + descaddr |= extract64(ttbr, 2, 4) << 48; + } else if (descaddr >> outputsize) { level = 0; fault_type = ARMFault_AddressSize; goto do_fault; @@ -11620,7 +11625,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, } descaddr = descriptor & descaddrmask; - if (descaddr >> outputsize) { + + /* + * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12] + * of descriptor. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.31.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:31:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 11/17] target/arm: Extend arm_fi_to_lfsc to level -1 Date: Wed, 23 Feb 2022 12:31:31 -1000 Message-Id: <20220223223137.114264-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1035 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With FEAT_LPA2, rather than introducing translation level 4, we introduce level -1, below the current level 0. Extend arm_fi_to_lfsc to handle these faults. Assert that this new translation level does not leak into fault types for which it is not defined, which allows some masking of fi->level to be removed. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3d3d41ba2b..00af41d792 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -462,28 +462,51 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) case ARMFault_None: return 0; case ARMFault_AddressSize: - fsc = fi->level & 3; + assert(fi->level >= -1 && fi->level <= 3); + if (fi->level < 0) { + fsc = 0b101001; + } else { + fsc = fi->level; + } break; case ARMFault_AccessFlag: - fsc = (fi->level & 3) | (0x2 << 2); + assert(fi->level >= 0 && fi->level <= 3); + fsc = 0b001000 | fi->level; break; case ARMFault_Permission: - fsc = (fi->level & 3) | (0x3 << 2); + assert(fi->level >= 0 && fi->level <= 3); + fsc = 0b001100 | fi->level; break; case ARMFault_Translation: - fsc = (fi->level & 3) | (0x1 << 2); + assert(fi->level >= -1 && fi->level <= 3); + if (fi->level < 0) { + fsc = 0b101011; + } else { + fsc = 0b000100 | fi->level; + } break; case ARMFault_SyncExternal: fsc = 0x10 | (fi->ea << 12); break; case ARMFault_SyncExternalOnWalk: - fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12); + assert(fi->level >= -1 && fi->level <= 3); + if (fi->level < 0) { + fsc = 0b010011; + } else { + fsc = 0b010100 | fi->level; + } + fsc |= fi->ea << 12; break; case ARMFault_SyncParity: fsc = 0x18; break; case ARMFault_SyncParityOnWalk: - fsc = (fi->level & 3) | (0x7 << 2); + assert(fi->level >= -1 && fi->level <= 3); + if (fi->level < 0) { + fsc = 0b011011; + } else { + fsc = 0b011100 | fi->level; + } break; case ARMFault_AsyncParity: fsc = 0x19; From patchwork Wed Feb 23 22:31:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545229 Delivered-To: patch@linaro.org Received: by 2002:ac0:e142:0:0:0:0:0 with SMTP id r2csp1092430imn; Wed, 23 Feb 2022 14:47:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJxUNCmKXdoEyrdYwH2RH3C0B2YhlUBR2xgqKL0NyudHCDc80mAW3bNfpZjVGK0OC00aobQQ X-Received: by 2002:ac8:5a91:0:b0:2de:25c5:1d68 with SMTP id c17-20020ac85a91000000b002de25c51d68mr8599qtc.94.1645656464882; Wed, 23 Feb 2022 14:47:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645656464; cv=none; d=google.com; s=arc-20160816; b=sHl0ql82LAMecc6DO5idH5yJ5PAmR/kISm+EkoMX6I/HK9BcJ56OfLzWK+nEbPw4T5 Lb3xbhoPbXHJ0MqrThlw6VUErou9fk3rj7s8CTdcYh6eY9ymRUQWb9TrDUYgbuEPYwft qIXOND9MyX7GqYDB62iChjsrKZCU4rciYfBV/HzzH+Qc4NZluvo3I0x1kDq0RoIAqhw9 whvnAHkIfNGIFcpZLRetRsWXLVeMeeJda4Zq/qbmVjfHVtekCQbFfZAVqHj43Vd19JZe 2yNEm77GGNaDlAhtV+w7qF3wetblGgyHnx9jvH8CUWm/gZ/i4/5RhrPZwwwUxTyjBpKL yBvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Uavi3yQmU7TEij7jJpcySVBC3+TVvlm3sHX3b1s1W6c=; b=qOMSkJiOoBbq2+UPinvIANGHQAKK8fEyqlaT4TWq9NQQG94mTjTNN8k6KfS4kTnFZn lyYNrcROu6SE1AeCmPjstpZTCj/4WICLx8iPQ0RGuYKINSE7mPVOSlRQO2WAfzlWXP2z rXFXGm4I7K33Yo2E8O+mscCAynjzWvNQ1fWMvglOMcfcNuTzg6uZFvmejJ7NlNT03EqX Oz7+sy/HG7+2swy7Jl0gaAofNWej8BCFWTRcAp6NrT8fhy1y5amIsOkAcmexDRqEmYrE /OtRXP6MgWG5q/AfLkyHsU0+GM8vVMGTF9/g2u6UcrwJf1dtlQH+kMHe2Xo32FX3QORe 1FCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=E4feHmkw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.31.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:31:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 12/17] target/arm: Introduce tlbi_aa64_get_range Date: Wed, 23 Feb 2022 12:31:32 -1000 Message-Id: <20220223223137.114264-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1036 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Merge tlbi_aa64_range_get_length and tlbi_aa64_range_get_base, returning a structure containing both results. Pass in the ARMMMUIdx, rather than the digested two_ranges boolean. This is in preparation for FEAT_LPA2, where the interpretation of 'value' depends on the effective value of DS for the regime. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 58 +++++++++++++++++++-------------------------- 1 file changed, 24 insertions(+), 34 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 950f56599e..31c2a716f2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4511,70 +4511,60 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, } #ifdef TARGET_AARCH64 -static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, - uint64_t value) -{ - unsigned int page_shift; - unsigned int page_size_granule; - uint64_t num; - uint64_t scale; - uint64_t exponent; +typedef struct { + uint64_t base; uint64_t length; +} TLBIRange; + +static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, + uint64_t value) +{ + unsigned int page_size_granule, page_shift, num, scale, exponent; + TLBIRange ret = { }; - num = extract64(value, 39, 5); - scale = extract64(value, 44, 2); page_size_granule = extract64(value, 46, 2); if (page_size_granule == 0) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", page_size_granule); - return 0; + return ret; } page_shift = (page_size_granule - 1) * 2 + 12; - + num = extract64(value, 39, 5); + scale = extract64(value, 44, 2); exponent = (5 * scale) + 1; - length = (num + 1) << (exponent + page_shift); - return length; -} + ret.length = (num + 1) << (exponent + page_shift); -static uint64_t tlbi_aa64_range_get_base(CPUARMState *env, uint64_t value, - bool two_ranges) -{ - /* TODO: ARMv8.7 FEAT_LPA2 */ - uint64_t pageaddr; - - if (two_ranges) { - pageaddr = sextract64(value, 0, 37) << TARGET_PAGE_BITS; + if (regime_has_2_ranges(mmuidx)) { + ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS; } else { - pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS; + ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS; } - return pageaddr; + return ret; } static void do_rvae_write(CPUARMState *env, uint64_t value, int idxmap, bool synced) { ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap); - bool two_ranges = regime_has_2_ranges(one_idx); - uint64_t baseaddr, length; + TLBIRange range; int bits; - baseaddr = tlbi_aa64_range_get_base(env, value, two_ranges); - length = tlbi_aa64_range_get_length(env, value); - bits = tlbbits_for_regime(env, one_idx, baseaddr); + range = tlbi_aa64_get_range(env, one_idx, value); + bits = tlbbits_for_regime(env, one_idx, range.base); if (synced) { tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), - baseaddr, - length, + range.base, + range.length, idxmap, bits); } else { - tlb_flush_range_by_mmuidx(env_cpu(env), baseaddr, - length, idxmap, bits); + tlb_flush_range_by_mmuidx(env_cpu(env), range.base, + range.length, idxmap, bits); } } From patchwork Wed Feb 23 22:31:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545230 Delivered-To: patch@linaro.org Received: by 2002:ac0:e142:0:0:0:0:0 with SMTP id r2csp1092787imn; Wed, 23 Feb 2022 14:48:27 -0800 (PST) X-Google-Smtp-Source: ABdhPJyBb80EmKEvovvurKfGI6N2iAZ3nPIcRLLDLASGOpdRyvEbm50m4S7ppciAFDl3BiQZ9bo/ X-Received: by 2002:a05:620a:ec9:b0:608:292f:8479 with SMTP id x9-20020a05620a0ec900b00608292f8479mr1344qkm.328.1645656507100; Wed, 23 Feb 2022 14:48:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645656507; cv=none; d=google.com; s=arc-20160816; b=XJ2swLpq97jquVpzRlGF78BoBsPwK6vGsQKgIyY/G9suPuehofohbcGFnK8J99NHGc HnFHW7EWisb2WHHknBt68GVcDurHTMXn5GpO1WrDNjpFdcyPcgu9xgS93QXTE4zqNtJ/ Uskz+tYqKK7nsFwm/2ymfR3DxGMHIU0PB/yzAm5JlVs4OK3dmk5Z35w+WMeMXdYYwLEp 1x1PeNuPg4qQ6/8QVVeawu/3cZW8BlXcsz3b2kR1DpYjuncOd9JascBtczQJ03IaruP9 LnILkcAFwNHJjALzUPk4HvjXZIHVh4WZPxg0TmOzldK9X5c0rVAr/VVPnJzbJGJWE7HU UGig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iuG8ohkKwqyyIJ7svsXNRHI3s70BPYfliw43HdSQEsk=; b=VQqyYi4V3c+FZxHJbYxOTQgwDUhnH6pdoQzW/5QSduqglDtSmgpAkjaaHAqoL57mE9 TiXWSBoGOmv+Pay8eD4mfXJuF2hiMPfZRiZFZ6WUJZmyVlDvciES5krI6xrZs14HF3l7 zZjKsYpL9EnoZ3hE2F2qwZjjTqN2Mcviz6pzf3eec1beS10b2AVPbVGwix3Xh/8pwraI QIncDY3TE3ycVe1u0SOizhd6TPZYYVDszbSP1NZ9pjnz1YSRCjoahTlNXUNpfmAGFD7E Ckwa+1Va/U2EKet2iiPWQ3naDdwy/wLsBy+OZvL227SEFrxiJCmnZ4hAEv9TP7boxi/f vzCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WddS2ivj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.32.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:32:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 13/17] target/arm: Fix TLBIRange.base for 16k and 64k pages Date: Wed, 23 Feb 2022 12:31:33 -1000 Message-Id: <20220223223137.114264-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1033 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The shift of the BaseADDR field depends on the translation granule in use. Fixes: 84940ed8255 ("target/arm: Add support for FEAT_TLBIRANGE") Reported-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 31c2a716f2..e455397fb5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4538,10 +4538,11 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, ret.length = (num + 1) << (exponent + page_shift); if (regime_has_2_ranges(mmuidx)) { - ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS; + ret.base = sextract64(value, 0, 37); } else { - ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS; + ret.base = extract64(value, 0, 37); } + ret.base <<= page_shift; return ret; } From patchwork Wed Feb 23 22:31:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545231 Delivered-To: patch@linaro.org Received: by 2002:ac0:e142:0:0:0:0:0 with SMTP id r2csp1093921imn; Wed, 23 Feb 2022 14:50:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJyeUibRQSrOZBqSYk3uhBl0R1QLG7XfD5iJuKbnluG2P4kMhiUYhhYz/lhEdhKqb6Yaifdj X-Received: by 2002:a37:a487:0:b0:60d:d3a1:a660 with SMTP id n129-20020a37a487000000b0060dd3a1a660mr7899qke.178.1645656628482; Wed, 23 Feb 2022 14:50:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645656628; cv=none; d=google.com; s=arc-20160816; b=b4+KB4N75P1S6X4ClQxvmVUhKwoJPNOcMP1MKHbymiUL8QcV1OsPKQUDmHfvUSX4jO BNru+Bn6oxjCGeIW/ge4Xc1rhwhV2GSH7W3FAZO+5VC9N4gFuJlDteG4mF5rX+5hP3SQ eIeNimMSGbwNSNg6kPAwQyjbhsm8WaC0L9fSHdceK+c5peREELPSKIMJP74N+6hdFHOJ +X6RLq4aqicalde5wSgHnBirG40BGgDZ2nMlaJDwW/8ZMfYn+Ub6YtHlXIcdwymY1I3q nExZJevUTIfZouEZhUENQ4EkVXdQl6to60FFPE9IfFkvjUV3HzGXApMASpuMB6YMLkBq UNvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WFTKQrLiJ3VwSgvkt/IhaEgBVQ3+b8tLX7nUBsUG9rM=; b=Nr1szpnF2hR75aWGFMHqLlkSiuZWPzeqQ2kqgOzA3i3YcVm1QfH5UUfdE8H4wNJZjv XvmwWkg5px+lKR/ULzRjKQWGC0QSwe/rkIoJYlSujfbrTXJotKl5VWiMHfxaUlKLfzU+ vmh5n8PudKWdwwqg2IIYA/Oiz2y7b/9CVIsl2HYqmR1/lcTyIlj5iWr7kfq65zREIImG IKICq1STfKfDAiLmZpfI0RDQBcxETf3iOw6lttVh6yFD4AqD4temlX3reAzJFJCCB4eQ 7mMCbE1bnHDEVSdxSeneOSIj4mMmefYMwUCmX6b1ikffTWaVLadWCGjqihe48jdPeF3P 8ziQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nWPSZzl1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.32.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:32:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 14/17] target/arm: Validate tlbi TG matches translation granule in use Date: Wed, 23 Feb 2022 12:31:34 -1000 Message-Id: <20220223223137.114264-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::431 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For FEAT_LPA2, we will need other ARMVAParameters, which themselves depend on the translation granule in use. We might as well validate that the given TG matches; the architecture "does not require that the instruction invalidates any entries" if this is not true. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e455397fb5..3a7f5cf6f0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4520,12 +4520,16 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, uint64_t value) { unsigned int page_size_granule, page_shift, num, scale, exponent; + /* Extract one bit to represent the va selector in use. */ + uint64_t select = sextract64(value, 36, 1); + ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true); TLBIRange ret = { }; page_size_granule = extract64(value, 46, 2); - if (page_size_granule == 0) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", + /* The granule encoded in value must match the granule in use. */ + if (page_size_granule != (param.using64k ? 3 : param.using16k ? 2 : 1)) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n", page_size_granule); return ret; } @@ -4537,7 +4541,7 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, ret.length = (num + 1) << (exponent + page_shift); - if (regime_has_2_ranges(mmuidx)) { + if (param.select) { ret.base = sextract64(value, 0, 37); } else { ret.base = extract64(value, 0, 37); From patchwork Wed Feb 23 22:31:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545232 X-Google-Smtp-Source: ABdhPJyV7/bATVbO2lKQpuYA6UHNCnMreZN0FnxFkXdcE0xzrrG6JfUdFSmXGUXmn2R/w24kPM6e X-Received: by 2002:a05:620a:199d:b0:608:102e:64d8 with SMTP id bm29-20020a05620a199d00b00608102e64d8mr1307754qkb.709.1645656654166; Wed, 23 Feb 2022 14:50:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645656654; cv=none; d=google.com; s=arc-20160816; b=hxIdpWvOuu5YIJnWSy69NfmQFe4lb8Rxv+mvxdcU6WxBHAEvHr1EicFCOS/csfz+0n Ysta6y/Zcy+jLySPsgVRBuQhLWcSxk8k07dCXCnrYYLXBrsN5R6UbdM9SrZaJ0a315fF ip0M75rCMFqGzPij9TE0z79BXc3DnNSTjLPSXSJU7XMYRQ4l/TfGyahJIpEtIpexRi23 c34LjO5jtmTH3czcu7oRCnXVSTFlyehmDLkJ+moulE81L5EpIu+BNZBoZnn+DS4umXub J6mAys+iX90sjma54RXAAA2oEBA9cbi2wrxc2/Epo9ZCiQj0ULPdcL9+Xkvtmodl30ie 9ngA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/ncep1+pfaj4VrhFhzBJtvktsI7eesl8NO/EGk2kyoM=; b=AUxSy+x3+FJNUNYX9+nk/DL4Bupvd/hIVfAsY7nr/bXg25xfaL043ypi8PjTzVs3/M +h6LCfSATwMoZHn01Y2UqOpf1HF3SYow5TVPhrprVFqQhM9VPCHfDds27Q3V11MNY/e7 72/tE0YfW3hLbTUZASpYES0jlK7NL5kNbSKK4ohn2cl251uYZYdxRKVBmwzamLu+6gqh XqE3KZr+pdA7jjsO/Obv5Nq1RCZRbLZ+h4wk8geqYs7IZ9blb5MgL36kMKa3m5QA7tvC un3uvZYrahkjfUzfLMOmY4KFpEdd/qo1XUeHEUBgxa110/6rFRUKrRl4H25bjvn1SP9H EDOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NVeSSx7n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.32.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:32:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 15/17] target/arm: Advertise all page sizes for -cpu max Date: Wed, 23 Feb 2022 12:31:35 -1000 Message-Id: <20220223223137.114264-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We support 16k pages, but do not advertize that in ID_AA64MMFR0. The value 0 in the TGRAN*_2 fields indicates that stage2 lookups defer to the same support as stage1 lookups. This setting is deprecated, so indicate support for all stage2 page sizes directly. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d88662cef6..2fdc16bf18 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -796,6 +796,10 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64mmfr0; t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ cpu->isar.id_aa64mmfr0 = t; t = cpu->isar.id_aa64mmfr1; From patchwork Wed Feb 23 22:31:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545234 X-Google-Smtp-Source: ABdhPJwt/rWnk7lDItwyl8cy7a38yrqeNbsmtdi/3Y3pK2T6xcCbwxVVeVeuoO0/+FUOPpipd+Ux X-Received: by 2002:a05:6214:2504:b0:42d:7b1a:8dd1 with SMTP id gf4-20020a056214250400b0042d7b1a8dd1mr1758333qvb.8.1645656938801; Wed, 23 Feb 2022 14:55:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645656938; cv=none; d=google.com; s=arc-20160816; b=yqSGLamihsyFMxAMHiWtWCwu4YnzJ1YzCyOmln7EOVwa2eaHF1/+eIQghtYuCRUhey 4mnqj6IrZ2UA52JY1CPy2T51nb8jRRP1rlcYL2U+Wdmpn9wHU3XCKPSF827N13e/ekIG j2klfHjNVsw+XeMa++b7fJTkORNB8haPokZECJ3RLi9zsIke/z7l3/8aXafq7f7CaB4/ 2WW5IMjp9XjrcCySzXdjkCkTDUDO6OiPEyiSCOIjPMNTHlHGnsJ/dmDK66vVVV/jttzG xwARgChlqxYO/eQqMHavidI3nNtR4kKvidP5dp0JJHhprHtBLhIpa+cvWRAnfkUawZ4k g7Kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mWBxuwt8V3FGFQ5JHqGb8ST2XOZhCQVYfBFh0OJ1LZY=; b=cGfaKUmgbTz+5fXTGTJy8NAXaeLSzdPJBdmdlsHXWlnuK2gYe6+aFzGHItgaa74ivF waqmLh451BSie75Z2gI7QWSqtRPz5QRLdZJwH0gPynTuHMHczuWWRnrNfZ6ZRYo2gwqg BSZbE+oatOrjbbuL68SAYPhDWk9Hw7C8Q/+RqUNn/vkwjVKCtzyFfw0Q3Y0dzcm+APbB Pw+oU69WNyWtELa3PjTQ3gQXPh8ZFYYIFP7mfRCuaEnFdCIe7eKD1GkIkiAbTgm0+i64 ULCHggyLEj4lShLNSpXa55uSiijFWzlPVk84BbwBj4QVfWQdZDUezKTziRUnLMF4xFww AlKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hTKynpU4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.32.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:32:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 16/17] tests/avocado: Limit test_virt_tcg_gicv[23] to cortex-a72 Date: Wed, 23 Feb 2022 12:31:36 -1000 Message-Id: <20220223223137.114264-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::430 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Beraldo Leal , =?utf-8?q?Phi?= =?utf-8?q?lippe_Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , qemu-arm@nongnu.org, Cleber Rosa , alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These tests currently use Fedora Core 31, with a v5.3.7 kernel, which is broken vs FEAT_LPA2. Before we can re-enable these tests for -cpu max, we need to advance to at least a v5.12 kernel. Signed-off-by: Richard Henderson --- Fedora Cloud 35 uses a v5.14 kernel, and does work with FEAT_LPA2. However, I have no idea how to update the makefile/avocado combo to get that to happen. Cc: Cleber Rosa Cc: Philippe Mathieu-Daudé Cc: Wainer dos Santos Moschetta Cc: Beraldo Leal --- tests/avocado/boot_linux.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py index ab19146d1e..a79c1578a6 100644 --- a/tests/avocado/boot_linux.py +++ b/tests/avocado/boot_linux.py @@ -74,7 +74,7 @@ def add_common_args(self): def test_virt_tcg_gicv2(self): """ :avocado: tags=accel:tcg - :avocado: tags=cpu:max + :avocado: tags=cpu:cortex-a72 :avocado: tags=device:gicv2 """ self.require_accelerator("tcg") @@ -86,7 +86,7 @@ def test_virt_tcg_gicv2(self): def test_virt_tcg_gicv3(self): """ :avocado: tags=accel:tcg - :avocado: tags=cpu:max + :avocado: tags=cpu:cortex-a72 :avocado: tags=device:gicv3 """ self.require_accelerator("tcg") From patchwork Wed Feb 23 22:31:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545233 X-Google-Smtp-Source: ABdhPJzgh6bshun9QryzQydByvaXop18X+Gra6/e/gMLTajwbQr/Ko7LmJY3G2Sbxf3LX/wCuhEQ X-Received: by 2002:a05:622a:2c6:b0:2dd:2d54:6781 with SMTP id a6-20020a05622a02c600b002dd2d546781mr1947962qtx.649.1645656780479; Wed, 23 Feb 2022 14:53:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645656780; cv=none; d=google.com; s=arc-20160816; b=pACr6MWsAd9oKh7WH9IhEbC0mqgejuUqWiRlWjxog9lJZdfp3WRBeGhUiAfWBugkRM ECvBdLbsDu1h7hnpenqFoL4Dx+bSFCGY9/X3tjPTOBYNM0TNcHzM5/klrgIcGsf4MfKL /1DW3sKNnJgDkfO1unX4v0om8i1MZ+gZhHt3hwVFcBIof/XyZ7nIOQcOZBcuwzJqX5u2 GDO5AgsyDFGlTaRIJwUhQebw0FtOFlfUWEQFWPJFGtjHH9rKa0YUyhbipkwU/9czu86K I76abV8VTkK1j0Q88ICvU+UDy/YBqgn7Uf/mMwzcbSN0+wrr2DBUI290f9otrdxc0nPZ 8Veg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=19hfjB18qiT1jmcGWmvL02wOHBgHmeraSiuqJSfuTKE=; b=WKwksAQoyV/TlWjQ9H6wAGS0wDyZzBUXb4oWlkyGBEd6Tm3Ga+n+gr6/II9RAgXbKN 5OSa7aPki5QR9Pd3e5KGaS2/TD7Y/bVilAZLsJhIwvNdWQ3DVFktK72RMnHrD4T0OSg2 KIlCGGi53wvivwekt/lEs9Zwe2LCZ/hrhP8sW4BvrLsCgfKOMZ3nYTfDYpqfhb93z81b 4VHXcj7/CBtRtPj1+TxL5z1PXw0wac+ntqQX5eMP8SxNa5YVglUYhIfzEVEVnRpdLAJE gCz7cLk4Ax3q3Ym98R+4Zj7yWb/L++fGrECAxePJtRgPPU2kDhXRgsASOXrsGMy68EuB zmAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fboG4XYx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.32.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:32:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 17/17] target/arm: Implement FEAT_LPA2 Date: Wed, 23 Feb 2022 12:31:37 -1000 Message-Id: <20220223223137.114264-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This feature widens physical addresses (and intermediate physical addresses for 2-stage translation) from 48 to 52 bits, when using 4k or 16k pages. This introduces the DS bit to TCR_ELx, which is RES0 unless the page size is enabled and supports LPA2, resulting in the effective value of DS for a given table walk. The DS bit changes the format of the page table descriptor slightly, moving the PS field out to TCR so that all pages have the same sharability and repurposing those bits of the page table descriptor for the highest bits of the output address. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Check DS in tlbi_aa64_get_range. Check TGRAN4_2 and TGRAN16_2. --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 22 ++++++++ target/arm/internals.h | 2 + target/arm/cpu64.c | 7 ++- target/arm/helper.c | 102 +++++++++++++++++++++++++++++----- 5 files changed, 116 insertions(+), 18 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 0053ddce20..520fd39071 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -25,6 +25,7 @@ the following architecture extensions: - FEAT_JSCVT (JavaScript conversion instructions) - FEAT_LOR (Limited ordering regions) - FEAT_LPA (Large Physical Address space) +- FEAT_LPA2 (Large Physical and virtual Address space v2) - FEAT_LRCPC (Load-acquire RCpc instructions) - FEAT_LRCPC2 (Load-acquire RCpc instructions v2) - FEAT_LSE (Large System Extensions) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c52d56f669..24d9fff170 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4284,6 +4284,28 @@ static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; } +static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; +} + +static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); +} + +static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; +} + +static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); +} + static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; diff --git a/target/arm/internals.h b/target/arm/internals.h index 00af41d792..a34be2e459 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1056,6 +1056,7 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) typedef struct ARMVAParameters { unsigned tsz : 8; unsigned ps : 3; + unsigned sh : 2; unsigned select : 1; bool tbi : 1; bool epd : 1; @@ -1063,6 +1064,7 @@ typedef struct ARMVAParameters { bool using16k : 1; bool using64k : 1; bool tsz_oob : 1; /* tsz has been clamped to legal range */ + bool ds : 1; } ARMVAParameters; ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2fdc16bf18..fc3c65ab2a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -796,10 +796,11 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64mmfr0; t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ - t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ - t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ - t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ cpu->isar.id_aa64mmfr0 = t; t = cpu->isar.id_aa64mmfr1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 3a7f5cf6f0..088956eecf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4546,6 +4546,14 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, } else { ret.base = extract64(value, 0, 37); } + if (param.ds) { + /* + * With DS=1, BaseADDR is always shifted 16 so that it is able + * to address all 52 va bits. The input address is perforce + * aligned on a 64k boundary regardless of translation granule. + */ + page_shift = 16; + } ret.base <<= page_shift; return ret; @@ -11081,8 +11089,13 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, const int grainsize = stride + 3; int startsizecheck; - /* Negative levels are never allowed. */ - if (level < 0) { + /* + * Negative levels are usually not allowed... + * Except for FEAT_LPA2, 4k page table, 52-bit address space, which + * begins with level -1. Note that previous feature tests will have + * eliminated this combination if it is not enabled. + */ + if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) { return false; } @@ -11223,8 +11236,9 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; - bool epd, hpd, using16k, using64k, tsz_oob; - int select, tsz, tbi, max_tsz, min_tsz, ps; + bool epd, hpd, using16k, using64k, tsz_oob, ds; + int select, tsz, tbi, max_tsz, min_tsz, ps, sh; + ARMCPU *cpu = env_archcpu(env); if (!regime_has_2_ranges(mmu_idx)) { select = 0; @@ -11238,7 +11252,9 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, hpd = extract32(tcr, 24, 1); } epd = false; + sh = extract32(tcr, 12, 2); ps = extract32(tcr, 16, 3); + ds = extract64(tcr, 32, 1); } else { /* * Bit 55 is always between the two regions, and is canonical for @@ -11248,6 +11264,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, if (!select) { tsz = extract32(tcr, 0, 6); epd = extract32(tcr, 7, 1); + sh = extract32(tcr, 12, 2); using64k = extract32(tcr, 14, 1); using16k = extract32(tcr, 15, 1); hpd = extract64(tcr, 41, 1); @@ -11257,24 +11274,51 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, using64k = tg == 3; tsz = extract32(tcr, 16, 6); epd = extract32(tcr, 23, 1); + sh = extract32(tcr, 28, 2); hpd = extract64(tcr, 42, 1); } ps = extract64(tcr, 32, 3); + ds = extract64(tcr, 59, 1); } - if (cpu_isar_feature(aa64_st, env_archcpu(env))) { + if (cpu_isar_feature(aa64_st, cpu)) { max_tsz = 48 - using64k; } else { max_tsz = 39; } + /* + * DS is RES0 unless FEAT_LPA2 is supported for the given page size; + * adjust the effective value of DS, as documented. + */ min_tsz = 16; if (using64k) { - if (cpu_isar_feature(aa64_lva, env_archcpu(env))) { + if (cpu_isar_feature(aa64_lva, cpu)) { + min_tsz = 12; + } + ds = false; + } else if (ds) { + switch (mmu_idx) { + case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: + if (using16k) { + ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu); + } else { + ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu); + } + break; + default: + if (using16k) { + ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu); + } else { + ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu); + } + break; + } + if (ds) { min_tsz = 12; } } - /* TODO: FEAT_LPA2 */ if (tsz > max_tsz) { tsz = max_tsz; @@ -11296,6 +11340,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, return (ARMVAParameters) { .tsz = tsz, .ps = ps, + .sh = sh, .select = select, .tbi = tbi, .epd = epd, @@ -11303,6 +11348,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, .using16k = using16k, .using64k = using64k, .tsz_oob = tsz_oob, + .ds = ds, }; } @@ -11528,10 +11574,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * VTCR_EL2.SL0 field (whose interpretation depends on the page size) */ uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); + uint32_t sl2 = extract64(tcr->raw_tcr, 33, 1); uint32_t startlevel; bool ok; - if (!aarch64 || stride == 9) { + /* SL2 is RES0 unless DS=1 & 4kb granule. */ + if (param.ds && stride == 9 && sl2) { + if (sl0 != 0) { + level = 0; + fault_type = ARMFault_Translation; + goto do_fault; + } + startlevel = -1; + } else if (!aarch64 || stride == 9) { /* AArch32 or 4KB pages */ startlevel = 2 - sl0; @@ -11585,10 +11640,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0 * or an AddressSize fault is raised. So for v8 we extract those SBZ * bits as part of the address, which will be checked via outputsize. - * For AArch64, the address field always goes up to bit 47 (with extra - * bits for FEAT_LPA placed elsewhere). AArch64 implies v8. + * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2; + * the highest bits of a 52-bit output are placed elsewhere. */ - if (arm_feature(env, ARM_FEATURE_V8)) { + if (param.ds) { + descaddrmask = MAKE_64BIT_MASK(0, 50); + } else if (arm_feature(env, ARM_FEATURE_V8)) { descaddrmask = MAKE_64BIT_MASK(0, 48); } else { descaddrmask = MAKE_64BIT_MASK(0, 40); @@ -11623,11 +11680,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12] - * of descriptor. Otherwise, if descaddr is out of range, raise - * AddressSizeFault. + * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of + * descaddr are in [9:8]. Otherwise, if descaddr is out of range, + * raise AddressSizeFault. */ if (outputsize > 48) { - descaddr |= extract64(descriptor, 12, 4) << 48; + if (param.ds) { + descaddr |= extract64(descriptor, 8, 2) << 50; + } else { + descaddr |= extract64(descriptor, 12, 4) << 48; + } } else if (descaddr >> outputsize) { fault_type = ARMFault_AddressSize; goto do_fault; @@ -11721,7 +11783,17 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, assert(attrindx <= 7); cacheattrs->attrs = extract64(mair, attrindx * 8, 8); } - cacheattrs->shareability = extract32(attrs, 6, 2); + + /* + * For FEAT_LPA2 and effective DS, the SH field in the attributes + * was re-purposed for output address bits. The SH attribute in + * that case comes from TCR_ELx, which we extracted earlier. + */ + if (param.ds) { + cacheattrs->shareability = param.sh; + } else { + cacheattrs->shareability = extract32(attrs, 6, 2); + } *phys_ptr = descaddr; *page_size_ptr = page_size;