From patchwork Fri Nov 30 06:52:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 152489 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3313212ljp; Thu, 29 Nov 2018 22:55:15 -0800 (PST) X-Google-Smtp-Source: AFSGD/VN8rN0oIulHkaxTPu/df6Z5azLH5ahkjF5VGIPsBb7HLmr8bn393BrFXttErFx63eDoxRC X-Received: by 2002:a17:902:2c03:: with SMTP id m3mr4704292plb.125.1543560915649; Thu, 29 Nov 2018 22:55:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543560915; cv=none; d=google.com; s=arc-20160816; b=ToTB3j5mvDshbJtIT8RxXiX3Z9iDIw2rSFFZB0g9b1tuiSYFIONFVzDj7qYGmN40CU v9a/ScOUI/iBTSanZUKdNo1ZqxwPSfNKCVJffLe4t/7W+dAzeKuZifqewL5+/Sse8nWk 0GjrmyWwUgIlpkigK0RQRYKtBSEtanJ61iTDWQnqT6v+IpbdtqWHEis610WExWGj7UGj TpkIBK6AubZu9EzbwqXoW73YXWjtf6bYuU/itLqvg9ulftKMDgwaGNcxZ1dab+NcNRMx lIJB9NlfCQO9KveCuv6UrwO7+M49JAHM9G1k728+oJpZFfpfQOAJZBXfXI/Mo7V1XG/i cHbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=QZvfeZHAnMUYvaTlclKUDRPDClRnA84dF7+NxVt5aH0=; b=a5LPjLrql9OMq0qat2/PRSvosqrySmUOHH1s0yw5qzZkvJuqryWKKbEvYV+htywMok MpVvkCcWD/mdSBjDlJiyO3v9yiT+cDSUC04SdLNrHukhLCSvIAKlKKqPuJfv98kqtsjD TTtrdpYEdb2rCqFrOZSs0huwFLTHnW5cgaAuxLDDEcF4f1CMcraWtDEHfwr05Mpk0e/v S5EjpDi26OKjaJ0Kk/fKzH7AGVrtKgTK7ZQTuhYN6JmuPxwsZz9i9A3Jiw74VYmUlxQe xPCG2FMWj/+VKaqLIux5IO9OXNJTvl6pC5WIexrk9H5igH61TM9D11ycP4e7NMhdOVhP s6Ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="F2Cxd1+/"; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id w128sm5859175pfw.79.2018.11.29.22.55.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Nov 2018 22:55:10 -0800 (PST) From: Bjorn Andersson To: Michael Turquette , Stephen Boyd Cc: Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Marc Gonzalez , Amit Kucheria Subject: [PATCH 2/3] clk: qcom: gcc-msm8998: Disable halt check of UFS clocks Date: Thu, 29 Nov 2018 22:52:58 -0800 Message-Id: <20181130065259.26497-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181130065259.26497-1-bjorn.andersson@linaro.org> References: <20181130065259.26497-1-bjorn.andersson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop the halt check of the UFS symbol clocks, in accordance with other platforms. This makes clk_disable_unused() happy and makes it possible to turn the clocks on again without an error. Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-msm8998.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.18.0 diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index d89f8e7c2a59..3d232d266d72 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2403,7 +2403,7 @@ static struct clk_branch gcc_ufs_phy_aux_clk = { static struct clk_branch gcc_ufs_rx_symbol_0_clk = { .halt_reg = 0x75014, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x75014, .enable_mask = BIT(0), @@ -2416,7 +2416,7 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = { static struct clk_branch gcc_ufs_rx_symbol_1_clk = { .halt_reg = 0x7605c, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x7605c, .enable_mask = BIT(0), @@ -2429,7 +2429,7 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = { static struct clk_branch gcc_ufs_tx_symbol_0_clk = { .halt_reg = 0x75010, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x75010, .enable_mask = BIT(0), From patchwork Fri Nov 30 06:52:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 152490 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3313226ljp; Thu, 29 Nov 2018 22:55:16 -0800 (PST) X-Google-Smtp-Source: AFSGD/Uz97UIz1iixww1gDicY0lRBr3c95iCSli7loYXoUErJLHwgvA493ByYe68Oi8mOR27kFaP X-Received: by 2002:a17:902:3281:: with SMTP id z1mr4644871plb.296.1543560916326; Thu, 29 Nov 2018 22:55:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543560916; cv=none; d=google.com; s=arc-20160816; b=wXbW1YEhd54r/6pAld3iflZ0GdtYKDsfCAvtUadNVCcUZfmq1tBraVVTfhqQNXzhOD PT1SKARDrIIuF4iZYo8N/cxY/ZDlp2/T+1iCumkTArqPLXii+5VN5paqyJ7u2Uzjb2FQ QZsffagfzwIBvRyl4khH1VNAhX0jqN6pnAPYKE6pjXzb/mHLSeeEJ1sfp/7FFJ+dpzHi aApThtg5VlUEqj9cnerJCNJezC15mWh5W87riav3UcFvUhMCbwR1K3chj5Y1XQQHVQxq dhCpofYQGTo662B/cp9YaOBw2+CDLmlgDLxOvjKTgGN5Ca+ZWtJI1bzNBpzPOpqPrdVZ gTug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=hnyjjpjHBnVhzfF63jdnmIEwzmmZ945S0nK4qK9f2bw=; b=cE9yV5TL0ZvRr6Rd9m6rAL1D1VzmzOm7tR4IS5jlKyjZVVL76Utbh0w7iqmLW9hWHp E3m9NifZOMnyGGs9BYu2nPXDTmR72pNIM2gypEs9pZVNlkQEIXJA0HyXvp+cJMws8Xaf fnBF7PUn4m81+aFHraKG2y0z/T1S23nLQBn4fXUIzVtYF1mGr4K1f6Lg1dbdwGfezBZ9 JOk8h4L+LT+Mu1P5CVvNDGCUaKAeYGj6ezlNqkNxrAQCkvfOkYM/w6Vy/7kg5xWEaQzc W2HnnkQH8mnK60EzyG3aO7tu1tzVC1Ym4hMNwGXL98deb2M6QKmAF1hOK2e69o1V+H3M 5F0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HNjKLnsq; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id w128sm5859175pfw.79.2018.11.29.22.55.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Nov 2018 22:55:11 -0800 (PST) From: Bjorn Andersson To: Michael Turquette , Stephen Boyd Cc: Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Marc Gonzalez , Amit Kucheria Subject: [PATCH 3/3] clk: qcom: gcc-msm8998: Add clkref clocks Date: Thu, 29 Nov 2018 22:52:59 -0800 Message-Id: <20181130065259.26497-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181130065259.26497-1-bjorn.andersson@linaro.org> References: <20181130065259.26497-1-bjorn.andersson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add clkref clocks for usb3, hdmi, ufs, pcie, and usb2. They are all sourced off CXO_IN, so parent them off "xo" until a proper link to the rpmcc can be described in DT. Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-msm8998.c | 75 ++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-msm8998.h | 5 ++ 2 files changed, 80 insertions(+) -- 2.18.0 diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index 3d232d266d72..3cf16a4f931c 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2543,6 +2543,76 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { }, }; +static struct clk_branch gcc_hdmi_clkref_clk = { + .halt_reg = 0x88000, + .clkr = { + .enable_reg = 0x88000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_hdmi_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_clkref_clk = { + .halt_reg = 0x88004, + .clkr = { + .enable_reg = 0x88004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_clkref_clk = { + .halt_reg = 0x88008, + .clkr = { + .enable_reg = 0x88008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_clkref_clk = { + .halt_reg = 0x8800c, + .clkr = { + .enable_reg = 0x8800c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_rx1_usb2_clkref_clk = { + .halt_reg = 0x88014, + .clkr = { + .enable_reg = 0x88014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rx1_usb2_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc pcie_0_gdsc = { .gdscr = 0x6b004, .gds_hw_ctrl = 0x0, @@ -2735,6 +2805,11 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, + [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr, + [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, + [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, + [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr, + [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, }; static struct gdsc *gcc_msm8998_gdscs[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 58a242e656b1..b3448800980a 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -180,6 +180,11 @@ #define USB30_MASTER_CLK_SRC 163 #define USB30_MOCK_UTMI_CLK_SRC 164 #define USB3_PHY_AUX_CLK_SRC 165 +#define GCC_USB3_CLKREF_CLK 166 +#define GCC_HDMI_CLKREF_CLK 167 +#define GCC_UFS_CLKREF_CLK 168 +#define GCC_PCIE_CLKREF_CLK 169 +#define GCC_RX1_USB2_CLKREF_CLK 170 #define PCIE_0_GDSC 0 #define UFS_GDSC 1