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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id r2sm3691694wmq.24.2022.02.17.15.57.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Feb 2022 15:57:04 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 02/16] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation Date: Fri, 18 Feb 2022 00:56:49 +0100 Message-Id: <20220217235703.26641-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220217235703.26641-1-ansuelsmth@gmail.com> References: <20220217235703.26641-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc-common.yaml as a template and remove the compatible from qcom,gcc.yaml Signed-off-by: Ansuel Smith --- .../bindings/clock/qcom,gcc-apq8064.yaml | 29 +++++-------------- .../bindings/clock/qcom,gcc-other.yaml | 3 -- 2 files changed, 7 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml index 8e2eac6cbfb9..97936411b6b4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml @@ -6,6 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global Clock & Reset Controller Binding for APQ8064 +allOf: + - $ref: qcom,gcc.yaml# + maintainers: - Stephen Boyd - Taniya Das @@ -17,22 +20,12 @@ description: | See also: - dt-bindings/clock/qcom,gcc-msm8960.h - dt-bindings/reset/qcom,gcc-msm8960.h + - dt-bindings/clock/qcom,gcc-apq8084.h + - dt-bindings/reset/qcom,gcc-apq8084.h properties: compatible: - const: qcom,gcc-apq8064 - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 + const: qcom,gcc-apq8084 nvmem-cells: minItems: 1 @@ -53,21 +46,13 @@ properties: '#thermal-sensor-cells': const: 1 - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' - nvmem-cells - nvmem-cell-names - '#thermal-sensor-cells' -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml index 824d80530683..2703b53150d8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml @@ -15,8 +15,6 @@ description: power domains. See also: - - dt-bindings/clock/qcom,gcc-apq8084.h - - dt-bindings/reset/qcom,gcc-apq8084.h - dt-bindings/clock/qcom,gcc-ipq4019.h - dt-bindings/clock/qcom,gcc-ipq6018.h - dt-bindings/reset/qcom,gcc-ipq6018.h @@ -40,7 +38,6 @@ allOf: properties: compatible: enum: - - qcom,gcc-apq8084 - qcom,gcc-ipq4019 - qcom,gcc-ipq6018 - qcom,gcc-ipq8064 From patchwork Thu Feb 17 23:56:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 543479 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8FA7C433F5 for ; Thu, 17 Feb 2022 23:57:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229844AbiBQX5a (ORCPT ); Thu, 17 Feb 2022 18:57:30 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:52874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229827AbiBQX50 (ORCPT ); Thu, 17 Feb 2022 18:57:26 -0500 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D2626419BE; Thu, 17 Feb 2022 15:57:08 -0800 (PST) Received: by mail-wr1-x429.google.com with SMTP id x5so6814085wrg.13; Thu, 17 Feb 2022 15:57:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=u469mMf11FmBaVlEEJAE/kqasFIogYLGPGt/lzpdIA8=; b=lPHwNX27fK0/ySI3rIP5nQfAaPbHlv+g461yKHUe+HA+mMp3xXqJnvr+h4B6xCXHx/ gxCe/RdAo+t7eeqW/KC/XgmJsUz2GuSlygfO7EHMJbA0LX4jTn0q+ZFkMv4JWLHaqiXr Z7KPsVD7X3uxq/2fKqUB93KFPvAi7jRh7tBZov2TWM/z6A9gRC7yp3KLVy8JaaHneQi+ V7PgDkkB24nUPecdWbOPkjMVb585ZhSRnKuWBJrkZ1oZXGWD2p56XySlDRNV+fxYPdDt kqY64hDYPmxXd7l1vF8Lqoc3/vWZSVgXt6GWoyToLNSDyr6+ut7Dlrdoe1dhQY2ygfog MANQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u469mMf11FmBaVlEEJAE/kqasFIogYLGPGt/lzpdIA8=; b=4lTS9WZ8zhKAdm2ppNSTr2Xf/NiZhVMKdgrZtw6LpuwwRDdH9hrlPfrHhpfmSKd3fS uhQdJBvR0qxDN3jHwGUv9pDKyKvK+WYi2Kn/Nu8T3sGjxGdAk91TWf3m+YzkOb8EniZX oyCyoL8LX/C8AW4x7DVQujY7OlwX39SvXe8B/YvP/K8AajGjruNLp4yf96lF2MmKDkj6 g1NssvbD0y8JkdWoQTd0pt30rWHy4YKG6yMPccMODYDYDecfDcU07MxKZe0WYs8dwEST Lccikg6ChVW8n06s3DLjJoMbzczYegx/xRLZVsRM9i/I6APzUY4X4rpx3dL0jfk2lkw9 iT+g== X-Gm-Message-State: AOAM5327ce6d/iQncF1ILRaQcCI3N01ZBjRRLSqhz5OUgq16TFiD26on cDBMY69Zef0dzclL/uSje18= X-Google-Smtp-Source: ABdhPJyNcfglwasHkAu3TJQYc4r3TaWDjYyuIhyW/xOuFnBdIFtb0sEMFPRiYltiX0dbdQidnTm3Iw== X-Received: by 2002:a5d:4534:0:b0:1e4:9d38:2d4f with SMTP id j20-20020a5d4534000000b001e49d382d4fmr4147985wra.2.1645142227291; Thu, 17 Feb 2022 15:57:07 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id r2sm3691694wmq.24.2022.02.17.15.57.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Feb 2022 15:57:06 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 04/16] clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 Date: Fri, 18 Feb 2022 00:56:51 +0100 Message-Id: <20220217235703.26641-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220217235703.26641-1-ansuelsmth@gmail.com> References: <20220217235703.26641-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Parent gcc_pxo_pll8_pll0 had the parent definition and parent map swapped. Fix this naming error. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index d6b7adb4be38..34cddf461dba 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] = { "pll3", }; -static const struct parent_map gcc_pxo_pll8_pll0[] = { +static const struct parent_map gcc_pxo_pll8_pll0_map[] = { { P_PXO, 0 }, { P_PLL8, 3 }, { P_PLL0, 2 } }; -static const char * const gcc_pxo_pll8_pll0_map[] = { +static const char * const gcc_pxo_pll8_pll0[] = { "pxo", "pll8_vote", "pll0_vote", @@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb30_master, .clkr = { @@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb30_utmi, .clkr = { @@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb, .clkr = { @@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb, .clkr = { @@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, From patchwork Thu Feb 17 23:56:53 2022 Content-Type: text/plain; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id r2sm3691694wmq.24.2022.02.17.15.57.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Feb 2022 15:57:08 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 06/16] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents Date: Fri, 18 Feb 2022 00:56:53 +0100 Message-Id: <20220217235703.26641-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220217235703.26641-1-ansuelsmth@gmail.com> References: <20220217235703.26641-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++----------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 828383c30322..f6db7247835e 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -373,7 +373,7 @@ static struct clk_rcg gsbi1_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -424,7 +424,7 @@ static struct clk_rcg gsbi2_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -475,7 +475,7 @@ static struct clk_rcg gsbi4_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -526,7 +526,7 @@ static struct clk_rcg gsbi5_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -577,7 +577,7 @@ static struct clk_rcg gsbi6_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -628,7 +628,7 @@ static struct clk_rcg gsbi7_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -692,7 +692,7 @@ static struct clk_rcg gsbi1_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -743,7 +743,7 @@ static struct clk_rcg gsbi2_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -794,7 +794,7 @@ static struct clk_rcg gsbi4_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -845,7 +845,7 @@ static struct clk_rcg gsbi5_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -896,7 +896,7 @@ static struct clk_rcg gsbi6_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -947,7 +947,7 @@ static struct clk_rcg gsbi7_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1099,7 +1099,7 @@ static struct clk_rcg gp0_src = { .hw.init = &(struct clk_init_data){ .name = "gp0_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1150,7 +1150,7 @@ static struct clk_rcg gp1_src = { .hw.init = &(struct clk_init_data){ .name = "gp1_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1201,7 +1201,7 @@ static struct clk_rcg gp2_src = { .hw.init = &(struct clk_init_data){ .name = "gp2_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1257,7 +1257,7 @@ static struct clk_rcg prng_src = { .hw.init = &(struct clk_init_data){ .name = "prng_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, }, @@ -1321,7 +1321,7 @@ static struct clk_rcg sdc1_src = { .hw.init = &(struct clk_init_data){ .name = "sdc1_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1371,7 +1371,7 @@ static struct clk_rcg sdc3_src = { .hw.init = &(struct clk_init_data){ .name = "sdc3_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1456,7 +1456,7 @@ static struct clk_rcg tsif_ref_src = { .hw.init = &(struct clk_init_data){ .name = "tsif_ref_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1620,7 +1620,7 @@ static struct clk_rcg pcie_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1714,7 +1714,7 @@ static struct clk_rcg pcie1_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1808,7 +1808,7 @@ static struct clk_rcg pcie2_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1907,7 +1907,7 @@ static struct clk_rcg sata_ref_src = { .hw.init = &(struct clk_init_data){ .name = "sata_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2048,7 +2048,7 @@ static struct clk_rcg usb30_master_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2122,7 +2122,7 @@ static struct clk_rcg usb30_utmi_clk = { .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2196,7 +2196,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2262,7 +2262,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2398,7 +2398,7 @@ static struct clk_dyn_rcg gmac_core1_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core1_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2470,7 +2470,7 @@ static struct clk_dyn_rcg gmac_core2_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core2_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2542,7 +2542,7 @@ static struct clk_dyn_rcg gmac_core3_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core3_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2614,7 +2614,7 @@ static struct clk_dyn_rcg gmac_core4_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core4_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2674,7 +2674,7 @@ static struct clk_dyn_rcg nss_tcm_src = { .hw.init = &(struct clk_init_data){ .name = "nss_tcm_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2752,7 +2752,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = { .hw.init = &(struct clk_init_data){ .name = "ubi32_core1_src_clk", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, @@ -2805,7 +2805,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { .hw.init = &(struct clk_init_data){ .name = "ubi32_core2_src_clk", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, From patchwork Thu Feb 17 23:56:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 543477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D31F7C433EF for ; Thu, 17 Feb 2022 23:57:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229988AbiBQX6E (ORCPT ); Thu, 17 Feb 2022 18:58:04 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:53990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229904AbiBQX5i (ORCPT ); Thu, 17 Feb 2022 18:57:38 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7F6941FB9; Thu, 17 Feb 2022 15:57:13 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id x5so6814236wrg.13; Thu, 17 Feb 2022 15:57:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=v/5XpP2o4oras0yfl9rRpfS7wlw8o3QwJIwjKKbzGZY=; b=B8XMvom0WsbQwAR5Ksu2mBaZrtdaAaDLk/mRLPLajgGpUXZplL7eV620pIrY0aNN8O 0fwHzvHufrTdzSq7QYyARav9Zt21UgAW0JTAXjFAnjGjXFg3FjGC8uXMdxXo06TauPdA P23/Q/9pJNfBzkh7UkXWG6uTdBrs95xWGXrP+QO7WXtYRNsI8Zbs7VE2druKPimYY0+Y yjZjw+pg8id5MBGi8fF5KvMiJiUt9jGt0jzbJZRIAeW5sDXFWr0aFpFbN9ywl6LcFXpp ZDfvGFObHW1KdPlP+O36t+w1jIOXmtq7ZmpLYCM7hQ7VS5WQ4gfP4SKQrW7Q703Sz7cO 3+wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v/5XpP2o4oras0yfl9rRpfS7wlw8o3QwJIwjKKbzGZY=; b=nRVa+F0b8oY6LfsN1CPUs6jwHMqE2JVydJ8LFO1GJ8b7H5mk7714IwdmS6ZSfgtHVe iAb2RNsBrSHrGWt9vk5jzCQAsptDNqqNX7+md+Q9V6jaQuqjBykvFS4zPBUp00LIt6KA SpmyLir+cQ4JcUMZqXwDA4FzBq1PHGixJ3dxzE5lMok+EcPVy7jF2tvALF5nM6Df0pu9 u974RKwQxn4qhiffGjCtNyUcUxoG4wbJ5DkHbS7I7y/VOZfWvvTa2tc4rZKBZTRCYWi7 rMILT2rXsgEZ6kHUy9wFqQIVF4UGn6/2agxK2O3iaSDoCMf8Sn6z8FKrCvwGC0xOYA6U WC9w== X-Gm-Message-State: AOAM531VL8PwwdwCIWxrHERqDLF1CtQt9qVEOhbIpto0E1QInHygAvdk tKT0xLE5Gn+Iuogtv/whsrg= X-Google-Smtp-Source: ABdhPJxoaCVq2/xXwgrZl0Xo9LbuYrYYxbdj0AxfnoyWPBhLztPxCRgWYLKEURCxJ7OLKAPrks+EJQ== X-Received: by 2002:a5d:6b86:0:b0:1e3:2862:d5d9 with SMTP id n6-20020a5d6b86000000b001e32862d5d9mr3936167wrx.493.1645142231416; Thu, 17 Feb 2022 15:57:11 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id r2sm3691694wmq.24.2022.02.17.15.57.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Feb 2022 15:57:11 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 08/16] clk: qcom: gcc-ipq806x: add additional freq nss cores Date: Fri, 18 Feb 2022 00:56:55 +0100 Message-Id: <20220217235703.26641-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220217235703.26641-1-ansuelsmth@gmail.com> References: <20220217235703.26641-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be clocked to 800MHz. Add these missing freq to the gcc driver. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index a4bf78fe8678..53a61860063d 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = { static struct pll_freq_tbl pll18_freq_tbl[] = { NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), + NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625), NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), + NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625), }; static struct clk_pll pll18 = { @@ -2702,7 +2704,9 @@ static const struct freq_tbl clk_tbl_nss[] = { { 110000000, P_PLL18, 1, 1, 5 }, { 275000000, P_PLL18, 2, 0, 0 }, { 550000000, P_PLL18, 1, 0, 0 }, + { 600000000, P_PLL18, 1, 0, 0 }, { 733000000, P_PLL18, 1, 0, 0 }, + { 800000000, P_PLL18, 1, 0, 0 }, { } }; From patchwork Thu Feb 17 23:56:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 543476 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2408C4332F for ; Thu, 17 Feb 2022 23:58:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229793AbiBQX6M (ORCPT ); Thu, 17 Feb 2022 18:58:12 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:56648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229787AbiBQX6E (ORCPT ); Thu, 17 Feb 2022 18:58:04 -0500 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31D8A42EC8; Thu, 17 Feb 2022 15:57:26 -0800 (PST) Received: by mail-wr1-x432.google.com with SMTP id x5so6814292wrg.13; Thu, 17 Feb 2022 15:57:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FZYn4dDcPjXeJZV6gh5sYOUK3nuBBshuULLNYbagtWM=; b=p2fZr2bEOFZ/lxAQQKPqKjiMYkPzb1hgQZy8IGivHanoZ5/5wENheWCpskLXpFxdUi VuWY8j4FWnmGmKq96o25bC0M7Q69mFKLt4JXZnjd3uY16nvwHwloYSkc1oNqL3Fr10UX iqrO8oSL3IjkuIm/AfjVV6D69HWhjsPJiLI6WVeBlqVgQ3IAo9SzG+F7KP+Ynpg17PaH +N1Ledd3PARh4ehvXt4bb2glRfcYI1ibXDFObYLbZpJVn9/Ty8p3T+kBsaUWLkiY7xZb 3Cqkvh90ZjfMHtSjTnD3jVKYGmdPt3N3j+PtRmS/oJvpGO5NP1CXA5WNyYOTJ3vsc/dP TFbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FZYn4dDcPjXeJZV6gh5sYOUK3nuBBshuULLNYbagtWM=; b=rUcvCp33AAMxv3tHPypXvB8hHNEX3EV8pKyT+8L0V+NJ2A2BEAu5FWoZU6y3NPm+DW UhNYUeiEptlZ5QsJAJIEomZ6BrBlByFnXlNKinpd7oi9pp9UL+KJPWljaeu/88JMtmLt w+hkxQ5L2gLIVXu5QpCiy3snMGJTh53OA6D1eg73PaZ8wDYUTqmtn9VxeBw0H4nDG3Dx j2GOGk+vsuZjnyLPnt8GJKb3bPuSI2+YnLBz8IfSSit9fDMgHBB5FCaF9N9R0Fhp1P9/ T7lBd44A1Nbkj0CY1lUzTFBPPz+P/WDR/HUkhpg3r7OHdzTzUnXA3ScmuB2paOsZAXds D7jQ== X-Gm-Message-State: AOAM532Rc61eVGciK95nFkDmhrqgyRniXyg0vB1Rhs83Ra2+GuBLvMLd fLz3pIlcJtNCc/zuUH5FW0o= X-Google-Smtp-Source: ABdhPJwU5YMC2StsQVw15/v4ARdP1QkUCzJvBv66hk2TXNWNy+VkJG+FacLTb2zLCMC/I6/YzEJaEA== X-Received: by 2002:a5d:4e03:0:b0:1e3:3a59:48ae with SMTP id p3-20020a5d4e03000000b001e33a5948aemr3981917wrt.634.1645142232538; Thu, 17 Feb 2022 15:57:12 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id r2sm3691694wmq.24.2022.02.17.15.57.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Feb 2022 15:57:12 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 09/16] clk: qcom: gcc-ipq806x: add unusued flag for critical clock Date: Fri, 18 Feb 2022 00:56:56 +0100 Message-Id: <20220217235703.26641-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220217235703.26641-1-ansuelsmth@gmail.com> References: <20220217235703.26641-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some clocks are used by other devices present on the SoC. For example the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to reject any regulator change command. These clock should never be disabled. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 53a61860063d..77bc3d94f580 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -798,7 +798,7 @@ static struct clk_rcg gsbi4_qup_src = { .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, }, }, }; @@ -816,7 +816,7 @@ static struct clk_branch gsbi4_qup_clk = { }, .num_parents = 1, .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }, }; @@ -900,7 +900,7 @@ static struct clk_rcg gsbi6_qup_src = { .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, }, }, }; @@ -969,7 +969,7 @@ static struct clk_branch gsbi7_qup_clk = { }, .num_parents = 1, .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }, }; @@ -1015,6 +1015,7 @@ static struct clk_branch gsbi4_h_clk = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_h_clk", .ops = &clk_branch_ops, + .flags = CLK_IGNORE_UNUSED, }, }, }; From patchwork Thu Feb 17 23:56:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 543475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 959BEC433FE for ; Thu, 17 Feb 2022 23:58:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229903AbiBQX7B (ORCPT ); Thu, 17 Feb 2022 18:59:01 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:34250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229630AbiBQX7A (ORCPT ); Thu, 17 Feb 2022 18:59:00 -0500 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C64131907; Thu, 17 Feb 2022 15:58:30 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id j9-20020a05600c190900b0037bff8a24ebso7351283wmq.4; Thu, 17 Feb 2022 15:58:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=RF2SupLnblRY3PGRxJOT5rLVt7yv2WyDPqmkS+jmfa4=; b=Y9Dx1di7yXLg8EBhZ5x+IxrKiVc1XivXfid/HaNES5wbitlhCA1POMl7BB1zCw/B9S fw5j2Oc1NcZz6m9Ryp69ciPyKOaN4VBwlVF6P94/jMhknGJ69KGAUsVvKL7VqTdoYGr/ d2HZjv+BmwW+M6RCiMMntSrofRy0UG6XKOPVkyA2Q5a5NsXxe5JUakPXms2v8EH+RoM+ ltzPaqWhFVQ0O775Zi0yFu0jgWTq2uIr5sswHhFap/yIHfTWOZscT5AA8YAICOISj6u+ RA/9O3GUQc8ObriPlUHVXPuAAtVEOhgAJob73vXnZRSVR4eQjK6Cm1XeQCIA/v0f0kkb JJbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RF2SupLnblRY3PGRxJOT5rLVt7yv2WyDPqmkS+jmfa4=; b=mQNjnRUhn9dVF7xodD6PL20O2K+Cm6h8zUL2jQaX4hLAZgtFy+C/OVb8htWX8cTMyf kOTY8yJ0RuLtXytkHn/FJ49YNxq8x0v0ugzGqoFDEddFJXOwZ3Ea5E0l4krFtlXvx6Zi qgUIxlVI60bgf91zjrICD2hmH5x6TZBKMJGA2BhWTriGbcHE7ExtBVyguxPceSAUaENy eHg9eq8DNGmfBtZo1yhyoUb9fkx9KreAVjtYOuy4SQPi4jEVLfRDlkIqR8KwACp+qW8f RoxmDLChHfQNdVp687OzQc/HbTWYYquF13r9mYWd3Bx+jrcZgijHQW8WigrbUW/2eshb RnpQ== X-Gm-Message-State: AOAM530uJyA5QJ8iVmCca86+NSF+6eucN77suI3B9tygUJ8YHjeUurBJ ULbmtK/xN4tsPHp8VGfSR0k= X-Google-Smtp-Source: ABdhPJw/9g43AeaBTkk+EuqymDN/lAV4tsvforF4CCWF5AKAlAefszVtMvjUfRWMU7jYwPTm6Pg3Yw== X-Received: by 2002:a05:600c:4e12:b0:37b:ebf6:3d17 with SMTP id b18-20020a05600c4e1200b0037bebf63d17mr4702866wmq.44.1645142236336; Thu, 17 Feb 2022 15:57:16 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id r2sm3691694wmq.24.2022.02.17.15.57.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Feb 2022 15:57:15 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 12/16] dt-bindings: clock: add ipq8064 ce5 clk define Date: Fri, 18 Feb 2022 00:56:59 +0100 Message-Id: <20220217235703.26641-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220217235703.26641-1-ansuelsmth@gmail.com> References: <20220217235703.26641-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver. Signed-off-by: Ansuel Smith --- include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h index 7deec14a6dee..02262d2ac899 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h @@ -240,7 +240,7 @@ #define PLL14 232 #define PLL14_VOTE 233 #define PLL18 234 -#define CE5_SRC 235 +#define CE5_A_CLK 235 #define CE5_H_CLK 236 #define CE5_CORE_CLK 237 #define CE3_SLEEP_CLK 238 @@ -283,5 +283,8 @@ #define EBI2_AON_CLK 281 #define NSSTCM_CLK_SRC 282 #define NSSTCM_CLK 283 +#define CE5_A_CLK_SRC 285 +#define CE5_H_CLK_SRC 286 +#define CE5_CORE_CLK_SRC 287 #endif From patchwork Thu Feb 17 23:57:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 543474 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1A8CC4332F for ; Thu, 17 Feb 2022 23:59:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229925AbiBQX7j (ORCPT ); Thu, 17 Feb 2022 18:59:39 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:38630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229960AbiBQX7i (ORCPT ); Thu, 17 Feb 2022 18:59:38 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3111622BD7; Thu, 17 Feb 2022 15:59:13 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id f3so11510261wrh.7; Thu, 17 Feb 2022 15:59:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vT22BNhvWNrWcIFz/SRqR6yLshzUpgXQgOLovMBptOU=; b=bM8B6vC/eHIfkdXvjvjzL0Io3HKiXs0BA7aifVkhBrtTk4ngyHOIZvcyuEmvV5LwQm WdSUq34wTE1tqEtkkTraje0lPl/0xUcdLe/MPHjIFT3TOh0mh6qpGRBvKxg3sfSiafcF sS9XjOeXcMgD/UlM3mXU69hTehlbVxtFN2KholoVF331OQ8Kvp4O5RrpQ363kuNOHu6e qiTZD6vXY8pW9GadBxHwCgNNH5/1qO2a+d2jJmJgPg6U1G91vdLgRqGwwpNUjYx1CTWZ WE3xy81vHrKJg3Yq+lH+7f90WCoIQp/WT97uRz2+JhM3fMr9xhtPmYd3T078Mk76szBc +cwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vT22BNhvWNrWcIFz/SRqR6yLshzUpgXQgOLovMBptOU=; b=q/SXee97kJPaH8qqGAwWhbB0Hzw9tnqmpB7Kx+SUP5+r+Zf5h64DS1E8YFgjhgnppC Ztrl0/+gkX4fXoOcFFdBc6wUlplU40M26iPsInfyEXYGUDVQZAKLMveEuAKuV9NXBddP 2m5mlpX/1JTZnKq50DQtAzZcKFO6Ah689x40+ssRZbr0thZkuKWGqRA2lL21bx4/Aw1F kHMucbG6m249LPZbPq3YuJBeHudbDhPtCNccruQAQMs2CQ3nG3I99T15GM5cFXYdcG47 vo6lqLHUrijeUMZN48zXUpjxVpX9VbWfNPfbZNtbX+z+knA6j2Kd6YdnDdvJqDPkUTN3 YHfw== X-Gm-Message-State: AOAM530IkaYPXL7quSIKUam8hAYZqGPRPWBPvAjYFbIvIE/XoaWo7Aro PexeJ6lau7H7FROpy/n49vI= X-Google-Smtp-Source: ABdhPJx0o0QEWI6rJv/9wEUhc/aYF1XXdO7EAOnqwF9+/FebyqXIwWI2GYV49YBmfR5KWqyhwgGkqQ== X-Received: by 2002:a5d:6292:0:b0:1e7:8afb:73ea with SMTP id k18-20020a5d6292000000b001e78afb73eamr3944853wru.149.1645142238476; Thu, 17 Feb 2022 15:57:18 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id r2sm3691694wmq.24.2022.02.17.15.57.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Feb 2022 15:57:18 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 14/16] dt-bindings: reset: add ipq8064 ce5 resets Date: Fri, 18 Feb 2022 00:57:01 +0100 Message-Id: <20220217235703.26641-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220217235703.26641-1-ansuelsmth@gmail.com> References: <20220217235703.26641-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add ipq8064 ce5 resets needed for CryptoEngine gcc driver. Signed-off-by: Ansuel Smith --- include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h index 26b6f9200620..020c9cf18751 100644 --- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h +++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h @@ -163,5 +163,10 @@ #define NSS_CAL_PRBS_RST_N_RESET 154 #define NSS_LCKDT_RST_N_RESET 155 #define NSS_SRDS_N_RESET 156 +#define CRYPTO_ENG1_RESET 157 +#define CRYPTO_ENG2_RESET 158 +#define CRYPTO_ENG3_RESET 159 +#define CRYPTO_ENG4_RESET 160 +#define CRYPTO_AHB_RESET 161 #endif From patchwork Thu Feb 17 23:57:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 543473 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 171B1C4167E for ; Thu, 17 Feb 2022 23:59:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230016AbiBQX7k (ORCPT ); Thu, 17 Feb 2022 18:59:40 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:38658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230006AbiBQX7i (ORCPT ); Thu, 17 Feb 2022 18:59:38 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA8B42E08D; Thu, 17 Feb 2022 15:59:14 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id p9so11627561wra.12; Thu, 17 Feb 2022 15:59:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=g3H8tOvYka3MHkICVbkvjI48HA63lA9VQLbmV9F1OAQ=; b=U0JbSyWgvbgz1wvc6NzKGXiJmcv4W7XaJLMpXGnFCqcW3gONW2tYFhlNGYsiNiGHaS Nvi9Ys6piSsb9FXWh8bsHcef+8YUgE46LiCZtFbr5YgwPFfk6UdQh0mpL47eUf/fDcD6 se1CwyWuQYhAfmBZPdjlzCA7mTIUTbB82iY0hOKUCG0xTQ1nV29oHqBiHRDLrmFUj7H8 qA9lHXeRRGcl04inq3YNABnFwPAU2MEGHzAnZwdQqA7VUGAprgYxzzObGLu0l+iMc2ah wyVEU3I3I+L930zbwkxkX2IfFeeXVnD8H6tZgTml78G/NOQ1+KSHGw0xoJ6cCpeMUPeU eL9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g3H8tOvYka3MHkICVbkvjI48HA63lA9VQLbmV9F1OAQ=; b=YN865eT2axRCX7FWUSf03tEcDr+IhOyQmX2zPIyLWtMqogGZJnsq9vz0LWSNAfHC+y xH2Joczflq/QSUPdQCxOR7h55dltEB59JoGYNWkUZEFe1zTvrwXlnF+g9qcRhA4OpH8n Q3J07VFdCbwCrvFTA+gCFj+ExGYTgs/B1mDfa79LOgeO/hKnU34VaSY65E0rSPrdtYQ9 e82XlaqLYbiCUh989l2J4QfajrGPUozQynuRpm/fnTkT2JMLOT+HqU+T1Cx3IgLBk0DD bR5jyZVZN1jRq6//8AAPX59pPd4nerHbLDfvQiB9VgJ+LrlzbI5S2MOoXeJqrCzjovBC PTlA== X-Gm-Message-State: AOAM533PDh/Fn3E1JEoqbTXlfblrVsi3ztIUBF8NtKzzFOhiKStH+Fz2 svOtwvhzGniH0kXzGz+pmc0= X-Google-Smtp-Source: ABdhPJxUXi9EJni7SmfF9zA5T/CqgubQKgH7dzM0zxTYKfWqAO3WHnIPta90bm7i9bub1UUUL3VEkw== X-Received: by 2002:a5d:518d:0:b0:1e5:8cc9:5aa4 with SMTP id k13-20020a5d518d000000b001e58cc95aa4mr3845871wrv.119.1645142240450; Thu, 17 Feb 2022 15:57:20 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id r2sm3691694wmq.24.2022.02.17.15.57.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Feb 2022 15:57:20 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 16/16] ARM: dts: qcom: Add syscon and cxo/pxo clock to gcc node for ipq8064 Date: Fri, 18 Feb 2022 00:57:03 +0100 Message-Id: <20220217235703.26641-17-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220217235703.26641-1-ansuelsmth@gmail.com> References: <20220217235703.26641-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add syscon compatible required for tsens driver to correctly probe driver and access the reg. Also add cxo and pxo tag and declare them as gcc clock now requires them for the ipq8064 gcc driver that has now been modernized. Signed-off-by: Ansuel Smith --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 11481313bdb6..5524a68cf3d1 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -298,13 +298,13 @@ smem: smem@41000000 { }; clocks { - cxo_board { + cxo_board: cxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; @@ -736,7 +736,9 @@ tsens_calib_backup: calib_backup@410 { }; gcc: clock-controller@900000 { - compatible = "qcom,gcc-ipq8064"; + compatible = "qcom,gcc-ipq8064", "syscon"; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>;