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[209.132.180.67]) by mx.google.com with ESMTP id e2si1670689pgs.94.2018.11.29.03.08.29; Thu, 29 Nov 2018 03:08:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XTxvTWeh; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727248AbeK2WN2 (ORCPT + 15 others); Thu, 29 Nov 2018 17:13:28 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:42100 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726949AbeK2WN2 (ORCPT ); Thu, 29 Nov 2018 17:13:28 -0500 Received: by mail-lj1-f193.google.com with SMTP id l15-v6so1335708lja.9 for ; Thu, 29 Nov 2018 03:08:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=t2b3ZoY3m8QExeDiV8SpS1dFs70/vogCmJbkC7YwYLI=; b=XTxvTWehiof55dKhoIxPHKPTGTeyi0rh0lHKTlghkKPMIqVmtm3CAlfvyKqiOtjasN cdQzuwg30uh1sMmSEZQhUwI7wB51A4gZZCuDERxNLrWthph/udv90KO2+vXhB9RetS7z /q/XvmYu4g3YW7SV9ivLuOiycTmJTrvcYGtPQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=t2b3ZoY3m8QExeDiV8SpS1dFs70/vogCmJbkC7YwYLI=; b=pdIdFkzSf2tL1xtpb+f9BCTGzi7su3CaFFZNJWaXNK7Pk7zGGwPdphsFYkHReLTuqu hfZ5t1ZTlmjVXefoviDxPzYPuWFgnlDxPDhKErzdIwmChlnyEGlJ1Vz/qQBxBRDlrQEN YKA0XPrsO5ieUblNeFjtFQTQYxV4enCSMB97pnr6hAzmabJE90ZBvjx7ZWmTqr2Kltsi IxZuglQcQVhpdBumH2zUZH8n+jnHCzhdh0vAMfGtQFoTMj11bIsPumbupOq22S1eKpcX 7bEASysMyYum8013MMwps7grYRrCBQWzSM9nzbNk13KS0WVYJ1XW9rOk5KLgAT2Dj8YG cr6w== X-Gm-Message-State: AA+aEWbEG3T/+McGmnt5dkR6EkcLdFl2luyMkk3l0OYoapuEnxcsPv13 j8GU5cre7xpEiKPp/Smr3rdMST9K2JxE4w== X-Received: by 2002:a2e:5c86:: with SMTP id q128-v6mr825398ljb.119.1543489706660; Thu, 29 Nov 2018 03:08:26 -0800 (PST) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id z6sm242458lfa.87.2018.11.29.03.08.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 29 Nov 2018 03:08:25 -0800 (PST) From: Linus Walleij To: linux-arm-msm@vger.kernel.org, Andy Gross , David Brown Cc: linux-arm-kernel@lists.infradead.org, Linus Walleij Subject: [PATCH] ARM: dts: msm8660: Fix up GIC IRQ flags Date: Thu, 29 Nov 2018 12:08:21 +0100 Message-Id: <20181129110821.18102-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org All the GSBI blocks are marking their GIC IRQ lines as "IRQ_TYPE_NONE" but there is no such thing: all GIC IRQ lines have a trigger type. That yields the following warning from the GIC driver: WARNING: CPU: 0 PID: 1 at ../drivers/irqchip/irq-gic.c:1016 gic_irq_domain_translate+0xdc/0xe4 (...) Mark all of these IRQ_TYPE_LEVEL_HIGH as is common so this warning goes away. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/qcom-msm8660.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.19.1 diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 9b1cf00d8ca3..e5da87036dbb 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -141,7 +141,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16540000 0x1000>, <0x16500000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -150,7 +150,7 @@ gsbi6_i2c: i2c@16580000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16580000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -176,7 +176,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16640000 0x1000>, <0x16600000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -185,7 +185,7 @@ gsbi7_i2c: i2c@16680000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16680000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -209,7 +209,7 @@ gsbi8_i2c: i2c@19880000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x19880000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -234,7 +234,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; - interrupts = <0 195 IRQ_TYPE_NONE>; + interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -243,7 +243,7 @@ gsbi12_i2c: i2c@19c80000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x19c80000 0x1000>; - interrupts = <0 196 IRQ_TYPE_NONE>; + interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>;