From patchwork Wed Feb 16 00:08:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wesley Cheng X-Patchwork-Id: 544083 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF5C6C433EF for ; Wed, 16 Feb 2022 00:08:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243466AbiBPAJC (ORCPT ); Tue, 15 Feb 2022 19:09:02 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:49958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237850AbiBPAJA (ORCPT ); Tue, 15 Feb 2022 19:09:00 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 877E6A9959; Tue, 15 Feb 2022 16:08:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644970130; x=1676506130; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kGpx79+WUt1lqyewEV2ymHo3cDgsw78Ck4Qr0gknnzk=; b=rdlKHjdsvwsVq11fB+F79q44tCuOj+zln2SEdF+uPB0TYwxGFv4UdYX+ 1Xg+bVJiJVkb8WqQkoKDuke0XJJwZDFssBP74EtP8uHlk3K6BI4ojBrcp Q4HfUpsBNfxqlAjEYiadssGKA5KoYReLgybx0OXUteUq9jkspRwm2pvf7 U=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 15 Feb 2022 16:08:49 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 16:08:49 -0800 Received: from nalasex01b.na.qualcomm.com (10.47.209.197) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Tue, 15 Feb 2022 16:08:48 -0800 Received: from wcheng-linux.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 15 Feb 2022 16:08:48 -0800 From: Wesley Cheng To: , CC: , , , , Wesley Cheng Subject: [RFC PATCH v2 1/3] usb: dwc3: Flush pending SETUP data during stop active xfers Date: Tue, 15 Feb 2022 16:08:33 -0800 Message-ID: <20220216000835.25400-2-quic_wcheng@quicinc.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220216000835.25400-1-quic_wcheng@quicinc.com> References: <20220216000835.25400-1-quic_wcheng@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org While running the pullup disable sequence, if there are pending SETUP transfers stored in the controller, then the ENDTRANSFER commands on non control eps will fail w/ ETIMEDOUT. As a suggestion from SNPS, in order to drain potentially cached SETUP packets, SW needs to issue a STARTTRANSFER command. After issuing the STARTTRANSFER, and retrying the ENDTRANSFER, the command should succeed. Else, if the endpoints are not properly stopped, the controller halt sequence will fail as well. One limitation is that the current logic will drop the SETUP data being received (ie dropping the SETUP packet), however, it should be acceptable in the pullup disable case, as the device is eventually going to disconnect from the host. Signed-off-by: Wesley Cheng --- drivers/usb/dwc3/core.h | 7 +++++++ drivers/usb/dwc3/ep0.c | 20 +++++++++++-------- drivers/usb/dwc3/gadget.c | 42 ++++++++++++++++++++++++++++++++++----- 3 files changed, 56 insertions(+), 13 deletions(-) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index eb9c1efced05..a411682e7f44 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -1551,6 +1551,8 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, u32 param); void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc); +void dwc3_ep0_stall_and_restart(struct dwc3 *dwc); +void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep); #else static inline int dwc3_gadget_init(struct dwc3 *dwc) { return 0; } @@ -1572,6 +1574,11 @@ static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, { return 0; } static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc) { } +static inline void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) +{ } +static inline void dwc3_ep0_end_control_data(struct dwc3 *dwc, + struct dwc3_ep *dep) +{ } #endif #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 658739410992..a2cc94c25dcf 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -197,7 +197,7 @@ int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, int ret; spin_lock_irqsave(&dwc->lock, flags); - if (!dep->endpoint.desc || !dwc->pullups_connected) { + if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) { dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", dep->name); ret = -ESHUTDOWN; @@ -218,19 +218,21 @@ int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, return ret; } -static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) +void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) { struct dwc3_ep *dep; /* reinitialize physical ep1 */ dep = dwc->eps[1]; dep->flags = DWC3_EP_ENABLED; + dep->trb_enqueue = 0; /* stall is always issued on EP0 */ dep = dwc->eps[0]; __dwc3_gadget_ep_set_halt(dep, 1, false); dep->flags = DWC3_EP_ENABLED; dwc->delayed_status = false; + dep->trb_enqueue = 0; if (!list_empty(&dep->pending_list)) { struct dwc3_request *req; @@ -240,7 +242,9 @@ static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) } dwc->ep0state = EP0_SETUP_PHASE; - dwc3_ep0_out_start(dwc); + complete(&dwc->ep0_in_setup); + if (dwc->softconnect) + dwc3_ep0_out_start(dwc); } int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) @@ -272,8 +276,6 @@ void dwc3_ep0_out_start(struct dwc3 *dwc) struct dwc3_ep *dep; int ret; - complete(&dwc->ep0_in_setup); - dep = dwc->eps[0]; dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8, DWC3_TRBCTL_CONTROL_SETUP, false); @@ -922,7 +924,9 @@ static void dwc3_ep0_complete_status(struct dwc3 *dwc, dwc->setup_packet_pending = true; dwc->ep0state = EP0_SETUP_PHASE; - dwc3_ep0_out_start(dwc); + complete(&dwc->ep0_in_setup); + if (dwc->softconnect) + dwc3_ep0_out_start(dwc); } static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, @@ -1073,7 +1077,7 @@ void dwc3_ep0_send_delayed_status(struct dwc3 *dwc) __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); } -static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) +void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) { struct dwc3_gadget_ep_cmd_params params; u32 cmd; @@ -1083,7 +1087,7 @@ static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) return; cmd = DWC3_DEPCMD_ENDTRANSFER; - cmd |= DWC3_DEPCMD_CMDIOC; + cmd |= dwc->connected ? DWC3_DEPCMD_CMDIOC : DWC3_DEPCMD_HIPRI_FORCERM; cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); memset(¶ms, 0, sizeof(params)); ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 183b90923f51..f6801199440c 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -885,12 +885,13 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) reg |= DWC3_DALEPENA_EP(dep->number); dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); - if (usb_endpoint_xfer_control(desc)) - goto out; - /* Initialize the TRB ring */ dep->trb_dequeue = 0; dep->trb_enqueue = 0; + + if (usb_endpoint_xfer_control(desc)) + goto out; + memset(dep->trb_pool, 0, sizeof(struct dwc3_trb) * DWC3_TRB_NUM); @@ -2476,7 +2477,8 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) * Per databook, when we want to stop the gadget, if a control transfer * is still in process, complete it and get the core into setup phase. */ - if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) { + if ((!is_on && (dwc->ep0state != EP0_SETUP_PHASE || + dwc->ep0_next_event != DWC3_EP0_COMPLETE))) { reinit_completion(&dwc->ep0_in_setup); ret = wait_for_completion_timeout(&dwc->ep0_in_setup, @@ -2519,6 +2521,17 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) u32 count; dwc->connected = false; + + /* + * Ensure no pending data/setup stages, and disable ep0 to + * block further EP0 transactions before stopping pending + * transfers. + */ + dwc3_ep0_end_control_data(dwc, dwc->eps[1]); + dwc3_ep0_stall_and_restart(dwc); + __dwc3_gadget_ep_disable(dwc->eps[0]); + __dwc3_gadget_ep_disable(dwc->eps[1]); + /* * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a * Section 4.1.8 Table 4-7, it states that for a device-initiated @@ -3600,8 +3613,10 @@ static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt) { struct dwc3_gadget_ep_cmd_params params; + struct dwc3 *dwc = dep->dwc; u32 cmd; int ret; + int retries = 1; if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) || (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) @@ -3633,7 +3648,7 @@ static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, * * This mode is NOT available on the DWC_usb31 IP. */ - +retry: cmd = DWC3_DEPCMD_ENDTRANSFER; cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0; @@ -3641,6 +3656,23 @@ static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, memset(¶ms, 0, sizeof(params)); ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); WARN_ON_ONCE(ret); + if (ret == -ETIMEDOUT) { + if (!dwc->connected) { + /* + * While the controller is in an active setup/control + * transfer, the HW is unable to service other eps + * potentially leading to an endxfer command timeout. + * It was recommended to ensure that there are no + * pending/cached setup packets stored in internal + * memory. Only way to achieve this is to issue another + * start transfer, and retry. + */ + if (retries--) { + dwc3_ep0_out_start(dwc); + goto retry; + } + } + } dep->resource_index = 0; if (!interrupt) From patchwork Wed Feb 16 00:08:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wesley Cheng X-Patchwork-Id: 544082 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D514CC43217 for ; Wed, 16 Feb 2022 00:08:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244803AbiBPAJE (ORCPT ); Tue, 15 Feb 2022 19:09:04 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:49962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239042AbiBPAJB (ORCPT ); Tue, 15 Feb 2022 19:09:01 -0500 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F1AFAEF1D; Tue, 15 Feb 2022 16:08:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644970130; x=1676506130; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oN4NWytvEcUVUp7v1buldlNzHy56+BuMGRT2tVQLD2A=; b=Ug65FQNKfxecU87bZHf63kB8+Ji0s7Ym9SmgAjTJWF9sMG88UpZSlxJu 95rWGEEAv9lcFz3bNFVcTkLOiCVH+FGE1ySkFpddb1c62/1VEMzN7Cenm FXDit1CRU6GVvI4AL7a0LwAuEOCiYDSLt3q5HDFeCfC/+DWPcJGXr1wKm Y=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 15 Feb 2022 16:08:50 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 16:08:49 -0800 Received: from nalasex01b.na.qualcomm.com (10.47.209.197) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Tue, 15 Feb 2022 16:08:49 -0800 Received: from wcheng-linux.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 15 Feb 2022 16:08:48 -0800 From: Wesley Cheng To: , CC: , , , , Wesley Cheng Subject: [RFC PATCH v2 2/3] usb: dwc3: gadget: Wait for ep0 xfers to complete during dequeue Date: Tue, 15 Feb 2022 16:08:34 -0800 Message-ID: <20220216000835.25400-3-quic_wcheng@quicinc.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220216000835.25400-1-quic_wcheng@quicinc.com> References: <20220216000835.25400-1-quic_wcheng@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org If the request being dequeued is currently active, then the current logic is to issue a stop transfer command, and allow the command completion to cleanup the cancelled list. The DWC3 controller will run into endxfer command timeouts if there is an ongoing EP0 transaction. If this is the case, wait for the EP0 completion event before proceeding to retry the endxfer command again. Signed-off-by: Wesley Cheng --- drivers/usb/dwc3/core.h | 5 +++++ drivers/usb/dwc3/ep0.c | 2 ++ drivers/usb/dwc3/gadget.c | 47 +++++++++++++++++++++++++++++++++------ 3 files changed, 47 insertions(+), 7 deletions(-) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index a411682e7f44..00348d6d479b 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -736,6 +736,7 @@ struct dwc3_ep { #define DWC3_EP_FIRST_STREAM_PRIMED BIT(10) #define DWC3_EP_PENDING_CLEAR_STALL BIT(11) #define DWC3_EP_TXFIFO_RESIZED BIT(12) +#define DWC3_EP_PENDING_DEQUEUE BIT(13) /* This last one is specific to EP0 */ #define DWC3_EP0_DIR_IN BIT(31) @@ -1272,6 +1273,7 @@ struct dwc3 { unsigned delayed_status:1; unsigned ep0_bounced:1; unsigned ep0_expect_in:1; + unsigned ep_dequeue_pending:1; unsigned has_hibernation:1; unsigned sysdev_is_parent:1; unsigned has_lpm_erratum:1; @@ -1553,6 +1555,7 @@ int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc); void dwc3_ep0_stall_and_restart(struct dwc3 *dwc); void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep); +int dwc3_gadget_check_ep_dequeue(struct dwc3 *dwc); #else static inline int dwc3_gadget_init(struct dwc3 *dwc) { return 0; } @@ -1579,6 +1582,8 @@ static inline void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) static inline void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) { } +static inline int dwc3_gadget_check_ep_dequeue(struct dwc3 *dwc) +{ return 0; } #endif #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index a2cc94c25dcf..99202f5a613e 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -243,6 +243,7 @@ void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) dwc->ep0state = EP0_SETUP_PHASE; complete(&dwc->ep0_in_setup); + dwc3_gadget_check_ep_dequeue(dwc); if (dwc->softconnect) dwc3_ep0_out_start(dwc); } @@ -925,6 +926,7 @@ static void dwc3_ep0_complete_status(struct dwc3 *dwc, dwc->ep0state = EP0_SETUP_PHASE; complete(&dwc->ep0_in_setup); + dwc3_gadget_check_ep_dequeue(dwc); if (dwc->softconnect) dwc3_ep0_out_start(dwc); } diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index f6801199440c..0c89baedf220 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -654,7 +654,7 @@ static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action) return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); } -static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, +static int dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt); /** @@ -1081,6 +1081,31 @@ static int dwc3_gadget_ep_enable(struct usb_ep *ep, return ret; } +int dwc3_gadget_check_ep_dequeue(struct dwc3 *dwc) +{ + struct dwc3_ep *dep; + int ret = 0; + int i; + + if (!dwc->ep_dequeue_pending) + return 0; + + for (i = 0; i < dwc->num_eps; i++) { + dep = dwc->eps[i]; + if (dep->flags & DWC3_EP_PENDING_DEQUEUE) { + ret = dwc3_stop_active_transfer(dep, false, true); + if (ret) + goto exit; + + dep->flags &= ~DWC3_EP_PENDING_DEQUEUE; + } + } + + dwc->ep_dequeue_pending = 0; +exit: + return ret; +} + static int dwc3_gadget_ep_disable(struct usb_ep *ep) { struct dwc3_ep *dep; @@ -2033,10 +2058,6 @@ static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, list_for_each_entry(r, &dep->started_list, list) { if (r == req) { struct dwc3_request *t; - - /* wait until it is processed */ - dwc3_stop_active_transfer(dep, true, true); - /* * Remove any started request if the transfer is * cancelled. @@ -2045,6 +2066,12 @@ static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, dwc3_gadget_move_cancelled_request(r, DWC3_REQUEST_STATUS_DEQUEUED); + ret = dwc3_stop_active_transfer(dep, false, true); + if (ret == -ETIMEDOUT) { + dep->flags |= DWC3_EP_PENDING_DEQUEUE; + dwc->ep_dequeue_pending = 1; + } + dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE; goto out; @@ -2319,6 +2346,7 @@ static void dwc3_stop_active_transfers(struct dwc3 *dwc) continue; dwc3_remove_requests(dwc, dep); + dep->flags &= ~DWC3_EP_PENDING_DEQUEUE; } } @@ -2715,6 +2743,7 @@ static int __dwc3_gadget_start(struct dwc3 *dwc) dwc->ep0state = EP0_SETUP_PHASE; dwc->link_state = DWC3_LINK_STATE_SS_DIS; dwc->delayed_status = false; + dwc->ep_dequeue_pending = 0; dwc3_ep0_out_start(dwc); dwc3_gadget_enable_irq(dwc); @@ -3433,6 +3462,7 @@ static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep, if (dep->stream_capable) dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM; + dep->flags &= ~DWC3_EP_PENDING_DEQUEUE; dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; dep->flags &= ~DWC3_EP_TRANSFER_STARTED; dwc3_gadget_ep_cleanup_cancelled_requests(dep); @@ -3609,7 +3639,7 @@ static void dwc3_reset_gadget(struct dwc3 *dwc) } } -static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, +static int dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt) { struct dwc3_gadget_ep_cmd_params params; @@ -3620,7 +3650,7 @@ static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) || (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) - return; + return 0; /* * NOTICE: We are violating what the Databook says about the @@ -3671,6 +3701,8 @@ static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, dwc3_ep0_out_start(dwc); goto retry; } + } else { + return ret; } } dep->resource_index = 0; @@ -3679,6 +3711,7 @@ static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, dep->flags &= ~DWC3_EP_TRANSFER_STARTED; else dep->flags |= DWC3_EP_END_TRANSFER_PENDING; + return ret; } static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) From patchwork Wed Feb 16 00:08:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wesley Cheng X-Patchwork-Id: 543288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6311FC4332F for ; Wed, 16 Feb 2022 00:08:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244792AbiBPAJD (ORCPT ); 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15 Feb 2022 16:08:50 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 16:08:50 -0800 Received: from nalasex01b.na.qualcomm.com (10.47.209.197) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Tue, 15 Feb 2022 16:08:49 -0800 Received: from wcheng-linux.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 15 Feb 2022 16:08:49 -0800 From: Wesley Cheng To: , CC: , , , , Wesley Cheng Subject: [RFC PATCH v2 3/3] usb: dwc3: Issue core soft reset before enabling run/stop Date: Tue, 15 Feb 2022 16:08:35 -0800 Message-ID: <20220216000835.25400-4-quic_wcheng@quicinc.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220216000835.25400-1-quic_wcheng@quicinc.com> References: <20220216000835.25400-1-quic_wcheng@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org It is recommended by the Synopsis databook to issue a DCTL.CSftReset when reconnecting from a device-initiated disconnect routine. This resolves issues with enumeration during fast composition switching cases, which result in an unknown device on the host. Signed-off-by: Wesley Cheng --- drivers/usb/dwc3/core.c | 4 +--- drivers/usb/dwc3/core.h | 2 ++ drivers/usb/dwc3/gadget.c | 11 +++++++++++ 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 18adddfba3da..02d10e1cb774 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -115,8 +115,6 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) dwc->current_dr_role = mode; } -static int dwc3_core_soft_reset(struct dwc3 *dwc); - static void __dwc3_set_mode(struct work_struct *work) { struct dwc3 *dwc = work_to_dwc(work); @@ -261,7 +259,7 @@ u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) * dwc3_core_soft_reset - Issues core soft reset and PHY reset * @dwc: pointer to our context structure */ -static int dwc3_core_soft_reset(struct dwc3 *dwc) +int dwc3_core_soft_reset(struct dwc3 *dwc) { u32 reg; int retries = 1000; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 00348d6d479b..b27ad8dad317 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -1532,6 +1532,8 @@ bool dwc3_has_imod(struct dwc3 *dwc); int dwc3_event_buffers_setup(struct dwc3 *dwc); void dwc3_event_buffers_cleanup(struct dwc3 *dwc); +int dwc3_core_soft_reset(struct dwc3 *dwc); + #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) int dwc3_host_init(struct dwc3 *dwc); void dwc3_host_exit(struct dwc3 *dwc); diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 0c89baedf220..788889f924f9 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -2585,6 +2585,17 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) dwc->ev_buf->length; } } else { + /* + * In the Synopsis DesignWare Cores USB3 Databook Rev. 1.90a + * Section 4.1.9, it specifies that for a reconnect after a + * device-initiated disconnect requires a core soft reset + * (DCTL.CSftRst) before enabling the run/stop bit. + */ + spin_unlock_irqrestore(&dwc->lock, flags); + dwc3_core_soft_reset(dwc); + spin_lock_irqsave(&dwc->lock, flags); + + dwc3_event_buffers_setup(dwc); __dwc3_gadget_start(dwc); }