From patchwork Fri Feb 11 19:12:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 542488 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D313C4332F for ; Fri, 11 Feb 2022 19:12:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344794AbiBKTMs (ORCPT ); Fri, 11 Feb 2022 14:12:48 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:39632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343767AbiBKTMr (ORCPT ); Fri, 11 Feb 2022 14:12:47 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DC85CE7; Fri, 11 Feb 2022 11:12:46 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CCD0E61F35; Fri, 11 Feb 2022 19:12:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3C94BC340E9; Fri, 11 Feb 2022 19:12:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644606765; bh=/kRr5IqKtgAB6PuFxk7QjfVSXaEzJJ5qpIyJSbD3iEA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Wj+9Wb+CZtHszzgJ+ck+1SkW0c4aQ8Pox7l5ywg2DmQlaPfXOUTSKbuMBNIcTXCRo W8KQvmDXlQO7fHSBE9l2XXC1MWvVBjZ4c21RMHWnretX0Q71qtKTQbL7szMxgUMzNQ 4gUYfcwuMiu6LFY/ZGMS529OY9aUnc0FR5Gn7B25FywTlLAkzQzu6Nca6+jt5YUiOZ DER+Sat5I1j9eecxwZL1cu+JHVn9s13aY8tTHZeZ2dXAg9lZwdJCAyi5Vbbyu0o4Kt CemlHDyDk4afLe7Hfn1s6Y+Mmr6B/F3rEQE9HiP19pYeRw53iyUPRqAhw67vofN6aI sV6GCYN9loMew== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Stephen Boyd , Michael Turquette , Greg Kroah-Hartman , Gregory Clement Cc: =?utf-8?q?Pali_Roh=C3=A1r?= , linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v8 1/6] math64: New DIV_U64_ROUND_CLOSEST helper Date: Fri, 11 Feb 2022 20:12:33 +0100 Message-Id: <20220211191238.2142-2-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220211191238.2142-1-kabel@kernel.org> References: <20220211191238.2142-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Pali Rohár Provide DIV_U64_ROUND_CLOSEST helper which uses div_u64 to perform division rounded to the closest integer using unsigned 64bit dividend and unsigned 32bit divisor. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún --- Changes since v7: - added Marek's Reviewed-by tag --- include/linux/math64.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/math64.h b/include/linux/math64.h index 2928f03d6d46..a14f40de1dca 100644 --- a/include/linux/math64.h +++ b/include/linux/math64.h @@ -300,6 +300,19 @@ u64 mul_u64_u64_div_u64(u64 a, u64 mul, u64 div); #define DIV64_U64_ROUND_CLOSEST(dividend, divisor) \ ({ u64 _tmp = (divisor); div64_u64((dividend) + _tmp / 2, _tmp); }) +/* + * DIV_U64_ROUND_CLOSEST - unsigned 64bit divide with 32bit divisor rounded to nearest integer + * @dividend: unsigned 64bit dividend + * @divisor: unsigned 32bit divisor + * + * Divide unsigned 64bit dividend by unsigned 32bit divisor + * and round to closest integer. + * + * Return: dividend / divisor rounded to nearest integer + */ +#define DIV_U64_ROUND_CLOSEST(dividend, divisor) \ + ({ u32 _tmp = (divisor); div_u64((u64)(dividend) + _tmp / 2, _tmp); }) + /* * DIV_S64_ROUND_CLOSEST - signed 64bit divide with 32bit divisor rounded to nearest integer * @dividend: signed 64bit dividend From patchwork Fri Feb 11 19:12:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 542050 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA979C433F5 for ; Fri, 11 Feb 2022 19:12:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345845AbiBKTMy (ORCPT ); Fri, 11 Feb 2022 14:12:54 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:39644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345686AbiBKTMu (ORCPT ); Fri, 11 Feb 2022 14:12:50 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D566238F; Fri, 11 Feb 2022 11:12:48 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 715E561F39; Fri, 11 Feb 2022 19:12:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AAD40C340F2; Fri, 11 Feb 2022 19:12:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644606767; bh=kaArX3mep8T1juUfVoTJSgqg1e77nuBpM1rAZZLiL5Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CGFg1aPBiw7lgHDhG+PiaowWYKoeM663d3ZC/qLhY/OXxHiLBxvuTY/WdqTQDft8L PXtWKCVQVOJ0mee3t/3NtPRN0qgpjhCDOw4nric1R9xjMcZQZX9e2pYxsvme0Fm+FR JxOtbqft01eG3Kli5M28K7xMZ9BBv2kBphPQ997hSpYQFK7w1yAQML2dSZbwydHApR Ymz6s9g/Dldlfsa7HC60qqjCvaJmRxhQF4uHEdDGH+ldD8e8vSfTc58J6uxoC9cAWv ZBWTdyzF05/lXrDzmRLsTJZ5pb6jVOooWIaxT2r68RsE0RLKZvmNmiBNilMurVbu62 uoRHZiCTu/yAg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Stephen Boyd , Michael Turquette , Greg Kroah-Hartman , Gregory Clement Cc: =?utf-8?q?Pali_Roh=C3=A1r?= , linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , =?utf-8?q?Mare?= =?utf-8?q?k_Beh=C3=BAn?= Subject: [PATCH v8 2/6] dt-bindings: mvebu-uart: document DT bindings for marvell,armada-3700-uart-clock Date: Fri, 11 Feb 2022 20:12:34 +0100 Message-Id: <20220211191238.2142-3-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220211191238.2142-1-kabel@kernel.org> References: <20220211191238.2142-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Pali Rohár Add DT bindings documentation for device nodes with compatible string "marvell,armada-3700-uart-clock". Signed-off-by: Pali Rohár Reviewed-by: Rob Herring Reviewed-by: Marek Behún Signed-off-by: Marek Behún --- Changes since v7: - added Reviewed-by tags - changed commit message a little ("This change adds" -> "Add") - fixed lint errors in yaml binding file --- .../clock/marvell,armada-3700-uart-clock.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/marvell,armada-3700-uart-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/marvell,armada-3700-uart-clock.yaml b/Documentation/devicetree/bindings/clock/marvell,armada-3700-uart-clock.yaml new file mode 100644 index 000000000000..175f5c8f2bc5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,armada-3700-uart-clock.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +title: Marvell Armada 3720 UART clocks + +maintainers: + - Pali Rohár + +properties: + compatible: + const: marvell,armada-3700-uart-clock + + reg: + items: + - description: UART Clock Control Register + - description: UART 2 Baud Rate Divisor Register + + clocks: + description: | + List of parent clocks suitable for UART from following set: + "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal" + UART clock can use one from this set and when more are provided + then kernel would choose and configure the most suitable one. + It is suggest to specify at least one TBG clock to achieve + baudrates above 230400 and also to specify clock which bootloader + used for UART (most probably xtal) for smooth boot log on UART. + + clock-names: + items: + - const: TBG-A-P + - const: TBG-B-P + - const: TBG-A-S + - const: TBG-B-S + - const: xtal + minItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + uartclk: clock-controller@12010 { + compatible = "marvell,armada-3700-uart-clock"; + reg = <0x12010 0x4>, <0x12210 0x4>; + clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>, <&xtalclk>; + clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"; + #clock-cells = <1>; + }; From patchwork Fri Feb 11 19:12:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 542487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E70ABC43217 for ; Fri, 11 Feb 2022 19:13:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352669AbiBKTNC (ORCPT ); Fri, 11 Feb 2022 14:13:02 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:39698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348720AbiBKTM5 (ORCPT ); Fri, 11 Feb 2022 14:12:57 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE8C1CEC; Fri, 11 Feb 2022 11:12:55 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 732F3B82C0E; Fri, 11 Feb 2022 19:12:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EA818C340F2; Fri, 11 Feb 2022 19:12:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644606773; bh=z4QJvv5jQOMSoBELgUEfc+t5uAq/ZocWJT4vzhJHC9k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mxR3FEwiw1/IApZN1xx2o1TK2U5T8LLeDp/nMfkHN5Rt7kvQ0Xvy8O+MMaXiDqJ2w aJmZQRzxAgICQrM17BgxiDE1GSDHy3H3ht7MaCXryHOnHF0HzKh7kEm2lHLq4oUFCg 21LxHUB53Uqm/orGNYQD0s5cXZomoIrurhEQZB2eUrfEnCJ6vsNp0b3kvfQ8BYeshb PYJt9QQMOl9ZSlDMSyIwJWvc0pKvPmYDQ1kF7qQH7C3zJhGvTf3zdDN1XiXhV0M7Wy IKNMRtztTz5/7oA6WO09ad3Nv3iawWzzuoHMg9VfF7tdoAhEwhwKcJ1+7TUrKbdrw3 tYF1Fu7dtqFfg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Stephen Boyd , Michael Turquette , Greg Kroah-Hartman , Gregory Clement Cc: =?utf-8?q?Pali_Roh=C3=A1r?= , linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , =?utf-8?q?Mare?= =?utf-8?q?k_Beh=C3=BAn?= Subject: [PATCH v8 4/6] dt-bindings: mvebu-uart: update information about UART clock Date: Fri, 11 Feb 2022 20:12:36 +0100 Message-Id: <20220211191238.2142-5-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220211191238.2142-1-kabel@kernel.org> References: <20220211191238.2142-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Pali Rohár Device "marvell,armada-3700-uart" should use "marvell,armada-3700-uart-clock" compatible clock. Signed-off-by: Pali Rohár Reviewed-by: Rob Herring Reviewed-by: Marek Behún Signed-off-by: Marek Behún --- Changes since v7: - added Reviewed-by tags --- Documentation/devicetree/bindings/serial/mvebu-uart.txt | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/mvebu-uart.txt b/Documentation/devicetree/bindings/serial/mvebu-uart.txt index 2d0dbdf32d1d..a062bbca532c 100644 --- a/Documentation/devicetree/bindings/serial/mvebu-uart.txt +++ b/Documentation/devicetree/bindings/serial/mvebu-uart.txt @@ -14,7 +14,10 @@ Required properties: is provided (possible only with the "marvell,armada-3700-uart" compatible string for backward compatibility), it will only work if the baudrate was initialized by the bootloader and no baudrate - change will then be possible. + change will then be possible. When provided it should be UART1-clk + for standard variant of UART and UART2-clk for extended variant + of UART. TBG clock (with UART TBG divisors d1=d2=1) or xtal clock + should not be used and are supported only for backward compatibility. - interrupts: - Must contain three elements for the standard variant of the IP (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx", @@ -34,7 +37,7 @@ Example: uart0: serial@12000 { compatible = "marvell,armada-3700-uart"; reg = <0x12000 0x18>; - clocks = <&xtalclk>; + clocks = <&uartclk 0>; interrupts = , , @@ -45,7 +48,7 @@ Example: uart1: serial@12200 { compatible = "marvell,armada-3700-uart-ext"; reg = <0x12200 0x30>; - clocks = <&xtalclk>; + clocks = <&uartclk 1>; interrupts = , ; From patchwork Fri Feb 11 19:12:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 542049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78817C433EF for ; Fri, 11 Feb 2022 19:13:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350665AbiBKTNC (ORCPT ); Fri, 11 Feb 2022 14:13:02 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:39708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349908AbiBKTM5 (ORCPT ); Fri, 11 Feb 2022 14:12:57 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92DD9CED; Fri, 11 Feb 2022 11:12:56 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2AC3461F3C; Fri, 11 Feb 2022 19:12:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8EC34C340F1; Fri, 11 Feb 2022 19:12:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644606775; bh=icDAxhIilkMcIBD/iE5/3SiYgSSWiOTuHCkrhxzg/7M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jBzHpQ5pdB0MztPObMedFoQYSkox1wWNSoNrPLoB0nNDR35MVSlsgv+pOSyFpp/IK oM3CSNSjYuenhrlMbUdGwfWp1QC1kkJNnrJdPmUsk8oOPAy+mjMW4pSW3ks6q0sKit NUpq4DZKVxjHKmZdHeqYObqM4XAKvUlUAIYndC1YkKlHgWKzfqtWFSclQWTQXjLLvn oq/DpY3BEyv8vF9lK6ovNagwkYk6rvkT6y9Bbe4if0Bv6PajxQklOvutFvXUUkMw94 J65CVQxFaghRpTsGsgsWH2GoiMyNj6juzzFLTWSl6t34AXFPHItlRiTfL/XWfz2pQr K5QmJmhAycRNQ== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Stephen Boyd , Michael Turquette , Greg Kroah-Hartman , Gregory Clement Cc: =?utf-8?q?Pali_Roh=C3=A1r?= , linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v8 5/6] arm64: dts: marvell: armada-37xx: add device node for UART clock and use it Date: Fri, 11 Feb 2022 20:12:37 +0100 Message-Id: <20220211191238.2142-6-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220211191238.2142-1-kabel@kernel.org> References: <20220211191238.2142-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Pali Rohár Define DT node for UART clock "marvell,armada-3700-uart-clock" and use this UART clock as a base clock for all UART devices. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún Acked-by: Gregory CLEMENT --- Changes since v7: - changed commit message ("This change defines" -> "Define") - added Marek's Reviewed-by tag --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 673f4906eef9..4cf6c8aa0ac2 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -132,10 +132,20 @@ avs: avs@11500 { reg = <0x11500 0x40>; }; + uartclk: clock-controller@12010 { + compatible = "marvell,armada-3700-uart-clock"; + reg = <0x12010 0x4>, <0x12210 0x4>; + clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, + <&tbg 3>, <&xtalclk>; + clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", + "TBG-B-S", "xtal"; + #clock-cells = <1>; + }; + uart0: serial@12000 { compatible = "marvell,armada-3700-uart"; reg = <0x12000 0x18>; - clocks = <&xtalclk>; + clocks = <&uartclk 0>; interrupts = , , @@ -147,7 +157,7 @@ uart0: serial@12000 { uart1: serial@12200 { compatible = "marvell,armada-3700-uart-ext"; reg = <0x12200 0x30>; - clocks = <&xtalclk>; + clocks = <&uartclk 1>; interrupts = , ; From patchwork Fri Feb 11 19:12:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 542048 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F868C433F5 for ; Fri, 11 Feb 2022 19:13:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352752AbiBKTND (ORCPT ); Fri, 11 Feb 2022 14:13:03 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:39742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349940AbiBKTNB (ORCPT ); Fri, 11 Feb 2022 14:13:01 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14051CF0; Fri, 11 Feb 2022 11:12:59 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 98F8461F3C; Fri, 11 Feb 2022 19:12:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 086E8C340E9; Fri, 11 Feb 2022 19:12:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644606778; bh=+AeaotqsM8rM5bOHFOpDOXMyO/XVaJ+vOedzjI39y7Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kEgi6NKeSbfB0okv7KmfDi7SnjYOstpC5RNvMQPPMsPXv03xkosCy08F5z0aiMY5N LpaDMbXLDcM+JJD4deyrCmdZDZQnCLto/jqY4UEeubuWHyVqWictP8/FsfT8xzDHhD G6CdSmZT0DaFDWjCdZhkHLdSAhv1gy5oDYvdzdv7Vk/KMK2XykSLq1JRoX+47i/4W5 8CkvA2Tto4GJzBQPqSa8klzf0VlXv9egGzhUtJypAc7jTw4BS3x9gf3/svZjUbUdP3 rsP0wA/eOl2a9IOKZpezr07l/1GBBWwOo85yktNCsWarLrtcO1lWY1HAELak50o0y2 FLOKdTJhOKDCQ== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Stephen Boyd , Michael Turquette , Greg Kroah-Hartman , Gregory Clement Cc: =?utf-8?q?Pali_Roh=C3=A1r?= , linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v8 6/6] serial: mvebu-uart: implement support for baudrates higher than 230400 Bd Date: Fri, 11 Feb 2022 20:12:38 +0100 Message-Id: <20220211191238.2142-7-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220211191238.2142-1-kabel@kernel.org> References: <20220211191238.2142-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Pali Rohár Implement simple usage of fractional divisor. When main divisor D is too large to represent requested baudrate then use divisor M from the fractional divisor feature. All the M prescalers are set to the same and maximal value 63, so the fractional part of the fractional divisor is not used at all. We also determine upper limit for possible baudrates. Experiments show that UART at baudrate 1500000 Bd with this configuration is stable. So there is no need to implement complicated calculation of fractional coefficients yet. To use this feature with higher baudrates, it is required to use UART clock provided by UART clock driver. Default boot xtal clock is not capable of higher baudrates. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún --- Changes since v7: - change commit message a little - fixed indentation at some places - added Marek's Reviewed-by tag --- drivers/tty/serial/mvebu-uart.c | 83 ++++++++++++++++++++++++++------- 1 file changed, 65 insertions(+), 18 deletions(-) diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c index 56278b29f5f5..97563a2b9f75 100644 --- a/drivers/tty/serial/mvebu-uart.c +++ b/drivers/tty/serial/mvebu-uart.c @@ -99,6 +99,7 @@ #define UART_OSAMP 0x14 #define OSAMP_DEFAULT_DIVISOR 16 #define OSAMP_DIVISORS_MASK 0x3F3F3F3F +#define OSAMP_MAX_DIVISOR 63 #define MVEBU_NR_UARTS 2 @@ -479,18 +480,60 @@ static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud) return -EOPNOTSUPP; /* - * The baudrate is derived from the UART clock thanks to two divisors: - * > D ("baud generator"): can divide the clock from 2 to 2^10 - 1. - * > M ("fractional divisor"): allows a better accuracy for - * baudrates higher than 230400. + * The baudrate is derived from the UART clock thanks to divisors: + * > d1 * d2 ("TBG divisors"): can divide only TBG clock from 1 to 6 + * > D ("baud generator"): can divide the clock from 1 to 1023 + * > M ("fractional divisor"): allows a better accuracy (from 1 to 63) * - * As the derivation of M is rather complicated, the code sticks to its - * default value (x16) when all the prescalers are zeroed, and only - * makes use of D to configure the desired baudrate. + * Exact formulas for calculating baudrate: + * + * with default x16 scheme: + * baudrate = xtal / (d * 16) + * baudrate = tbg / (d1 * d2 * d * 16) + * + * with fractional divisor: + * baudrate = 10 * xtal / (d * (3 * (m1 + m2) + 2 * (m3 + m4))) + * baudrate = 10 * tbg / (d1*d2 * d * (3 * (m1 + m2) + 2 * (m3 + m4))) + * + * Oversampling value: + * osamp = (m1 << 0) | (m2 << 8) | (m3 << 16) | (m4 << 24); + * + * Where m1 controls number of clock cycles per bit for bits 1,2,3; + * m2 for bits 4,5,6; m3 for bits 7,8 and m4 for bits 9,10. + * + * To simplify baudrate setup set all the M prescalers to the same + * value. For baudrates 9600 Bd and higher, it is enough to use the + * default (x16) divisor or fractional divisor with M = 63, so there + * is no need to use real fractional support (where the M prescalers + * are not equal). + * + * When all the M prescalers are zeroed then default (x16) divisor is + * used. Default x16 scheme is more stable than M (fractional divisor), + * so use M only when D divisor is not enough to derive baudrate. + * + * Member port->uartclk is either xtal clock rate or TBG clock rate + * divided by (d1 * d2). So d1 and d2 are already set by the UART clock + * driver (and UART driver itself cannot change them). Moreover they are + * shared between both UARTs. */ + m_divisor = OSAMP_DEFAULT_DIVISOR; d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); + if (d_divisor > BRDV_BAUD_MAX) { + /* + * Experiments show that small M divisors are unstable. + * Use maximal possible M = 63 and calculate D divisor. + */ + m_divisor = OSAMP_MAX_DIVISOR; + d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); + } + + if (d_divisor < 1) + d_divisor = 1; + else if (d_divisor > BRDV_BAUD_MAX) + d_divisor = BRDV_BAUD_MAX; + spin_lock_irqsave(&mvebu_uart_lock, flags); brdv = readl(port->membase + UART_BRDV); brdv &= ~BRDV_BAUD_MASK; @@ -500,6 +543,9 @@ static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud) osamp = readl(port->membase + UART_OSAMP); osamp &= ~OSAMP_DIVISORS_MASK; + if (m_divisor != OSAMP_DEFAULT_DIVISOR) + osamp |= (m_divisor << 0) | (m_divisor << 8) | + (m_divisor << 16) | (m_divisor << 24); writel(osamp, port->membase + UART_OSAMP); return 0; @@ -529,14 +575,16 @@ static void mvebu_uart_set_termios(struct uart_port *port, port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR; /* - * Maximal divisor is 1023 * 16 when using default (x16) scheme. - * Maximum achievable frequency with simple baudrate divisor is 230400. - * Since the error per bit frame would be of more than 15%, achieving - * higher frequencies would require to implement the fractional divisor - * feature. + * Maximal divisor is 1023 and maximal fractional divisor is 63. And + * experiments show that baudrates above 1/80 of parent clock rate are + * not stable. So disallow baudrates above 1/80 of the parent clock + * rate. If port->uartclk is not available, then + * mvebu_uart_baud_rate_set() fails, so values min_baud and max_baud + * in this case do not matter. */ - min_baud = DIV_ROUND_UP(port->uartclk, 1023 * 16); - max_baud = 230400; + min_baud = DIV_ROUND_UP(port->uartclk, BRDV_BAUD_MAX * + OSAMP_MAX_DIVISOR); + max_baud = port->uartclk / 80; baud = uart_get_baud_rate(port, termios, old, min_baud, max_baud); if (mvebu_uart_baud_rate_set(port, baud)) { @@ -1395,14 +1443,14 @@ static int mvebu_uart_clock_probe(struct platform_device *pdev) * Calculate the smallest TBG d1 and d2 divisors that * still can provide 9600 baudrate. */ - d1 = DIV_ROUND_UP(rate, 9600 * OSAMP_DEFAULT_DIVISOR * + d1 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR * BRDV_BAUD_MAX); if (d1 < 1) d1 = 1; else if (d1 > CLK_TBG_DIV1_MAX) d1 = CLK_TBG_DIV1_MAX; - d2 = DIV_ROUND_UP(rate, 9600 * OSAMP_DEFAULT_DIVISOR * + d2 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR * BRDV_BAUD_MAX * d1); if (d2 < 1) d2 = 1; @@ -1417,8 +1465,7 @@ static int mvebu_uart_clock_probe(struct platform_device *pdev) } /* Skip clock source which cannot provide 9600 baudrate */ - if (rate > 9600 * OSAMP_DEFAULT_DIVISOR * BRDV_BAUD_MAX * d1 * - d2) + if (rate > 9600 * OSAMP_MAX_DIVISOR * BRDV_BAUD_MAX * d1 * d2) continue; /*