From patchwork Fri Feb 11 21:19:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 542195 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01D26C4321E for ; Fri, 11 Feb 2022 21:20:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347305AbiBKVUY (ORCPT ); Fri, 11 Feb 2022 16:20:24 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:44466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349869AbiBKVUW (ORCPT ); Fri, 11 Feb 2022 16:20:22 -0500 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C76CC5D for ; Fri, 11 Feb 2022 13:20:19 -0800 (PST) Received: by mail-wr1-x42d.google.com with SMTP id k1so17248264wrd.8 for ; Fri, 11 Feb 2022 13:20:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sPk+buWgOsn3No8mnO4TlKeJmHvV821o0sf5g8wQD4g=; b=TJrDJRAuHHmM8qIgNnKQznHj6LG+MtpUZ6Wb/PSfK72doeJPRunNCA4hGOj3OfpAC8 1cGsEAXRmWeP2m97YGbWol2TKZ/vjeYflrWXKpjtYUGvuPiM2NR841eueMBkg4B1fjdk qWv/WtXxvrDM2mZPAgA+JgmF8yI7peCrFbc6FZc8WDp7E9bzPnMc7pcgjQT16FbWBNPS W5xvhcbSK1xOIl6r84asFJMxfdbI/AaK8hKopUcjUTNG86syxnwzG4UnCtnRilzjVkTd eaNPqld/PbdtKKGnMRtr8livRQoFVYm+Ou1MVwdyPXPqEEBAPcBKEqJT/yIVBy110AuU zUbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sPk+buWgOsn3No8mnO4TlKeJmHvV821o0sf5g8wQD4g=; b=pV/6r3OeGGkcyeE9BSKWx9IP4QcPfPHV+N2H7pbtvqcSm9EQ30aApbv0COgmrGmcG9 IoJuxrZ3ThoicKH4i46rWCIv8aKxrKdAogwy6+LaOVcK6qgz4lbrCOC4s2pjg9uLU4LC axg3bLu2XHDuEBJ/py8nRlmT1pYZl7rsVWd0O+BUQExolxqUhClfzfeKS08tfVq9ejyG e/Axc1Ce2C8IdHcVUTYio0/kDvAuFqgNsppZQo25ydsC4CxdG00o6XiKj10saavZrV3R hV/ZWGEaBKwuxddZmnfxcTW0eMVgSLNBRUYWGAHzdyaun5QvpEJNVJuxHWnigWXd1zpp Gz9A== X-Gm-Message-State: AOAM533BDEKfBv1+0txhyFxUzcLFSmo/WGNaVsB6YvuAgXNuZNzhCJn4 MdE/3wEJhn9Z1TbRTI/ecOYHVg== X-Google-Smtp-Source: ABdhPJyrWC9a2u6hNyiBuni7arFvrCsIIq+OnLl44DZGkVl0vsCqBO9pc1N4rSEjpDZzqszYA+FKdA== X-Received: by 2002:a05:6000:2c2:: with SMTP id o2mr2786757wry.30.1644614417562; Fri, 11 Feb 2022 13:20:17 -0800 (PST) Received: from localhost.localdomain (cpc78119-cwma10-2-0-cust590.7-3.cable.virginm.net. [81.96.50.79]) by smtp.gmail.com with ESMTPSA id x5sm14276017wrv.63.2022.02.11.13.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Feb 2022 13:20:17 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v4 1/8] mfd: qcom-spmi-pmic: expose the PMIC revid information to clients Date: Fri, 11 Feb 2022 21:19:52 +0000 Message-Id: <20220211211959.502514-2-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220211211959.502514-1-caleb.connolly@linaro.org> References: <20220211211959.502514-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some PMIC functions such as the RRADC need to be aware of the PMIC chip revision information to implement errata or otherwise adjust behaviour, export the PMIC information to enable this. This is specifically required to enable the RRADC to adjust coefficients based on which chip fab the PMIC was produced in, this can vary per unique device and therefore has to be read at runtime. Signed-off-by: Caleb Connolly --- drivers/mfd/qcom-spmi-pmic.c | 152 +++++++++++++++++++----------- include/soc/qcom/qcom-spmi-pmic.h | 60 ++++++++++++ 2 files changed, 155 insertions(+), 57 deletions(-) create mode 100644 include/soc/qcom/qcom-spmi-pmic.h diff --git a/drivers/mfd/qcom-spmi-pmic.c b/drivers/mfd/qcom-spmi-pmic.c index 1cacc00aa6c9..4af88b8bb7d0 100644 --- a/drivers/mfd/qcom-spmi-pmic.c +++ b/drivers/mfd/qcom-spmi-pmic.c @@ -3,51 +3,24 @@ * Copyright (c) 2014, The Linux Foundation. All rights reserved. */ +#include +#include #include #include +#include +#include #include #include #include +#include #define PMIC_REV2 0x101 #define PMIC_REV3 0x102 #define PMIC_REV4 0x103 #define PMIC_TYPE 0x104 #define PMIC_SUBTYPE 0x105 - #define PMIC_TYPE_VALUE 0x51 -#define COMMON_SUBTYPE 0x00 -#define PM8941_SUBTYPE 0x01 -#define PM8841_SUBTYPE 0x02 -#define PM8019_SUBTYPE 0x03 -#define PM8226_SUBTYPE 0x04 -#define PM8110_SUBTYPE 0x05 -#define PMA8084_SUBTYPE 0x06 -#define PMI8962_SUBTYPE 0x07 -#define PMD9635_SUBTYPE 0x08 -#define PM8994_SUBTYPE 0x09 -#define PMI8994_SUBTYPE 0x0a -#define PM8916_SUBTYPE 0x0b -#define PM8004_SUBTYPE 0x0c -#define PM8909_SUBTYPE 0x0d -#define PM8028_SUBTYPE 0x0e -#define PM8901_SUBTYPE 0x0f -#define PM8950_SUBTYPE 0x10 -#define PMI8950_SUBTYPE 0x11 -#define PM8998_SUBTYPE 0x14 -#define PMI8998_SUBTYPE 0x15 -#define PM8005_SUBTYPE 0x18 -#define PM660L_SUBTYPE 0x1A -#define PM660_SUBTYPE 0x1B -#define PM8150_SUBTYPE 0x1E -#define PM8150L_SUBTYPE 0x1f -#define PM8150B_SUBTYPE 0x20 -#define PMK8002_SUBTYPE 0x21 -#define PM8009_SUBTYPE 0x24 -#define PM8150C_SUBTYPE 0x26 -#define SMB2351_SUBTYPE 0x29 - static const struct of_device_id pmic_spmi_id_table[] = { { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE }, { .compatible = "qcom,pm660l", .data = (void *)PM660L_SUBTYPE }, @@ -81,42 +54,96 @@ static const struct of_device_id pmic_spmi_id_table[] = { { } }; -static void pmic_spmi_show_revid(struct regmap *map, struct device *dev) +/** + * @brief Get a pointer to the PMIC device + * + * @param dev the pmic function device + * @return const struct qcom_spmi_pmic* + * + * Ref counting is not needed as references will + * only be held by drivers below the pmic, they will + * always unregister before the pmic does. + */ +const struct qcom_spmi_pmic *qcom_pmic_get(struct device *dev) +{ + struct spmi_device *sdev; + struct device_node *other_usid; + struct platform_device *pdev; + int function_parent_usid; + + if (!of_match_device(pmic_spmi_id_table, dev->parent)) + return ERR_PTR(-EINVAL); + + sdev = to_spmi_device(dev->parent); + if (!sdev) + return ERR_PTR(-EINVAL); + + if (sdev->usid % 2 == 0) + return spmi_device_get_drvdata(sdev); + + function_parent_usid = sdev->usid; + + /* + * Walk through the list of PMICs until we find the sibling usid + * That is either 1 greater or 1 less than the current usid. + * The goal is the find to previous sibling. + */ + other_usid = of_get_next_child(sdev->dev.of_node, NULL); + do { + pdev = of_find_device_by_node(other_usid); + sdev = to_spmi_device(&pdev->dev); + + if (sdev->usid % 2 == 0 && function_parent_usid - sdev->usid == 1) + return spmi_device_get_drvdata(sdev); + + other_usid = of_get_next_child(sdev->dev.parent->of_node, other_usid); + } while (sdev->usid % 2 != 0 && other_usid); + + return ERR_PTR(-ENODATA); +} +EXPORT_SYMBOL(qcom_pmic_get); + +static inline void pmic_print_info(struct device *dev, struct qcom_spmi_pmic *pmic) +{ + dev_info(dev, "%x: %s v%d.%d\n", + pmic->subtype, pmic->name, pmic->major, pmic->minor); +} + +static int pmic_spmi_load_revid(struct regmap *map, struct device *dev, + struct qcom_spmi_pmic *pmic) { - unsigned int rev2, minor, major, type, subtype; - const char *name = "unknown"; int ret, i; - ret = regmap_read(map, PMIC_TYPE, &type); + ret = regmap_read(map, PMIC_TYPE, &pmic->type); if (ret < 0) - return; + return ret; - if (type != PMIC_TYPE_VALUE) - return; + if (pmic->type != PMIC_TYPE_VALUE) + return ret; - ret = regmap_read(map, PMIC_SUBTYPE, &subtype); + ret = regmap_read(map, PMIC_SUBTYPE, &pmic->subtype); if (ret < 0) - return; + return ret; for (i = 0; i < ARRAY_SIZE(pmic_spmi_id_table); i++) { - if (subtype == (unsigned long)pmic_spmi_id_table[i].data) + if (pmic->subtype == (unsigned long)pmic_spmi_id_table[i].data) break; } if (i != ARRAY_SIZE(pmic_spmi_id_table)) - name = pmic_spmi_id_table[i].compatible; + pmic->name = devm_kstrdup_const(dev, pmic_spmi_id_table[i].compatible, GFP_KERNEL); - ret = regmap_read(map, PMIC_REV2, &rev2); + ret = regmap_read(map, PMIC_REV2, &pmic->rev2); if (ret < 0) - return; + return ret; - ret = regmap_read(map, PMIC_REV3, &minor); + ret = regmap_read(map, PMIC_REV3, &pmic->minor); if (ret < 0) - return; + return ret; - ret = regmap_read(map, PMIC_REV4, &major); + ret = regmap_read(map, PMIC_REV4, &pmic->major); if (ret < 0) - return; + return ret; /* * In early versions of PM8941 and PM8226, the major revision number @@ -124,14 +151,14 @@ static void pmic_spmi_show_revid(struct regmap *map, struct device *dev) * Increment the major revision number here if the chip is an early * version of PM8941 or PM8226. */ - if ((subtype == PM8941_SUBTYPE || subtype == PM8226_SUBTYPE) && - major < 0x02) - major++; + if ((pmic->subtype == PM8941_SUBTYPE || pmic->subtype == PM8226_SUBTYPE) && + pmic->major < 0x02) + pmic->major++; - if (subtype == PM8110_SUBTYPE) - minor = rev2; + if (pmic->subtype == PM8110_SUBTYPE) + pmic->minor = pmic->rev2; - dev_dbg(dev, "%x: %s v%d.%d\n", subtype, name, major, minor); + return 0; } static const struct regmap_config spmi_regmap_config = { @@ -144,14 +171,25 @@ static const struct regmap_config spmi_regmap_config = { static int pmic_spmi_probe(struct spmi_device *sdev) { struct regmap *regmap; + struct qcom_spmi_pmic *pmic; + int ret; regmap = devm_regmap_init_spmi_ext(sdev, &spmi_regmap_config); if (IS_ERR(regmap)) return PTR_ERR(regmap); + pmic = devm_kzalloc(&sdev->dev, sizeof(*pmic), GFP_KERNEL); + if (!pmic) + return -ENOMEM; + /* Only the first slave id for a PMIC contains this information */ - if (sdev->usid % 2 == 0) - pmic_spmi_show_revid(regmap, &sdev->dev); + if (sdev->usid % 2 == 0) { + ret = pmic_spmi_load_revid(regmap, &sdev->dev, pmic); + if (ret < 0) + return ret; + spmi_device_set_drvdata(sdev, pmic); + pmic_print_info(&sdev->dev, pmic); + } return devm_of_platform_populate(&sdev->dev); } diff --git a/include/soc/qcom/qcom-spmi-pmic.h b/include/soc/qcom/qcom-spmi-pmic.h new file mode 100644 index 000000000000..a8a77be22cfc --- /dev/null +++ b/include/soc/qcom/qcom-spmi-pmic.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2021 Linaro. All rights reserved. + * Copyright (c) 2021 Caleb Connolly + */ + +#ifndef __QCOM_PMIC_H__ +#define __QCOM_PMIC_H__ + +#define COMMON_SUBTYPE 0x00 +#define PM8941_SUBTYPE 0x01 +#define PM8841_SUBTYPE 0x02 +#define PM8019_SUBTYPE 0x03 +#define PM8226_SUBTYPE 0x04 +#define PM8110_SUBTYPE 0x05 +#define PMA8084_SUBTYPE 0x06 +#define PMI8962_SUBTYPE 0x07 +#define PMD9635_SUBTYPE 0x08 +#define PM8994_SUBTYPE 0x09 +#define PMI8994_SUBTYPE 0x0a +#define PM8916_SUBTYPE 0x0b +#define PM8004_SUBTYPE 0x0c +#define PM8909_SUBTYPE 0x0d +#define PM8028_SUBTYPE 0x0e +#define PM8901_SUBTYPE 0x0f +#define PM8950_SUBTYPE 0x10 +#define PMI8950_SUBTYPE 0x11 +#define PM8998_SUBTYPE 0x14 +#define PMI8998_SUBTYPE 0x15 +#define PM8005_SUBTYPE 0x18 +#define PM660L_SUBTYPE 0x1A +#define PM660_SUBTYPE 0x1B +#define PM8150_SUBTYPE 0x1E +#define PM8150L_SUBTYPE 0x1f +#define PM8150B_SUBTYPE 0x20 +#define PMK8002_SUBTYPE 0x21 +#define PM8009_SUBTYPE 0x24 +#define PM8150C_SUBTYPE 0x26 +#define SMB2351_SUBTYPE 0x29 + +#define PMI8998_FAB_ID_SMIC 0x11 +#define PMI8998_FAB_ID_GF 0x30 + +#define PM660_FAB_ID_GF 0x0 +#define PM660_FAB_ID_TSMC 0x2 +#define PM660_FAB_ID_MX 0x3 + +struct qcom_spmi_pmic { + unsigned int type; + unsigned int subtype; + unsigned int major; + unsigned int minor; + unsigned int rev2; + const char *name; +}; + +struct device; + +const struct qcom_spmi_pmic *qcom_pmic_get(struct device *dev); + +#endif /* __QCOM_PMIC_H__ */ From patchwork Fri Feb 11 21:19:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 541879 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B3D5C433EF for ; Fri, 11 Feb 2022 21:20:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353542AbiBKVUX (ORCPT ); Fri, 11 Feb 2022 16:20:23 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:44468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347305AbiBKVUW (ORCPT ); Fri, 11 Feb 2022 16:20:22 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A519C58 for ; Fri, 11 Feb 2022 13:20:20 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id q7so17162334wrc.13 for ; Fri, 11 Feb 2022 13:20:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ydVzqquU4q/bWYrhn+94me4Lj3peddSiUdmbeVAiITc=; b=eSsxeZ4orkbspSt5KyAoqc7J1G/ZVd50cU0CRQdOoyaUDUM2GyOsV5HrStc2X/sJiR reAHMUR+YEcXzGhuvA+YZtNBiI81wN7pJclpVCoZP+yB/13or87sp6PsYyAcFW8bEo5D ajsz5GOvDmg5hcIjS6cV3YqMaVrACl/tyCibGHXUTxBFWYUjXcRFmGRwpUMMJ7sMRf6J p4YsJ/3wbDI7VEdSQF1lPVVWbQKo7kv5gZyNku/H4yJGgWrkzIzhYJ7fjcPGbCkhk9lV 5arye/KpxpBVL5j339xJyzXFKBtc4D7IGqnNaqRLzXdkDmfznNFPEng0uT/5SGiDC0ZB Ut/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ydVzqquU4q/bWYrhn+94me4Lj3peddSiUdmbeVAiITc=; b=VdI0l1dhYm8Ers3/99F6qs3ZzhJWiX/lx8ZWd/xmrGG7nI2LfTx33zIEK7DN4RD6HU or3zwKQC9whSOgrXtVB6pGBkh+pSqx6EEIjC7Qaw1chRRaYCN3Fi0FImPRvPNuXUuxvM SgTYE6DuEbamjLLN4BxkwQw0BFM4X+eWfYm4GvbZ/BgvF7Z1ZQ4hM74RAHiPO7US6ol3 Kwy120O+oowbOAVOOVv832k25/KRYjzQhoaVHpvKE07pk0ImqbSHmbrIyZnPHgrq0MPC Cltn6CL6bEjrDuxhMXH3mkhVaXIroPVoX5UAGUuqY109r9ChPnED4X4by+Cdm9FMfv21 Qa+g== X-Gm-Message-State: AOAM532BXVAd7uWua3wEBHJhAOMps4VWqjdeZh+Pr+GJxr2vqtzLtaCq O08oONUjipMlgEDbyqgDKN4z+g== X-Google-Smtp-Source: ABdhPJzhZEYpbYwKubpWDwBWiROzAN94i5PS0Q4CpmndFnMgR0mcybs5TbwKfi0KKdJUUO/HtNQVZw== X-Received: by 2002:a05:6000:1861:: with SMTP id d1mr2775461wri.92.1644614418738; Fri, 11 Feb 2022 13:20:18 -0800 (PST) Received: from localhost.localdomain (cpc78119-cwma10-2-0-cust590.7-3.cable.virginm.net. [81.96.50.79]) by smtp.gmail.com with ESMTPSA id x5sm14276017wrv.63.2022.02.11.13.20.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Feb 2022 13:20:18 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v4 2/8] mfd: qcom-spmi-pmic: read fab id on supported PMICs Date: Fri, 11 Feb 2022 21:19:53 +0000 Message-Id: <20220211211959.502514-3-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220211211959.502514-1-caleb.connolly@linaro.org> References: <20220211211959.502514-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The PMI8998 and PM660 expose the fab_id, this is needed by drivers like the RRADC to calibrate ADC values. Signed-off-by: Caleb Connolly --- drivers/mfd/qcom-spmi-pmic.c | 7 +++++++ include/soc/qcom/qcom-spmi-pmic.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/mfd/qcom-spmi-pmic.c b/drivers/mfd/qcom-spmi-pmic.c index 4af88b8bb7d0..c77b4c82559e 100644 --- a/drivers/mfd/qcom-spmi-pmic.c +++ b/drivers/mfd/qcom-spmi-pmic.c @@ -19,6 +19,7 @@ #define PMIC_REV4 0x103 #define PMIC_TYPE 0x104 #define PMIC_SUBTYPE 0x105 +#define PMIC_FAB_ID 0x1f2 #define PMIC_TYPE_VALUE 0x51 static const struct of_device_id pmic_spmi_id_table[] = { @@ -145,6 +146,12 @@ static int pmic_spmi_load_revid(struct regmap *map, struct device *dev, if (ret < 0) return ret; + if (pmic->subtype == PMI8998_SUBTYPE || pmic->subtype == PM660_SUBTYPE) { + ret = regmap_read(map, PMIC_FAB_ID, &pmic->fab_id); + if (ret < 0) + return ret; + } + /* * In early versions of PM8941 and PM8226, the major revision number * started incrementing from 0 (eg 0 = v1.0, 1 = v2.0). diff --git a/include/soc/qcom/qcom-spmi-pmic.h b/include/soc/qcom/qcom-spmi-pmic.h index a8a77be22cfc..c821f6c6c8a8 100644 --- a/include/soc/qcom/qcom-spmi-pmic.h +++ b/include/soc/qcom/qcom-spmi-pmic.h @@ -50,6 +50,7 @@ struct qcom_spmi_pmic { unsigned int major; unsigned int minor; unsigned int rev2; + unsigned int fab_id; const char *name; }; From patchwork Fri Feb 11 21:19:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 541878 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21EACC433F5 for ; Fri, 11 Feb 2022 21:20:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343753AbiBKVUY (ORCPT ); Fri, 11 Feb 2022 16:20:24 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:44498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353173AbiBKVUX (ORCPT ); Fri, 11 Feb 2022 16:20:23 -0500 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B37EC5C for ; Fri, 11 Feb 2022 13:20:21 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id az26-20020a05600c601a00b0037c078db59cso2632102wmb.4 for ; Fri, 11 Feb 2022 13:20:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BXhDDcjJdPDbZfpGFJmQRsA5lMP0BnPrEwgZzVXptZc=; b=E7AMSUvwtUB2Ul1EJMd0nBqLS8YlEKGzgAhZ2r+5hsVmb38DHWw113iqnrGSgremJA PljpHRQdKRZRDUWNbqPq8R663G+7jupXGPLJz7SY4W1/vqMVGSOK+k3jyVD5MUaIJHic Pd6acQk46RmUBRN6pcXoVzQGVmGSdYEGJpg3siCoNTxiUZeAa2cctzQNT8tylI0Imfjl 9gHr+cHUmyNWhjOBA8ujO5PoZLtN3/TVHeyurIsJvB7Ku9fK74kPvOkNpmGR+AAg+JE7 2iMT0RsZSxwD0B9cA3F62Hbb2IDQORQ05z4GfrHClnJZc/4KxQr0y0dLjxVwupHqfVmH QYww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BXhDDcjJdPDbZfpGFJmQRsA5lMP0BnPrEwgZzVXptZc=; b=xnhNcz50qVSPilR+POOxAksZ3y/nPxihj8Np3IepdZX4u0xJExO4KRynOnhVZFSGmk TJxaOVmU48qJxfERaVdtXsO1Kb245P0WLvEA675aUaxzCcl88USftcbxnFGw1kb4c6Ny uaKVvUmr4MNQ3rL8edvU5cbQ9bCtBZJkTmCDx9yYs1N/75yRTJz4MdqlAloD24tnKnDE 7zH0gBPyRE1xEOmfhPS7jzrUlU+QThrf6ecJMtN+d4oNhmmkY0629OeRUHDQi7Fj0FgE b9Ce0XYy6oaCSqZUI8KsE/gZ96xx00pO9NivbtYEU1RP7A93oBXc5Ezj1n83Hg+Z8UwU sMvw== X-Gm-Message-State: AOAM533X5fd6vearsW2iQ82LJHe6Bqtdy7Pknejo0zA45fBo7j+bAsjP OcOxott6lbncTjjLX++Ve5+5yQ== X-Google-Smtp-Source: ABdhPJxFtczxqzZSasyWl6Efyuq/Lsq4Dj9LUh4RHYrT5mfp4m6j2c/6HjXjX17HJP6Nrx8qMZaMiQ== X-Received: by 2002:a05:600c:1d92:: with SMTP id p18mr1779690wms.93.1644614419749; Fri, 11 Feb 2022 13:20:19 -0800 (PST) Received: from localhost.localdomain (cpc78119-cwma10-2-0-cust590.7-3.cable.virginm.net. [81.96.50.79]) by smtp.gmail.com with ESMTPSA id x5sm14276017wrv.63.2022.02.11.13.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Feb 2022 13:20:19 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org, Rob Herring Subject: [PATCH v4 3/8] dt-bindings: iio: adc: document qcom-spmi-rradc Date: Fri, 11 Feb 2022 21:19:54 +0000 Message-Id: <20220211211959.502514-4-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220211211959.502514-1-caleb.connolly@linaro.org> References: <20220211211959.502514-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add dt-binding docs for the Qualcomm SPMI RRADC found in PMICs like PMI8998 and PMI8994 Signed-off-by: Caleb Connolly Reviewed-by: Rob Herring --- .../bindings/iio/adc/qcom,spmi-rradc.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml new file mode 100644 index 000000000000..11d47c46a48d --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-rradc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC Round Robin ADC + +maintainers: + - Caleb Connolly + +description: | + The Qualcomm SPMI Round Robin ADC (RRADC) provides interface to clients to read the + voltage, current and temperature for supported peripherals such as the battery thermistor + die temperature, charger temperature, USB and DC input voltage / current and battery ID + resistor. + +properties: + compatible: + enum: + - qcom,pmi8998-rradc + - qcom,pm660-rradc + + reg: + description: rradc base address and length in the SPMI PMIC register map + maxItems: 1 + + qcom,batt-id-delay-ms: + description: + Sets the hardware settling time for the battery ID resistor. + enum: [0, 1, 4, 12, 20, 40, 60, 80] + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pmic { + #address-cells = <1>; + #size-cells = <0>; + + pmic_rradc: adc@4500 { + compatible = "qcom,pmi8998-rradc"; + reg = <0x4500>; + #io-channel-cells = <1>; + }; + }; +... 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[81.96.50.79]) by smtp.gmail.com with ESMTPSA id x5sm14276017wrv.63.2022.02.11.13.20.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Feb 2022 13:20:20 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v4 4/8] iio: adc: qcom-spmi-rradc: introduce round robin adc Date: Fri, 11 Feb 2022 21:19:55 +0000 Message-Id: <20220211211959.502514-5-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220211211959.502514-1-caleb.connolly@linaro.org> References: <20220211211959.502514-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Round Robin ADC is responsible for reading data about the rate of charge from the USB or DC input ports, it can also read the battery ID (resistence), skin temperature and the die temperature of the pmic. It is found on the PMI8998 and PM660 Qualcomm PMICs. Signed-off-by: Caleb Connolly --- drivers/iio/adc/Kconfig | 13 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/qcom-spmi-rradc.c | 1014 +++++++++++++++++++++++++++++ 3 files changed, 1028 insertions(+) create mode 100644 drivers/iio/adc/qcom-spmi-rradc.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 4fdc8bfbb407..21fdf9d58552 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -812,6 +812,19 @@ config QCOM_PM8XXX_XOADC To compile this driver as a module, choose M here: the module will be called qcom-pm8xxx-xoadc. +config QCOM_SPMI_RRADC + tristate "Qualcomm SPMI RRADC" + depends on MFD_SPMI_PMIC + help + This is for the PMIC Round Robin ADC driver. + + This driver exposes the battery ID resistor, battery thermal, PMIC die + temperature, charger USB in and DC in voltage and current. + + To compile this driver as a module, choose M here: the module will + be called qcom-qpmi-rradc. + + config QCOM_SPMI_IADC tristate "Qualcomm SPMI PMIC current ADC" depends on SPMI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 4a8f1833993b..b0dd7f142abd 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -77,6 +77,7 @@ obj-$(CONFIG_NPCM_ADC) += npcm_adc.o obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o +obj-$(CONFIG_QCOM_SPMI_RRADC) += qcom-spmi-rradc.o obj-$(CONFIG_QCOM_VADC_COMMON) += qcom-vadc-common.o obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o obj-$(CONFIG_QCOM_PM8XXX_XOADC) += qcom-pm8xxx-xoadc.o diff --git a/drivers/iio/adc/qcom-spmi-rradc.c b/drivers/iio/adc/qcom-spmi-rradc.c new file mode 100644 index 000000000000..27195edbbcb4 --- /dev/null +++ b/drivers/iio/adc/qcom-spmi-rradc.c @@ -0,0 +1,1014 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Linaro Limited. + * Author: Caleb Connolly + * + * This driver is for the Round Robin ADC found in the pmi8998 and pm660 PMICs. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RR_ADC_EN_CTL 0x46 +#define RR_ADC_SKIN_TEMP_LSB 0x50 +#define RR_ADC_SKIN_TEMP_MSB 0x51 +#define RR_ADC_CTL 0x52 +#define RR_ADC_CTL_CONTINUOUS_SEL BIT(3) +#define RR_ADC_LOG 0x53 +#define RR_ADC_LOG_CLR_CTRL BIT(0) + +#define RR_ADC_FAKE_BATT_LOW_LSB 0x58 +#define RR_ADC_FAKE_BATT_LOW_MSB 0x59 +#define RR_ADC_FAKE_BATT_HIGH_LSB 0x5A +#define RR_ADC_FAKE_BATT_HIGH_MSB 0x5B + +#define RR_ADC_BATT_ID_CTRL 0x60 +#define RR_ADC_BATT_ID_CTRL_CHANNEL_CONV BIT(0) +#define RR_ADC_BATT_ID_TRIGGER 0x61 +#define RR_ADC_BATT_ID_STS 0x62 +#define RR_ADC_BATT_ID_CFG 0x63 +#define BATT_ID_SETTLE_MASK GENMASK(7, 5) +#define RR_ADC_BATT_ID_5_LSB 0x66 +#define RR_ADC_BATT_ID_5_MSB 0x67 +#define RR_ADC_BATT_ID_15_LSB 0x68 +#define RR_ADC_BATT_ID_15_MSB 0x69 +#define RR_ADC_BATT_ID_150_LSB 0x6A +#define RR_ADC_BATT_ID_150_MSB 0x6B + +#define RR_ADC_BATT_THERM_CTRL 0x70 +#define RR_ADC_BATT_THERM_TRIGGER 0x71 +#define RR_ADC_BATT_THERM_STS 0x72 +#define RR_ADC_BATT_THERM_CFG 0x73 +#define RR_ADC_BATT_THERM_LSB 0x74 +#define RR_ADC_BATT_THERM_MSB 0x75 +#define RR_ADC_BATT_THERM_FREQ 0x76 + +#define RR_ADC_AUX_THERM_CTRL 0x80 +#define RR_ADC_AUX_THERM_TRIGGER 0x81 +#define RR_ADC_AUX_THERM_STS 0x82 +#define RR_ADC_AUX_THERM_CFG 0x83 +#define RR_ADC_AUX_THERM_LSB 0x84 +#define RR_ADC_AUX_THERM_MSB 0x85 + +#define RR_ADC_SKIN_HOT 0x86 +#define RR_ADC_SKIN_TOO_HOT 0x87 + +#define RR_ADC_AUX_THERM_C1 0x88 +#define RR_ADC_AUX_THERM_C2 0x89 +#define RR_ADC_AUX_THERM_C3 0x8A +#define RR_ADC_AUX_THERM_HALF_RANGE 0x8B + +#define RR_ADC_USB_IN_V_CTRL 0x90 +#define RR_ADC_USB_IN_V_TRIGGER 0x91 +#define RR_ADC_USB_IN_V_STS 0x92 +#define RR_ADC_USB_IN_V_LSB 0x94 +#define RR_ADC_USB_IN_V_MSB 0x95 +#define RR_ADC_USB_IN_I_CTRL 0x98 +#define RR_ADC_USB_IN_I_TRIGGER 0x99 +#define RR_ADC_USB_IN_I_STS 0x9A +#define RR_ADC_USB_IN_I_LSB 0x9C +#define RR_ADC_USB_IN_I_MSB 0x9D + +#define RR_ADC_DC_IN_V_CTRL 0xA0 +#define RR_ADC_DC_IN_V_TRIGGER 0xA1 +#define RR_ADC_DC_IN_V_STS 0xA2 +#define RR_ADC_DC_IN_V_LSB 0xA4 +#define RR_ADC_DC_IN_V_MSB 0xA5 +#define RR_ADC_DC_IN_I_CTRL 0xA8 +#define RR_ADC_DC_IN_I_TRIGGER 0xA9 +#define RR_ADC_DC_IN_I_STS 0xAA +#define RR_ADC_DC_IN_I_LSB 0xAC +#define RR_ADC_DC_IN_I_MSB 0xAD + +#define RR_ADC_PMI_DIE_TEMP_CTRL 0xB0 +#define RR_ADC_PMI_DIE_TEMP_TRIGGER 0xB1 +#define RR_ADC_PMI_DIE_TEMP_STS 0xB2 +#define RR_ADC_PMI_DIE_TEMP_CFG 0xB3 +#define RR_ADC_PMI_DIE_TEMP_LSB 0xB4 +#define RR_ADC_PMI_DIE_TEMP_MSB 0xB5 + +#define RR_ADC_CHARGER_TEMP_CTRL 0xB8 +#define RR_ADC_CHARGER_TEMP_TRIGGER 0xB9 +#define RR_ADC_CHARGER_TEMP_STS 0xBA +#define RR_ADC_CHARGER_TEMP_CFG 0xBB +#define RR_ADC_CHARGER_TEMP_LSB 0xBC +#define RR_ADC_CHARGER_TEMP_MSB 0xBD +#define RR_ADC_CHARGER_HOT 0xBE +#define RR_ADC_CHARGER_TOO_HOT 0xBF + +#define RR_ADC_GPIO_CTRL 0xC0 +#define RR_ADC_GPIO_TRIGGER 0xC1 +#define RR_ADC_GPIO_STS 0xC2 +#define RR_ADC_GPIO_LSB 0xC4 +#define RR_ADC_GPIO_MSB 0xC5 + +#define RR_ADC_ATEST_CTRL 0xC8 +#define RR_ADC_ATEST_TRIGGER 0xC9 +#define RR_ADC_ATEST_STS 0xCA +#define RR_ADC_ATEST_LSB 0xCC +#define RR_ADC_ATEST_MSB 0xCD +#define RR_ADC_SEC_ACCESS 0xD0 + +#define RR_ADC_PERPH_RESET_CTL2 0xD9 +#define RR_ADC_PERPH_RESET_CTL3 0xDA +#define RR_ADC_PERPH_RESET_CTL4 0xDB +#define RR_ADC_INT_TEST1 0xE0 +#define RR_ADC_INT_TEST_VAL 0xE1 + +#define RR_ADC_TM_TRIGGER_CTRLS 0xE2 +#define RR_ADC_TM_ADC_CTRLS 0xE3 +#define RR_ADC_TM_CNL_CTRL 0xE4 +#define RR_ADC_TM_BATT_ID_CTRL 0xE5 +#define RR_ADC_TM_THERM_CTRL 0xE6 +#define RR_ADC_TM_CONV_STS 0xE7 +#define RR_ADC_TM_ADC_READ_LSB 0xE8 +#define RR_ADC_TM_ADC_READ_MSB 0xE9 +#define RR_ADC_TM_ATEST_MUX_1 0xEA +#define RR_ADC_TM_ATEST_MUX_2 0xEB +#define RR_ADC_TM_REFERENCES 0xED +#define RR_ADC_TM_MISC_CTL 0xEE +#define RR_ADC_TM_RR_CTRL 0xEF + +#define RR_ADC_TRIGGER_EVERY_CYCLE BIT(7) +#define RR_ADC_TRIGGER_CTL BIT(0) + +#define RR_ADC_BATT_ID_RANGE 820 + +#define RR_ADC_BITS 10 +#define RR_ADC_CHAN_MSB (1 << RR_ADC_BITS) +#define RR_ADC_FS_VOLTAGE_MV 2500 + +/* BATT_THERM 0.25K/LSB */ +#define RR_ADC_BATT_THERM_LSB_K 4 + +#define RR_ADC_TEMP_FS_VOLTAGE_NUM 5000000 +#define RR_ADC_TEMP_FS_VOLTAGE_DEN 3 +#define RR_ADC_DIE_TEMP_OFFSET 601400 +#define RR_ADC_DIE_TEMP_SLOPE 2 +#define RR_ADC_DIE_TEMP_OFFSET_MILLI_DEGC 25000 + +#define RR_ADC_CHG_TEMP_GF_OFFSET_UV 1303168 +#define RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C 3784 +#define RR_ADC_CHG_TEMP_SMIC_OFFSET_UV 1338433 +#define RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C 3655 +#define RR_ADC_CHG_TEMP_660_GF_OFFSET_UV 1309001 +#define RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C 3403 +#define RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV 1295898 +#define RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C 3596 +#define RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV 1314779 +#define RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C 3496 +#define RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC 25000 +#define RR_ADC_CHG_THRESHOLD_SCALE 4 + +#define RR_ADC_VOLT_INPUT_FACTOR 8 +#define RR_ADC_CURR_INPUT_FACTOR 2000 +#define RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL 1886 +#define RR_ADC_CURR_USBIN_660_FACTOR_MIL 9 +#define RR_ADC_CURR_USBIN_660_UV_VAL 579500 + +#define RR_ADC_GPIO_FS_RANGE 5000 +#define RR_ADC_COHERENT_CHECK_RETRY 5 +#define RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN 16 + +#define RR_ADC_STS_CHANNEL_READING_MASK 0x3 +#define RR_ADC_STS_CHANNEL_STS 0x2 + +#define RR_ADC_TP_REV_VERSION1 21 +#define RR_ADC_TP_REV_VERSION2 29 +#define RR_ADC_TP_REV_VERSION3 32 + +#define RRADC_BATT_ID_DELAY_MAX 8 + +enum rradc_channel_id { + RR_ADC_BATT_ID = 0, + RR_ADC_BATT_THERM, + RR_ADC_SKIN_TEMP, + RR_ADC_USBIN_I, + RR_ADC_USBIN_V, + RR_ADC_DCIN_I, + RR_ADC_DCIN_V, + RR_ADC_DIE_TEMP, + RR_ADC_CHG_TEMP, + RR_ADC_GPIO, + RR_ADC_CHAN_MAX +}; + +struct rradc_chip; + +/** + * struct rradc_channel - rradc channel data + * @lsb: Channel least significant byte + * @status: Channel status address + * @size: number of bytes to read + * @trigger_addr: Trigger address, trigger is only used on some channels + * @trigger_mask: Trigger mask + * @scale_fn: Post process callback for channels which can't be exposed + * as offset + scale. + */ +struct rradc_channel { + const char *label; + u8 lsb; + u8 status; + int size; + int trigger_addr; + int trigger_mask; + int (*scale_fn)(struct rradc_chip *chip, u16 adc_code, int *result); +}; + +struct rradc_chip { + struct device *dev; + const struct qcom_spmi_pmic *pmic; + /* Lock held while accessing the rradc registers */ + struct mutex conversion_lock; + struct regmap *regmap; + u32 base; + int batt_id_delay; + u16 batt_id_data; +}; + +static const int batt_id_delays[] = { 0, 1, 4, 12, 20, 40, 60, 80 }; +static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX]; +static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX]; + +static int rradc_read(struct rradc_chip *chip, u16 addr, u8 *data, int len) +{ + int ret, retry_cnt = 0; + u8 data_check[RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN]; + + if (len > RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN) { + dev_err(chip->dev, + "Can't read more than %d bytes, but asked to read %d bytes.\n", + RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN, len); + return -EINVAL; + } + + while (retry_cnt < RR_ADC_COHERENT_CHECK_RETRY) { + ret = regmap_bulk_read(chip->regmap, chip->base + addr, data, + len); + if (ret < 0) { + dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr, + ret); + return ret; + } + + ret = regmap_bulk_read(chip->regmap, chip->base + addr, + data_check, len); + if (ret < 0) { + dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr, + ret); + return ret; + } + + if (memcmp(data, data_check, len) != 0) { + retry_cnt++; + dev_dbg(chip->dev, + "coherent read error, retry_cnt:%d\n", + retry_cnt); + continue; + } + + break; + } + + if (retry_cnt == RR_ADC_COHERENT_CHECK_RETRY) + dev_err(chip->dev, "Retry exceeded for coherrency check\n"); + + return ret; +} + +static int rradc_get_fab_coeff(struct rradc_chip *chip, int64_t *offset, + int64_t *slope) +{ + if (chip->pmic->subtype == PM660_SUBTYPE) { + switch (chip->pmic->fab_id) { + case PM660_FAB_ID_GF: + *offset = RR_ADC_CHG_TEMP_660_GF_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C; + break; + case PM660_FAB_ID_TSMC: + *offset = RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C; + break; + default: + *offset = RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C; + } + } else if (chip->pmic->subtype == PMI8998_SUBTYPE) { + switch (chip->pmic->fab_id) { + case PMI8998_FAB_ID_GF: + *offset = RR_ADC_CHG_TEMP_GF_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C; + break; + case PMI8998_FAB_ID_SMIC: + *offset = RR_ADC_CHG_TEMP_SMIC_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C; + break; + default: + return -EINVAL; + } + } else { + return -EINVAL; + } + + return 0; +} + +/* + * These functions explicitly cast int64_t to int. + * They will never overflow, as the values are small enough. + */ +static int rradc_post_process_batt_id(struct rradc_chip *chip, u16 adc_code, + int *result_ohms) +{ + uint32_t current_value; + int64_t r_id; + + current_value = chip->batt_id_data; + r_id = ((int64_t)adc_code * RR_ADC_FS_VOLTAGE_MV); + r_id = div64_s64(r_id, (RR_ADC_CHAN_MSB * current_value)); + *result_ohms = (int)(r_id * MILLI); + + return 0; +} + +static int rradc_enable_continuous_mode(struct rradc_chip *chip) +{ + int ret; + + /* Clear channel log */ + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG, + RR_ADC_LOG_CLR_CTRL, RR_ADC_LOG_CLR_CTRL); + if (ret < 0) { + dev_err(chip->dev, "log ctrl update to clear failed:%d\n", ret); + return ret; + } + + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG, + RR_ADC_LOG_CLR_CTRL, 0); + if (ret < 0) { + dev_err(chip->dev, "log ctrl update to not clear failed:%d\n", + ret); + return ret; + } + + /* Switch to continuous mode */ + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL, + RR_ADC_CTL_CONTINUOUS_SEL, + RR_ADC_CTL_CONTINUOUS_SEL); + if (ret < 0) + dev_err(chip->dev, "Update to continuous mode failed:%d\n", + ret); + + return ret; +} + +static int rradc_disable_continuous_mode(struct rradc_chip *chip) +{ + int ret; + + /* Switch to non continuous mode */ + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL, + RR_ADC_CTL_CONTINUOUS_SEL, 0); + if (ret < 0) + dev_err(chip->dev, "Update to non-continuous mode failed:%d\n", + ret); + + return ret; +} + +static bool rradc_is_ready(struct rradc_chip *chip, + enum rradc_channel_id chan_id) +{ + const struct rradc_channel *chan = &rradc_chans[chan_id]; + int ret; + unsigned int status, mask; + + /* BATT_ID STS bit does not get set initially */ + switch (chan_id) { + case RR_ADC_BATT_ID: + mask = RR_ADC_STS_CHANNEL_STS; + break; + default: + mask = RR_ADC_STS_CHANNEL_READING_MASK; + break; + } + + ret = regmap_read(chip->regmap, chip->base + chan->status, &status); + if (ret < 0 || !(status & mask)) + return false; + + return true; +} + +static int rradc_read_status_in_cont_mode(struct rradc_chip *chip, + enum rradc_channel_id chan_id) +{ + const struct rradc_channel *chan = &rradc_chans[chan_id]; + const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_id]; + int ret, i; + + if (chan->trigger_mask == 0) { + dev_err(chip->dev, "Channel doesn't have a trigger mask\n"); + return -EINVAL; + } + + ret = regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr, + chan->trigger_mask, chan->trigger_mask); + if (ret < 0) { + dev_err(chip->dev, + "Failed to apply trigger for channel '%s' ret=%d\n", + iio_chan->extend_name, ret); + return ret; + } + + ret = rradc_enable_continuous_mode(chip); + if (ret < 0) { + dev_err(chip->dev, "Failed to switch to continuous mode\n"); + goto disable_trigger; + } + + /* + * The wait/sleep values were found through trial and error, + * this is mostly for the battery ID channel which takes some + * time to settle. + */ + for (i = 0; i < 5; i++) { + if (rradc_is_ready(chip, chan_id)) + break; + usleep_range(50000, 50000 + 500); + } + + if (i == 5) { + dev_err(chip->dev, "Channel '%s' is not ready\n", + iio_chan->extend_name); + ret = -EINVAL; + } + + rradc_disable_continuous_mode(chip); + +disable_trigger: + regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr, + chan->trigger_mask, 0); + + return ret; +} + +static int rradc_prepare_batt_id_conversion(struct rradc_chip *chip, + enum rradc_channel_id chan_id, + u16 *data) +{ + int ret, batt_id_delay; + + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV); + if (ret < 0) { + dev_err(chip->dev, "Enabling BATT ID channel failed:%d\n", ret); + return ret; + } + + if (chip->batt_id_delay != -EINVAL) { + batt_id_delay = + FIELD_PREP(BATT_ID_SETTLE_MASK, chip->batt_id_delay); + ret = regmap_update_bits(chip->regmap, + chip->base + RR_ADC_BATT_ID_CFG, + batt_id_delay, batt_id_delay); + if (ret < 0) { + dev_err(chip->dev, + "BATT_ID settling time config failed:%d\n", + ret); + goto out_disable_batt_id; + } + } + + ret = regmap_update_bits(chip->regmap, + chip->base + RR_ADC_BATT_ID_TRIGGER, + RR_ADC_TRIGGER_CTL, RR_ADC_TRIGGER_CTL); + if (ret < 0) { + dev_err(chip->dev, "BATT_ID trigger set failed:%d\n", ret); + goto out_disable_batt_id; + } + + ret = rradc_read_status_in_cont_mode(chip, chan_id); + + /* + * Reset registers back to default values + */ + regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_TRIGGER, + RR_ADC_TRIGGER_CTL, 0); + +out_disable_batt_id: + regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, 0); + + return ret; +} + +static int rradc_do_conversion(struct rradc_chip *chip, + enum rradc_channel_id chan_id, u16 *data) +{ + const struct rradc_channel *chan = &rradc_chans[chan_id]; + const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_id]; + int ret; + u8 buf[6]; + + mutex_lock(&chip->conversion_lock); + + switch (chan_id) { + case RR_ADC_BATT_ID: + ret = rradc_prepare_batt_id_conversion(chip, chan_id, data); + if (ret < 0) { + dev_err(chip->dev, "Battery ID conversion failed:%d\n", + ret); + goto unlock_out; + } + break; + + case RR_ADC_USBIN_V: + case RR_ADC_DIE_TEMP: + ret = rradc_read_status_in_cont_mode(chip, chan_id); + if (ret < 0) { + dev_err(chip->dev, + "Error reading in continuous mode:%d\n", ret); + goto unlock_out; + } + break; + default: + if (!rradc_is_ready(chip, chan_id)) { + /* + * Usually this means the channel isn't attached, for example + * the in_voltage_usbin_v_input channel will not be ready if + * no USB cable is attached + */ + dev_dbg(chip->dev, "channel '%s' is not ready\n", + iio_chan->extend_name); + ret = -ENODATA; + goto unlock_out; + } + break; + } + + ret = rradc_read(chip, chan->lsb, buf, chan->size); + if (ret) { + dev_err(chip->dev, "read data failed\n"); + goto unlock_out; + } + + /* + * For the battery ID we read the register for every ID ADC and then + * see which one is actually connected. + */ + if (chan_id == RR_ADC_BATT_ID) { + u16 batt_id_150 = get_unaligned_le16(buf + 4); + u16 batt_id_15 = get_unaligned_le16(buf + 2); + u16 batt_id_5 = get_unaligned_le16(buf); + + if (!batt_id_150 && !batt_id_15 && !batt_id_5) { + dev_err(chip->dev, + "Invalid batt_id values with all zeros\n"); + ret = -EINVAL; + goto unlock_out; + } + + if (batt_id_150 <= RR_ADC_BATT_ID_RANGE) { + *data = batt_id_150; + chip->batt_id_data = 150; + } else if (batt_id_15 <= RR_ADC_BATT_ID_RANGE) { + *data = batt_id_15; + chip->batt_id_data = 15; + } else { + *data = batt_id_5; + chip->batt_id_data = 5; + } + } else { + /* + * All of the other channels are either 1 or 2 bytes. + * We can rely on the second byte being 0 for 1-byte channels. + */ + *data = get_unaligned_le16(buf); + } + +unlock_out: + mutex_unlock(&chip->conversion_lock); + + return ret; +} + +static int rradc_read_scale(struct rradc_chip *chip, int chan_id, int *val, + int *val2) +{ + int64_t fab_offset, fab_slope; + int ret; + + ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope); + if (ret < 0) { + dev_err(chip->dev, "Unable to get fab id coefficients\n"); + return -EINVAL; + } + + switch (chan_id) { + case RR_ADC_SKIN_TEMP: + *val = MILLI / RR_ADC_BATT_THERM_LSB_K; + return IIO_VAL_INT; + case RR_ADC_USBIN_I: + *val = RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL * + RR_ADC_FS_VOLTAGE_MV; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_DCIN_I: + *val = RR_ADC_CURR_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_USBIN_V: + case RR_ADC_DCIN_V: + *val = RR_ADC_VOLT_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV * MILLI; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_GPIO: + *val = RR_ADC_GPIO_FS_RANGE; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_CHG_TEMP: + *val = -RR_ADC_TEMP_FS_VOLTAGE_NUM; + *val2 = div64_s64(RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + fab_slope, + MILLI); + + return IIO_VAL_FRACTIONAL; + case RR_ADC_DIE_TEMP: + *val = RR_ADC_TEMP_FS_VOLTAGE_NUM; + *val2 = RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + RR_ADC_DIE_TEMP_SLOPE; + + return IIO_VAL_FRACTIONAL; + default: + break; + } + + return -EINVAL; +} + +static int rradc_read_offset(struct rradc_chip *chip, int chan_id, int *val) +{ + int64_t fab_offset, fab_slope; + int64_t offset1, offset2; + int ret; + + switch (chan_id) { + case RR_ADC_SKIN_TEMP: + /* + * Offset from kelvin to degC, divided by the + * scale factor (250). We lose some precision here. + * 273150 / 250 = 1092.6 + */ + *val = div64_s64(ABSOLUTE_ZERO_MILLICELSIUS, + (MILLI / RR_ADC_BATT_THERM_LSB_K)); + return IIO_VAL_INT; + case RR_ADC_CHG_TEMP: + ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope); + if (ret < 0) { + dev_err(chip->dev, + "Unable to get fab id coefficients\n"); + return -EINVAL; + } + offset1 = -(fab_offset * RR_ADC_TEMP_FS_VOLTAGE_DEN * + RR_ADC_CHAN_MSB); + offset1 += (int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM / (int64_t)2; + offset1 = div64_s64(offset1, + (int64_t)(RR_ADC_TEMP_FS_VOLTAGE_NUM)); + + offset2 = (int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC * + RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + (int64_t)fab_slope; + offset2 += ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM) / 2; + offset2 = div64_s64( + offset2, ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM)); + + /* + * The -1 is to compensate for lost precision. + * It should actually be -0.7906976744186046. + * This works out to every value being off + * by about +91 after applying offset and scale. + */ + *val = (int)(offset1 - offset2 - 1); + return IIO_VAL_INT; + case RR_ADC_DIE_TEMP: + offset1 = -RR_ADC_DIE_TEMP_OFFSET * + (int64_t)RR_ADC_TEMP_FS_VOLTAGE_DEN * + (int64_t)RR_ADC_CHAN_MSB; + offset1 = div64_s64(offset1, RR_ADC_TEMP_FS_VOLTAGE_NUM); + + offset2 = -(int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC * + RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + RR_ADC_DIE_TEMP_SLOPE; + offset2 = div64_s64(offset2, + ((int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM)); + + /* + * The result is -339, it should be + * -338.69789, this results in the calculated + * die temp being off by -0.004 - -0.0175 + */ + *val = (int)(offset1 - offset2); + return IIO_VAL_INT; + default: + break; + } + return -EINVAL; +} + +static int rradc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan_spec, int *val, + int *val2, long mask) +{ + struct rradc_chip *chip = iio_priv(indio_dev); + const struct rradc_channel *chan; + int ret; + u16 adc_code; + + if (chan_spec->channel >= RR_ADC_CHAN_MAX) { + dev_err(chip->dev, "Invalid channel index:%d\n", + chan_spec->channel); + return -EINVAL; + } + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return rradc_read_scale(chip, chan_spec->channel, val, val2); + case IIO_CHAN_INFO_OFFSET: + return rradc_read_offset(chip, chan_spec->channel, val); + default: + break; + } + + chan = &rradc_chans[chan_spec->channel]; + ret = rradc_do_conversion(chip, chan_spec->channel, &adc_code); + if (ret < 0) + return ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + *val = adc_code; + return IIO_VAL_INT; + case IIO_CHAN_INFO_PROCESSED: + if (chan->scale_fn) + chan->scale_fn(chip, adc_code, val); + else + return -EINVAL; + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int rradc_read_label(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, char *label) +{ + return snprintf(label, PAGE_SIZE, "%s\n", + rradc_chans[chan->channel].label); +} + +static const struct iio_info rradc_info = { + .read_raw = rradc_read_raw, + .read_label = rradc_read_label, +}; + +static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX] = { + { + .label = "batt_id", + .scale_fn = rradc_post_process_batt_id, + .lsb = RR_ADC_BATT_ID_5_LSB, + .status = RR_ADC_BATT_ID_STS, + .size = 6, + .trigger_addr = RR_ADC_BATT_ID_TRIGGER, + .trigger_mask = BIT(0), + }, + { + .label = "batt", + .lsb = RR_ADC_BATT_THERM_LSB, + .status = RR_ADC_BATT_THERM_STS, + .size = 2, + .trigger_addr = RR_ADC_BATT_THERM_TRIGGER, + }, + { + .label = "pmi8998_skin", + .lsb = RR_ADC_SKIN_TEMP_LSB, + .status = RR_ADC_AUX_THERM_STS, + .size = 2, + .trigger_addr = RR_ADC_AUX_THERM_TRIGGER, + }, + { + .label = "usbin_i", + .lsb = RR_ADC_USB_IN_I_LSB, + .status = RR_ADC_USB_IN_I_STS, + .size = 2, + .trigger_addr = RR_ADC_USB_IN_I_TRIGGER, + }, + { + .label = "usbin_v", + .lsb = RR_ADC_USB_IN_V_LSB, + .status = RR_ADC_USB_IN_V_STS, + .size = 2, + .trigger_addr = RR_ADC_USB_IN_V_TRIGGER, + .trigger_mask = BIT(7), + }, + { + .label = "dcin_i", + .lsb = RR_ADC_DC_IN_I_LSB, + .status = RR_ADC_DC_IN_I_STS, + .size = 2, + .trigger_addr = RR_ADC_DC_IN_I_TRIGGER, + }, + { + .label = "dcin_v", + .lsb = RR_ADC_DC_IN_V_LSB, + .status = RR_ADC_DC_IN_V_STS, + .size = 2, + .trigger_addr = RR_ADC_DC_IN_V_TRIGGER, + }, + { + .label = "pmi8998_die", + .lsb = RR_ADC_PMI_DIE_TEMP_LSB, + .status = RR_ADC_PMI_DIE_TEMP_STS, + .size = 2, + .trigger_addr = RR_ADC_PMI_DIE_TEMP_TRIGGER, + .trigger_mask = RR_ADC_TRIGGER_EVERY_CYCLE, + }, + { + .label = "chg", + .lsb = RR_ADC_CHARGER_TEMP_LSB, + .status = RR_ADC_CHARGER_TEMP_STS, + .size = 2, + .trigger_addr = RR_ADC_CHARGER_TEMP_TRIGGER, + }, + { + .label = "gpio", + .lsb = RR_ADC_GPIO_LSB, + .status = RR_ADC_GPIO_STS, + .size = 2, + .trigger_addr = RR_ADC_GPIO_TRIGGER, + }, +}; + +static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX] = { + { + .type = IIO_RESISTANCE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .channel = RR_ADC_BATT_ID, + .indexed = 1, + }, + { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .channel = RR_ADC_BATT_THERM, + .indexed = 1, + }, + { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OFFSET), + .channel = RR_ADC_SKIN_TEMP, + .indexed = 1, + }, + { + .type = IIO_CURRENT, + .info_mask_separate = + BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .channel = RR_ADC_USBIN_I, + .indexed = 1, + }, + { + .type = IIO_VOLTAGE, + .info_mask_separate = + BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .channel = RR_ADC_USBIN_V, + .indexed = 1, + }, + { + .type = IIO_CURRENT, + .info_mask_separate = + BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .channel = RR_ADC_DCIN_I, + .indexed = 1, + }, + { + .type = IIO_VOLTAGE, + .info_mask_separate = + BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .channel = RR_ADC_DCIN_V, + .indexed = 1, + }, + { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OFFSET), + .channel = RR_ADC_DIE_TEMP, + .indexed = 1, + }, + { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_OFFSET) | + BIT(IIO_CHAN_INFO_SCALE), + .channel = RR_ADC_CHG_TEMP, + .indexed = 1, + }, + { + .type = IIO_VOLTAGE, + .info_mask_separate = + BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .channel = RR_ADC_GPIO, + .indexed = 1, + }, +}; + +static int rradc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct iio_dev *indio_dev; + struct rradc_chip *chip; + int ret, i; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*chip)); + if (!indio_dev) + return -ENOMEM; + + chip = iio_priv(indio_dev); + chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!chip->regmap) { + dev_err(dev, "Couldn't get parent's regmap\n"); + return -EINVAL; + } + + chip->dev = dev; + mutex_init(&chip->conversion_lock); + + ret = device_property_read_u32(dev, "reg", &chip->base); + if (ret < 0) { + dev_err(chip->dev, "Couldn't find reg address, ret = %d\n", + ret); + return ret; + } + + chip->batt_id_delay = -EINVAL; + ret = device_property_read_u32(dev, "qcom,batt-id-delay-ms", + &chip->batt_id_delay); + if (!ret) { + for (i = 0; i < RRADC_BATT_ID_DELAY_MAX; i++) { + if (chip->batt_id_delay == batt_id_delays[i]) + break; + } + if (i == RRADC_BATT_ID_DELAY_MAX) + chip->batt_id_delay = -EINVAL; + } + + /* Get the PMIC revision ID, we need to handle some varying coefficients */ + chip->pmic = qcom_pmic_get(chip->dev); + if (IS_ERR_VALUE(chip->pmic)) { + dev_err(chip->dev, "Unable to get reference to PMIC device\n"); + return PTR_ERR(chip->pmic); + } + + indio_dev->name = pdev->name; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->info = &rradc_info; + indio_dev->channels = rradc_iio_chans; + indio_dev->num_channels = RR_ADC_CHAN_MAX; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id rradc_match_table[] = { + { .compatible = "qcom,pm660-rradc" }, + { .compatible = "qcom,pmi8998-rradc" }, + {} +}; +MODULE_DEVICE_TABLE(of, rradc_match_table); + +static struct platform_driver rradc_driver = { + .driver = { + .name = "qcom-rradc", + .of_match_table = rradc_match_table, + }, + .probe = rradc_probe, +}; +module_platform_driver(rradc_driver); + +MODULE_DESCRIPTION("QCOM SPMI PMIC RR ADC driver"); +MODULE_AUTHOR("Caleb Connolly "); +MODULE_LICENSE("GPL v2"); From patchwork Fri Feb 11 21:19:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 542194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 542BBC433F5 for ; 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[81.96.50.79]) by smtp.gmail.com with ESMTPSA id x5sm14276017wrv.63.2022.02.11.13.20.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Feb 2022 13:20:21 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v4 5/8] arm64: dts: qcom: pmi8998: add rradc node Date: Fri, 11 Feb 2022 21:19:56 +0000 Message-Id: <20220211211959.502514-6-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220211211959.502514-1-caleb.connolly@linaro.org> References: <20220211211959.502514-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a DT node for the Round Robin ADC found in the PMI8998 PMIC. Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index 0fef5f113f05..da10668c361d 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -18,6 +18,14 @@ pmi8998_gpio: gpios@c000 { interrupt-controller; #interrupt-cells = <2>; }; + + pmi8998_rradc: rradc@4500 { + compatible = "qcom,pmi8998-rradc"; + reg = <0x4500>; + #io-channel-cells = <1>; + + status = "disabled"; + }; }; pmi8998_lsid1: pmic@3 { From patchwork Fri Feb 11 21:19:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 541877 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2F36C4167D for ; Fri, 11 Feb 2022 21:20:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231287AbiBKVU2 (ORCPT ); Fri, 11 Feb 2022 16:20:28 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:44620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353582AbiBKVU1 (ORCPT ); Fri, 11 Feb 2022 16:20:27 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B5B1C65 for ; Fri, 11 Feb 2022 13:20:24 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id h6so17235574wrb.9 for ; Fri, 11 Feb 2022 13:20:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qImSYxU2i/y/qV71r8EFW+LTWk9ZfhM4KeM2jcTcklQ=; b=QxSLu+fdnas6QlKDy7hc1wCxmmCDCQi+UF54FoGDjT0/row5+zFN9h7vVwxtrRwgEb RsfLpn8W7cF5CJun/sXq2tSchnoPLFfOzWSuMXAyP2m1fhf4AA0iFuyA5CUaYNGYHi9f AKK5+Y3lFoZ/VCNbsyoLptA60yuRKPckAipE9+dzW+alA7ceSttMPnuzIXP5O4VHIDlT UMA7a2c8IBIJgyCU4wjbOT7k+qT0yluM35SUIWi4FoVFXUZMfiqboAzISXONTrr6XUbX qlmd3DL7VH8mFxttR5mgcKBo1dE8RYc8Nb2OWmowPk4wulvWt6VsirLWQgmH0uP5psUi A0Hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qImSYxU2i/y/qV71r8EFW+LTWk9ZfhM4KeM2jcTcklQ=; b=75Bbkblb1R2SA0TzPbi/ZWWoopIbThSK/blpasF9qPgRX2+VJYH0+50h28rkYxCGVD CN38xVvqMbowIxmbfChAUWgb33QVRrl0Q1NTtJypOelaG/bfHD2+ITrX0mKgXCJunzoL SYXIlpdb9QzU6ujcsFSclCkcnx7Y7GWdie7TGGz/rSrGgPHpPgfvpn3R17djaBYZLA+T skWYZBu7h2d4csUuW1l4YGXvI91Hap4f3ub37iwrANAN4UWMJ9VU+2wxwxSrKM+aygNi rrTKo1ANp06apN5fcuE5GjJGfkCF4znqbj4olEZjqnFL6hZHgBx9TBI1kBRIkkUsb8DO 3i2g== X-Gm-Message-State: AOAM531Ot3CGTu8qQToqjVmVqpLZphR7MTNrIDKZHt8+0WHPNNoG74Gx IbMM2XyF8A1pS0x6NHrl7XSxCA== X-Google-Smtp-Source: ABdhPJwEMh8WUnv/93PC2BLzWSybKIbelfP/NotI4vBM1XGxq9G+upA/cpNaC5b5dt47h+SnBImeBw== X-Received: by 2002:adf:e350:: with SMTP id n16mr2623926wrj.180.1644614423232; Fri, 11 Feb 2022 13:20:23 -0800 (PST) Received: from localhost.localdomain (cpc78119-cwma10-2-0-cust590.7-3.cable.virginm.net. [81.96.50.79]) by smtp.gmail.com with ESMTPSA id x5sm14276017wrv.63.2022.02.11.13.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Feb 2022 13:20:22 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v4 6/8] arm64: dts: qcom: sdm845-oneplus: enable rradc Date: Fri, 11 Feb 2022 21:19:57 +0000 Message-Id: <20220211211959.502514-7-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220211211959.502514-1-caleb.connolly@linaro.org> References: <20220211211959.502514-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable the RRADC for the OnePlus 6. Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 7f42e5315ecb..e8287cf02511 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -450,6 +450,10 @@ pinconf { }; }; +&pmi8998_rradc { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; From patchwork Fri Feb 11 21:19:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 542192 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5061C35273 for ; Fri, 11 Feb 2022 21:20:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351283AbiBKVUa (ORCPT ); Fri, 11 Feb 2022 16:20:30 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:44728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353589AbiBKVUa (ORCPT ); Fri, 11 Feb 2022 16:20:30 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AE64C68 for ; Fri, 11 Feb 2022 13:20:27 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id w11so17271860wra.4 for ; Fri, 11 Feb 2022 13:20:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o/d166yo9TtkM4+c7x0I89HNNMPO2K1Na/pBqagV1Y0=; b=MbgOlo5spfEC8hCE/EOFxOS2ueJMFq4HKxYCjwdtVmnelMXcnzpLW2NrAhaYmrgWey bJczkKEOn8ytNuZ8PsRDkR0QW/LDeD7e4N/u+qRHh00cW9uXtXplcVrMFfqguoLd5TlI lOFvwLGGLsFCWuqR4/aNUR/oh7rnHSDHfNDenAyQgKheud8B9j+u0daw3TG+hofMmLRo JY6DzswkszG8CV38N2KK4Y++aMNg35LKm+fUxySbFWVg8cZnYfxf8c5O2xNbdoQv7r9p TJOKbFXYaVcL5A+O7IjKQSV1+x40fJ1UB84H0Kj16osJRxSJiqOCkZX3B3ninGoya7R3 R+dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o/d166yo9TtkM4+c7x0I89HNNMPO2K1Na/pBqagV1Y0=; b=bl9HTyHF3uB39AxVuabx+rG2QhwaUMlnT9mHWQ+CoKS5YZQVqHYltoFK1475JynfGd AIo5zH4o2EW6Vle8zNLZJJSIw2nT451oVPKYMFyKV45/AvEcX6V5IA0P3qrWB37sGY/R rwx4AyTXjvn00gh5peRg1BG9kNGwVCVWYQ1vhsRKxucU1x4aPeEtfcdSYgN8m6UouMU2 zi78eIxSXBOhgYyMWYLwxtO2iA4/eL777ihWzim0+uyBNEHdC1FMstR05vIeZ8L9fO8F sZL+8tLDwie6vuYuJ5/MG09mWH1MM7xJ8RSoRcLrBlRboiETeg9LN1+NWGZ2gpC/+rD0 YIfw== X-Gm-Message-State: AOAM531BzVejlw6gAA7bvZlozxH2HvC6+ihW9qc0iqv+53ve/kTt8HH6 X2gP8WNlsDkJree4oURy4lBWUg== X-Google-Smtp-Source: ABdhPJziSJsedjC6g3EGZpOd6xSdkDK2oGv9uEK65oxUBGa3mTJzU2KatuQnr6TNOXXP4Ax51gl13A== X-Received: by 2002:adf:e409:: with SMTP id g9mr2812714wrm.496.1644614424204; Fri, 11 Feb 2022 13:20:24 -0800 (PST) Received: from localhost.localdomain (cpc78119-cwma10-2-0-cust590.7-3.cable.virginm.net. [81.96.50.79]) by smtp.gmail.com with ESMTPSA id x5sm14276017wrv.63.2022.02.11.13.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Feb 2022 13:20:23 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v4 7/8] arm64: dts: qcom: sdm845-db845c: enable rradc Date: Fri, 11 Feb 2022 21:19:58 +0000 Message-Id: <20220211211959.502514-8-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220211211959.502514-1-caleb.connolly@linaro.org> References: <20220211211959.502514-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable the Round Robin ADC for the db845c. Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 13f80a0b6faa..1c452b458121 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -595,6 +595,10 @@ resin { }; }; +&pmi8998_rradc { + status = "okay"; +}; + /* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ &q6afedai { qi2s@22 { From patchwork Fri Feb 11 21:19:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 542193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94EF1C4167E for ; Fri, 11 Feb 2022 21:20:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353560AbiBKVUa (ORCPT ); Fri, 11 Feb 2022 16:20:30 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:44696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353582AbiBKVU3 (ORCPT ); Fri, 11 Feb 2022 16:20:29 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F633C5D for ; Fri, 11 Feb 2022 13:20:26 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id v12so17320396wrv.2 for ; Fri, 11 Feb 2022 13:20:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=60je+LDflCDSpm+PbhIAk73PJa9MombVHWRyiPaaQWE=; b=h4WkdtLhlBFobnAEkWmySA8Nwmeb85SKr+lb6GsK6epAGVSFu2EIbIhkirXz2GADJu lH9AZPve5vGvhS4FsiP7BFHDLrAReADlmzMZNYNsVskOU5pNbNaaqmpq13AnOKfQ8xKT uPepIay2aY0NR/sK+eXdqegDfs7bUKIdXoAL+l6LdLmSaQeFL58Od6TS4NQO+Kj0UY3e QnrBLrYmGaxnONnYkFAFHXBCGfs/v/CcN+N5VKvKK/7aklrABjR7bsmd+TCdyR8wX/Vt kekGeMqysyIYTBEVZ0kNd5RJsjjYMZhv/g9mCUTarPp9vBBf6KGmAn+w2gjnPCWBSpUb pACw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=60je+LDflCDSpm+PbhIAk73PJa9MombVHWRyiPaaQWE=; b=a8P4OODjrIkxNVUox5m2fygQJ+GO+MDO/SoOsoz1+KMCw2jKZgS3G9dztzGOI1YxiB dXkd40K9P8FvbdKV2poo5nW5d6azr96+HcyWNxq0lvv0JfBtXPp9W3ehvT6O9xxHYmjM Z1ADlIDoHLFaz8xJHP1F+Vfsq+t5MHFhBPBtud9T9xGE7XKYR+lc+K2RH3+7ATI/VAaL 2gM+KGIveRWjt4Rl01e4O2QyhAUByhSStTISC1zmpxnYBtq1WJUgF3urTVYbdu2JfG3I 9Mds3ALchIUd1sqkPRMalN7lnsijkeOrO49xjfKfH4JwHNwKSZoUjHj47TvLoHBt8Cyf Q+7Q== X-Gm-Message-State: AOAM532aBDeL4INh5fD1gwSLepUyPBcCpSTIjPFXjpo5E5TDn4hYpV6I 5kcMo49mQ0T01U3sacEnlhOZRg== X-Google-Smtp-Source: ABdhPJzl3510qY7LU+n/pjQhbwF8vGNgMmFzEqER8E1ik5IHSTONjlcek0QUwEgXL1JJ47kcjHuOqg== X-Received: by 2002:a05:6000:170e:: with SMTP id n14mr2757727wrc.595.1644614425290; Fri, 11 Feb 2022 13:20:25 -0800 (PST) Received: from localhost.localdomain (cpc78119-cwma10-2-0-cust590.7-3.cable.virginm.net. [81.96.50.79]) by smtp.gmail.com with ESMTPSA id x5sm14276017wrv.63.2022.02.11.13.20.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Feb 2022 13:20:24 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v4 8/8] arm64: dts: qcom: sdm845-xiaomi-beryllium: enable rradc Date: Fri, 11 Feb 2022 21:19:59 +0000 Message-Id: <20220211211959.502514-9-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220211211959.502514-1-caleb.connolly@linaro.org> References: <20220211211959.502514-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable the PMI8998 RRADC. Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 367389526b41..b3b6aa4e0fa3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -312,6 +312,10 @@ resin { }; }; +&pmi8998_rradc { + status = "okay"; +}; + /* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */ &q6afedai { qi2s@22 {