From patchwork Tue Nov 27 16:29:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 152142 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1486190ljp; Tue, 27 Nov 2018 08:30:01 -0800 (PST) X-Google-Smtp-Source: AFSGD/Xmu17gaw2D0V2eg1LREQsrNLp56sI+3XPqawuNVDE4+Ohb8lm3vbdjOZItCt3/ehmGhhM0 X-Received: by 2002:a17:902:724a:: with SMTP id c10mr17297689pll.51.1543336201165; Tue, 27 Nov 2018 08:30:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543336201; cv=none; d=google.com; s=arc-20160816; b=NdAduyQVEetJYiSIhy+ocj9gEn2q1r4s19BF8bPkFtV1pkR7oa+JvuGX2lCfYWP3/r N7lg4xF9TDllJJTMGbQbPMirPh2y+r1WDtAONmxRh4Vm9t3vjwLavSnhBL8pjLLrtNZY WXRrPJhtj+8MAWwqmPUMqttmrpGOTZufKnHUrHyA1fXqlfGbjdDfrdTREVDKqQu8G42Z zT/7rpKueDdeQ6OQ3JB5GfLGI+MLD0mirzoifVzzgtyZ78WpmJf4ySCSP5QV7m+WrMOe DEMNWb4d9E+mKHHtu1DPPWdMTITNrqgk+4GnOiHm19PwvTKMm7Gf4H26+eUTDrA5Ns/E 1bkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=s5zhkfCpfsrybfxA0ie5n6DnKn1jNcno8a7LLALW7fc=; b=W3BG52FKbJmk9iqqPfm5sPy7sC2PKJ9lz+pcaUrr1Y8AzlV5s+ETVDT3JZMbwjndRQ FWaoyHnPU3UoLlorOzero+s7xq22FO1fFXzx3+/hkUl9Lo/2EUUnlfK4t4DrD9D+JuBe F+zQ/RSQDsEbla4ypug+h1i9Qh/pbdQLN4QO0DO2vfj1sXmUalpXyXvx6364tO+QNcTB /wxKuBXStHLCMpFw/b8w98O74akTbO5yn3pbk8ooexCliOxOdVRuuo4ZF94ozY+M2p63 Cn+dV+YQE7iWQ1piQzW5N4N0qR+7XHr/s5B3WdgNDTyh/5kLyJbjWBWYyF1NaxBEJQoA gTpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W0aDCfqb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s24si4396224plq.41.2018.11.27.08.29.53; Tue, 27 Nov 2018 08:30:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W0aDCfqb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731093AbeK1D15 (ORCPT + 32 others); Tue, 27 Nov 2018 22:27:57 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:45050 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731074AbeK1D14 (ORCPT ); Tue, 27 Nov 2018 22:27:56 -0500 Received: by mail-wr1-f68.google.com with SMTP id z5so19041416wrt.11 for ; Tue, 27 Nov 2018 08:29:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=s5zhkfCpfsrybfxA0ie5n6DnKn1jNcno8a7LLALW7fc=; b=W0aDCfqbcIPSRmcdsX12/LQ8Ufi7EHRGwNuS1GPizZ2EDJWTFmGyi8CLLkm2O6AgGE Bfd+uNsi373GPo7hZzoLEMBkn+Bxc2qZJupojzI+4wkqHuJ3UluyeUptT7sde5h3IQQm OG3lRm9v2lv36OEZ/zilPzUrU5hsC3kEkZMFM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=s5zhkfCpfsrybfxA0ie5n6DnKn1jNcno8a7LLALW7fc=; b=BI0wXGGIBiRV4IxPZbze/kWyFGHAlv9mbGnEYn5jF/aLLOZKI5LTWOXyWBBkRt5Eid f3V7wgsYL+NMjdgyfnrx+JGoh6D4sV6KeAoGclsvpsR0E7emjOUumluvEv7W0GJvtaib ED4Hav6b4xcHuUrh/A8I0FpvsmLHi/dPTVLsJEFBRXCBY6KX+vhozEBtjUbbMFVPz3wH GsdQpgsAQqZcd85u1jIcN8PF4RlcrS1AJHUgh/Ue9d3job0J/xUHKpgiIcpGFYnfJ68m kSZVF6le+TX6Pch6HAx3inms8SVX8cXiqJZuYeClFKEEMhaRU2M6EgJnMDS36knHU4eV /qIw== X-Gm-Message-State: AA+aEWa8CNl1H4V9JNVDHD+du8O/Z5Q9KJX1s4GzsvFqXWBVrwlotULK ln4WLkrR3e3hnUfKvLAM5nM92kiM+4s= X-Received: by 2002:adf:9422:: with SMTP id 31mr16736576wrq.106.1543336168929; Tue, 27 Nov 2018 08:29:28 -0800 (PST) Received: from localhost ([49.248.92.105]) by smtp.gmail.com with ESMTPSA id s139sm6736196wmd.3.2018.11.27.08.29.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Nov 2018 08:29:28 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, vkoul@kernel.org, khasim.mohammed@linaro.org, Zhang Rui , Daniel Lezcano , Rob Herring , Mark Rutland Subject: [PATCH v3 1/4] dt: thermal: tsens: Add bindings for qcs404 Date: Tue, 27 Nov 2018 21:59:04 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org qcs404 uses v1 of the TSENS IP block. Create a fallback DT property "qcom,tsens-v1" to gather common code. Signed-off-by: Amit Kucheria Reviewed-by: Vinod Koul Tested-by: Vinod Koul --- Documentation/devicetree/bindings/thermal/qcom-tsens.txt | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt index 1d9e8cf61018..799de3062352 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt @@ -8,9 +8,12 @@ Required properties: - "qcom,msm8996-tsens" (MSM8996) - "qcom,msm8998-tsens", "qcom,tsens-v2" (MSM8998) - "qcom,sdm845-tsens", "qcom,tsens-v2" (SDM845) + - "qcom,qcs404-tsens", "qcom,tsens-v1" (QCS404) The generic "qcom,tsens-v2" property must be used as a fallback for any SoC with version 2 of the TSENS IP. MSM8996 is the only exception because the generic property did not exist when support was added. + Similarly, the generic "qcom,tsens-v1" property must be used as a fallback for + any SoC with version 1 of the TSENS IP. - reg: Address range of the thermal registers. New platforms containing v2.x.y of the TSENS IP must specify the SROT and TM From patchwork Tue Nov 27 16:29:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 152143 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1486356ljp; Tue, 27 Nov 2018 08:30:08 -0800 (PST) X-Google-Smtp-Source: AFSGD/VSnbFjkTfsE/8Q9k6XWTwDATOzPEXsuvWCdwujhxfrSjCIL5DoFwXwAQWOl+xxN9nzx8nJ X-Received: by 2002:a63:2586:: with SMTP id l128mr30195316pgl.104.1543336208480; Tue, 27 Nov 2018 08:30:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543336208; cv=none; d=google.com; s=arc-20160816; b=YDpgwMjuWrbzo8Q9ieEDTQ6exLJv8WQzoxB1Z6k7oC1kRl1Arpwno70Hu8dfM+DgVN gKSTy8M9tco/uMsr4DTdy275X+izSEJYd2ECUP3fwffDKmWvQbsjynVqnvm//DroiWkQ OOKWE5rVH7RozBZ83LXeaq/hoYcx+U0N94N9T7vPSNqtc1/G2bSTivyWy6tNLhyKk+6u z1ZTzQ4EHIJz/oDwCxKWxqTNdx0vDcVArsndymZeQdFPRFwQRXKwjZQNRfLf0lDn9gpi U9jogUUrBSKRS1BI6AekSH052Ox+fnhGsLsBB4usPYBkk/LN6Tkvjz/kgb0WKXIVN+cl 8+tQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=BylX33cS3WT8vpnwLcJYmHJwvcIW8NPYepeh979rT/Y=; b=pCST30aEvfGfeMIveOru3kg1rH2V9ZByx1s5fq0hDShPeVHgKuuExJnbPkplUCxjwJ Av5VDKO4UH1G9SbkN4uDe6Ih0Vg3fxrA3ok2wBIH7IDOcXUHQykSPHornk4ABK7prIgV wElOZ2pQwPrvN4GjHMOVOE83YKsuBcvop7CHEQ7VnYa9GYvUMkSPSh0IDvN5tp9pdn5+ 4+s/b9gCHhIFEFKgiiuLVXrUSu4dAeR3lfcGyH+rD4QUzOmTTeofZ8Vz8+lLi13adMUe JkVMsLwFj4TWCCVj4CW9WQmi8os7WdVMkXzohWve11MlljwJH++jBaL2IEJO+Np/ZooX 9B1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="HXxd/UZf"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s24si4396224plq.41.2018.11.27.08.30.01; Tue, 27 Nov 2018 08:30:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="HXxd/UZf"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731106AbeK1D2K (ORCPT + 32 others); Tue, 27 Nov 2018 22:28:10 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:40054 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730444AbeK1D2J (ORCPT ); Tue, 27 Nov 2018 22:28:09 -0500 Received: by mail-wm1-f67.google.com with SMTP id q26so22795292wmf.5 for ; Tue, 27 Nov 2018 08:29:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=BylX33cS3WT8vpnwLcJYmHJwvcIW8NPYepeh979rT/Y=; b=HXxd/UZf9xiZr7kRcIy8dGg03mbzq9Y0S5ROI6V0cbfbyLnE8uzwAxt778JTtSxGMD xaZDmbG+03GnnWIw00lzzbLCppDTHoHgQHZ2o3chCxYq+KLslQgr1yCe/glcObDTXk4k 26exEBMAQqdXy5+K+P3ulENNc2YdxeNK+xyC4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=BylX33cS3WT8vpnwLcJYmHJwvcIW8NPYepeh979rT/Y=; b=IzEpZ5i+4GeyT20NIO+YyVRSwpSJ++jmTYJu4SH+VJnABewyuBYdRbXCyFMaPmFyud nnd0Co7Z2qKLBgVuxeVAdhT6HGZHMGp2rVFI/JJStUiOOrng6VmwH8/wDBZEWMEoyJ9c VvpMQJyZZ6C3Rb4vSQcVsSf+Efnt7WY9zv+g1iJ1nQUEfc0pYCxpFDWbaU9lBIC0RVhO vGbgeDoowoOzV1UY9ok7ZiHU3T/OM73tYwB9k1jBsnrIV8RaZweH50Baymuss1cVYCo/ P7RXStHTt2y64JIxXIRqc4+eDHaYzsUa96+pp7YD8LDMV4h5KKdHVw8ba6awiqPupDkf t3SA== X-Gm-Message-State: AA+aEWZC1Zbq+CaU8oj4VXM4tV+iixpXi7XpNaMi1MTNF2KwECpxqy7E X6SQPKo+ufs6lpdgG4dQDx+YDZvi3L8= X-Received: by 2002:a1c:cf82:: with SMTP id f124mr21573532wmg.95.1543336181360; Tue, 27 Nov 2018 08:29:41 -0800 (PST) Received: from localhost ([49.248.92.105]) by smtp.gmail.com with ESMTPSA id j8sm5579490wmd.0.2018.11.27.08.29.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Nov 2018 08:29:40 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, vkoul@kernel.org, khasim.mohammed@linaro.org, Zhang Rui , Daniel Lezcano Subject: [PATCH v3 2/4] drivers: thermal: tsens: Add generic support for TSENS v1 IP Date: Tue, 27 Nov 2018 21:59:05 +0530 Message-Id: <578f79ce10c51bbb7bd6f44395e10a3369a050f4.1543335819.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org qcs404 has a single TSENS IP block with 10 sensors. It uses version 1.4 of the TSENS IP, functionality for which is encapsulated inside qcom,tsens-v1 compatible. Signed-off-by: Amit Kucheria Reviewed-by: Vinod Koul Tested-by: Vinod Koul --- drivers/thermal/qcom/Makefile | 2 +- drivers/thermal/qcom/tsens-common.c | 2 +- drivers/thermal/qcom/tsens-v1.c | 196 ++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 3 + drivers/thermal/qcom/tsens.h | 3 +- 5 files changed, 203 insertions(+), 3 deletions(-) create mode 100644 drivers/thermal/qcom/tsens-v1.c -- 2.17.1 diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index a821929ede0b..60269ee90c43 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -1,2 +1,2 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o -qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-v2.o +qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-v2.o tsens-v1.o diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 3be4be2e0465..98f77401bc12 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -76,7 +76,7 @@ void compute_intercept_slope(struct tsens_device *tmdev, u32 *p1, } } -static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s) +int code_to_degc(u32 adc_code, const struct tsens_sensor *s) { int degc, num, den; diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c new file mode 100644 index 000000000000..1dbf4fde6da8 --- /dev/null +++ b/drivers/thermal/qcom/tsens-v1.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, Linaro Limited + */ + +#include +#include +#include "tsens.h" + +/* eeprom layout data for qcs404 (v1) */ +#define BASE0_MASK 0x000007f8 +#define BASE1_MASK 0x0007f800 +#define BASE0_SHIFT 3 +#define BASE1_SHIFT 11 + +#define S0_P1_MASK 0x0000003f +#define S1_P1_MASK 0x0003f000 +#define S2_P1_MASK 0x3f000000 +#define S3_P1_MASK 0x000003f0 +#define S4_P1_MASK 0x003f0000 +#define S5_P1_MASK 0x0000003f +#define S6_P1_MASK 0x0003f000 +#define S7_P1_MASK 0x3f000000 +#define S8_P1_MASK 0x000003f0 +#define S9_P1_MASK 0x003f0000 + +#define S0_P2_MASK 0x00000fc0 +#define S1_P2_MASK 0x00fc0000 +#define S2_P2_MASK_1_0 0xc0000000 +#define S2_P2_MASK_5_2 0x0000000f +#define S3_P2_MASK 0x0000fc00 +#define S4_P2_MASK 0x0fc00000 +#define S5_P2_MASK 0x00000fc0 +#define S6_P2_MASK 0x00fc0000 +#define S7_P2_MASK_1_0 0xc0000000 +#define S7_P2_MASK_5_2 0x0000000f +#define S8_P2_MASK 0x0000fc00 +#define S9_P2_MASK 0x0fc00000 + +#define S0_P1_SHIFT 0 +#define S0_P2_SHIFT 6 +#define S1_P1_SHIFT 12 +#define S1_P2_SHIFT 18 +#define S2_P1_SHIFT 24 +#define S2_P2_SHIFT_1_0 30 + +#define S2_P2_SHIFT_5_2 0 +#define S3_P1_SHIFT 4 +#define S3_P2_SHIFT 10 +#define S4_P1_SHIFT 16 +#define S4_P2_SHIFT 22 + +#define S5_P1_SHIFT 0 +#define S5_P2_SHIFT 6 +#define S6_P1_SHIFT 12 +#define S6_P2_SHIFT 18 +#define S7_P1_SHIFT 24 +#define S7_P2_SHIFT_1_0 30 + +#define S7_P2_SHIFT_5_2 0 +#define S8_P1_SHIFT 4 +#define S8_P2_SHIFT 10 +#define S9_P1_SHIFT 16 +#define S9_P2_SHIFT 22 + +#define CAL_SEL_MASK 7 +#define CAL_SEL_SHIFT 0 + +static int calibrate_v1(struct tsens_device *tmdev) +{ + u32 base0 = 0, base1 = 0; + u32 p1[10], p2[10]; + u32 mode = 0, lsb = 0, msb = 0; + u32 *qfprom_cdata; + int i; + + qfprom_cdata = (u32 *)qfprom_read(tmdev->dev, "calib"); + if (IS_ERR(qfprom_cdata)) + return PTR_ERR(qfprom_cdata); + + mode = (qfprom_cdata[4] & CAL_SEL_MASK) >> CAL_SEL_SHIFT; + dev_dbg(tmdev->dev, "calibration mode is %d\n", mode); + + switch (mode) { + case TWO_PT_CALIB: + base1 = (qfprom_cdata[4] & BASE1_MASK) >> BASE1_SHIFT; + p2[0] = (qfprom_cdata[0] & S0_P2_MASK) >> S0_P2_SHIFT; + p2[1] = (qfprom_cdata[0] & S1_P2_MASK) >> S1_P2_SHIFT; + /* This value is split over two registers, 2 bits and 4 bits */ + lsb = (qfprom_cdata[0] & S2_P2_MASK_1_0) >> S2_P2_SHIFT_1_0; + msb = (qfprom_cdata[1] & S2_P2_MASK_5_2) >> S2_P2_SHIFT_5_2; + p2[2] = msb << 2 | lsb; + p2[3] = (qfprom_cdata[1] & S3_P2_MASK) >> S3_P2_SHIFT; + p2[4] = (qfprom_cdata[1] & S4_P2_MASK) >> S4_P2_SHIFT; + p2[5] = (qfprom_cdata[2] & S5_P2_MASK) >> S5_P2_SHIFT; + p2[6] = (qfprom_cdata[2] & S6_P2_MASK) >> S6_P2_SHIFT; + /* This value is split over two registers, 2 bits and 4 bits */ + lsb = (qfprom_cdata[2] & S7_P2_MASK_1_0) >> S7_P2_SHIFT_1_0; + msb = (qfprom_cdata[3] & S7_P2_MASK_5_2) >> S7_P2_SHIFT_5_2; + p2[7] = msb << 2 | lsb; + p2[8] = (qfprom_cdata[3] & S8_P2_MASK) >> S8_P2_SHIFT; + p2[9] = (qfprom_cdata[3] & S9_P2_MASK) >> S9_P2_SHIFT; + for (i = 0; i < tmdev->num_sensors; i++) + p2[i] = ((base1 + p2[i]) << 2); + /* Fall through */ + case ONE_PT_CALIB2: + base0 = (qfprom_cdata[4] & BASE0_MASK) >> BASE0_SHIFT; + p1[0] = (qfprom_cdata[0] & S0_P1_MASK) >> S0_P1_SHIFT; + p1[1] = (qfprom_cdata[0] & S1_P1_MASK) >> S1_P1_SHIFT; + p1[2] = (qfprom_cdata[0] & S2_P1_MASK) >> S2_P1_SHIFT; + p1[3] = (qfprom_cdata[1] & S3_P1_MASK) >> S3_P1_SHIFT; + p1[4] = (qfprom_cdata[1] & S4_P1_MASK) >> S4_P1_SHIFT; + p1[5] = (qfprom_cdata[2] & S5_P1_MASK) >> S5_P1_SHIFT; + p1[6] = (qfprom_cdata[2] & S6_P1_MASK) >> S6_P1_SHIFT; + p1[7] = (qfprom_cdata[2] & S7_P1_MASK) >> S7_P1_SHIFT; + p1[8] = (qfprom_cdata[3] & S8_P1_MASK) >> S8_P1_SHIFT; + p1[9] = (qfprom_cdata[3] & S9_P1_MASK) >> S9_P1_SHIFT; + for (i = 0; i < tmdev->num_sensors; i++) + p1[i] = (((base0) + p1[i]) << 2); + break; + default: + for (i = 0; i < tmdev->num_sensors; i++) { + p1[i] = 500; + p2[i] = 780; + } + break; + } + + compute_intercept_slope(tmdev, p1, p2, mode); + + return 0; +} + +#define STATUS_OFFSET 0x44 +#define LAST_TEMP_MASK 0x3ff +#define STATUS_VALID_BIT BIT(14) + +static int get_temp_tsens_v1(struct tsens_device *tmdev, int id, int *temp) +{ + struct tsens_sensor *s = &tmdev->sensor[id]; + u32 code; + unsigned int status_reg; + u32 last_temp = 0, last_temp2 = 0, last_temp3 = 0; + int ret; + + status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * 4; + ret = regmap_read(tmdev->tm_map, status_reg, &code); + if (ret) + return ret; + last_temp = code & LAST_TEMP_MASK; + if (code & STATUS_VALID_BIT) + goto done; + + /* Try a second time */ + ret = regmap_read(tmdev->tm_map, status_reg, &code); + if (ret) + return ret; + if (code & STATUS_VALID_BIT) { + last_temp = code & LAST_TEMP_MASK; + goto done; + } else { + last_temp2 = code & LAST_TEMP_MASK; + } + + /* Try a third/last time */ + ret = regmap_read(tmdev->tm_map, status_reg, &code); + if (ret) + return ret; + if (code & STATUS_VALID_BIT) { + last_temp = code & LAST_TEMP_MASK; + goto done; + } else { + last_temp3 = code & LAST_TEMP_MASK; + } + + if (last_temp == last_temp2) + last_temp = last_temp2; + else if (last_temp2 == last_temp3) + last_temp = last_temp3; +done: + /* Convert temperature from ADC code to milliCelsius */ + *temp = code_to_degc(last_temp, s) * 1000; + + return 0; +} + +static const struct tsens_ops ops_generic_v1 = { + .init = init_common, + .calibrate = calibrate_v1, + .get_temp = get_temp_tsens_v1, +}; + +const struct tsens_data data_tsens_v1 = { + .ops = &ops_generic_v1, + .reg_offsets = { [SROT_CTRL_OFFSET] = 0x4 }, +}; diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index f1ec9bbe4717..d0cc0c09894a 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -63,6 +63,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,msm8996-tsens", .data = &data_8996, + }, { + .compatible = "qcom,tsens-v1", + .data = &data_tsens_v1, }, { .compatible = "qcom,tsens-v2", .data = &data_tsens_v2, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 7b7feee5dc46..f8dc96c42b94 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -90,9 +90,10 @@ char *qfprom_read(struct device *, const char *); void compute_intercept_slope(struct tsens_device *, u32 *, u32 *, u32); int init_common(struct tsens_device *); int get_temp_common(struct tsens_device *, int, int *); +int code_to_degc(u32 adc_code, const struct tsens_sensor *s); /* TSENS v1 targets */ -extern const struct tsens_data data_8916, data_8974, data_8960; +extern const struct tsens_data data_8916, data_8974, data_8960, data_tsens_v1; /* TSENS v2 targets */ extern const struct tsens_data data_8996, data_tsens_v2;