From patchwork Thu Feb 10 11:30:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 541431 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp2151343imo; Thu, 10 Feb 2022 03:38:30 -0800 (PST) X-Google-Smtp-Source: ABdhPJwzT6+bc+AOT/COn0/Tk6GnB6MiixJC2FBReIC5+2iIk60J4DVYOL0+cDoSOLlLP/NSAIu7 X-Received: by 2002:a25:b0e:: with SMTP id 14mr6363754ybl.125.1644493110658; Thu, 10 Feb 2022 03:38:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644493110; cv=none; d=google.com; s=arc-20160816; b=m/Z6G9aVd8QdxA8eTTBdes5SVflJoiI6TBetZksB720qE74/9FyMxdIjd/FjWZIoNd 6pUV2xEZyGl0CNVzpnEBmaFCOFN40tmjIWA8GFv43sm7suHKGdt0XJQBcMK4oayyIeBn 5vb0YETdYpUbW9RsVFCLfB5LOyGkmRTaN9EthQIDUchHpZ+FrX+NIhmMuOwVU1KtoQUL ZXyNcoUW4TJEPFRmomWn/I3fBkwOqq037hSg70REoxLzPYJpAoBrTjptupww26bAm/Lj gfEyUS12iZPNmAjLL8GPY2RO6dj+IHjyGmUeLNzz1u831Eln+3bUfdN4xXg+ByIeI0KZ g9qQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=A473qbjGyhHnN0ZQyd0Yg8rCuTL/rArhdYtN54HK9fc=; b=o1WCVPrjVl0pVEwbvlH3T5ABSEs696Xrh/B4XblirveFc00/m9Z+VTQzj/KnXJCAFi Z6Ax6rg9HOXgWVheLV0CZ6xrlAfb0vry5KcTptiwzp13obwkCmDjGLSYGf8g+RqyDBNY 0uOgAtEZgt4Wzk0u7uRcKpkGQfaCVKqnpMR5pQdcmcQWG13+RBLo9mOZLbgiQoVtWinO yOdiZ1Q5qFVOoAMpBebzdoS0XKgLbcbJNiBmCSXxRPxR0Mz23JwVDpxEYataGs6Z0ART 5BLIx1aAY/L2I8u2aD4FTdlaREFOXBlxczhPqXy4b6ajm5xeMfz06VwUxWHWmpW6PGqU I20g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gAaJXt9+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b62si13939097ybc.773.2022.02.10.03.38.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Feb 2022 03:38:30 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gAaJXt9+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nI7mQ-0000FB-3r for patch@linaro.org; Thu, 10 Feb 2022 06:38:30 -0500 Received: from eggs.gnu.org ([209.51.188.92]:42386) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nI7ee-0003hr-4T for qemu-devel@nongnu.org; Thu, 10 Feb 2022 06:30:28 -0500 Received: from [2a00:1450:4864:20::62f] (port=33735 helo=mail-ej1-x62f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nI7eb-0002VP-L2 for qemu-devel@nongnu.org; Thu, 10 Feb 2022 06:30:27 -0500 Received: by mail-ej1-x62f.google.com with SMTP id fy20so14507929ejc.0 for ; Thu, 10 Feb 2022 03:30:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A473qbjGyhHnN0ZQyd0Yg8rCuTL/rArhdYtN54HK9fc=; b=gAaJXt9+Pcc1amrW6/4raCME0JCmTtXkvfAoifDAYnAAfJImvW83uWbgKA3lXjYwIv 7Azi9V/6J0StO/FmWDwqer49IjhmSaCtVLxZhHomVetfjKlRJs/b8TXUzHL/dSs3UTs3 V7Qqnjw8Q8GiTuuqVEiOfsyN2LSR+pxAHZ7aa4oKzTi4tmY7GtDUzg2bb+5ZHOX4Xxrm 1V40GlO6N09cfOO+QqDCp1/uCRsYL+pj8bwzIMHA07xMALlpp84cyjeKW0KMzFufzG8i Zw5KjAjAtDoXbEG1v3obWaDzc0ecUkg1qCRw5kDJXh2FXFfsfD1WtPjzc4oS7XKNyCEy pvyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A473qbjGyhHnN0ZQyd0Yg8rCuTL/rArhdYtN54HK9fc=; b=BWQEBUhPUz+n7tyA4CcZPZMj4DglIdwRuk2R8rcw7+uOGoTApr0KkmUdv3k3+YNEE+ xS6CCOjF0RY2tjKMMj80U/Yab9TVUaXb3bx9ZKgKSTf7oYYrD1s13dd1YQ6yornD9me/ E/JeXIEnQRCHW9j+Q0AMmlaQiJHwAaRI+uq/ijofD9oNM83PyPt/EZbpzfQbJ1ju/eBP 5yQLVrTeCQo9WpG+cpN0DnLPOXrzb/yij2VReZC+E0o8b0c8XX2Sss4FVHyf/fA9Pays aOSLYNIADnt0n/d+ukDaBFZjY3/EZE6xpu/EPpiQWVsJS/f5pLNqd1J7Gzv7Au7RKuaS sdJg== X-Gm-Message-State: AOAM5304Ocn8ASmOU7wPb6wwQ8uURB2FiyHZR3JaeFXMVkUojZb6eqn6 MtU/U9BKv4cglFweNVUfJYx0/Q== X-Received: by 2002:a17:907:3da1:: with SMTP id he33mr5997248ejc.207.1644492624027; Thu, 10 Feb 2022 03:30:24 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id m4sm1910267ejl.45.2022.02.10.03.30.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Feb 2022 03:30:22 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A04971FFB8; Thu, 10 Feb 2022 11:30:21 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v5 1/2] semihosting/arm-compat: replace heuristic for softmmu SYS_HEAPINFO Date: Thu, 10 Feb 2022 11:30:20 +0000 Message-Id: <20220210113021.3799514-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220210113021.3799514-1-alex.bennee@linaro.org> References: <20220210113021.3799514-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::62f (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Strauss , Keith Packard , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The previous numbers were a guess at best and rather arbitrary without taking into account anything that might be loaded. Instead of using guesses based on the state of registers implement a new function that: a) scans the MemoryRegions for the largest RAM block b) iterates through all "ROM" blobs looking for the biggest gap The "ROM" blobs include all code loaded via -kernel and the various -device loader techniques. Signed-off-by: Alex Bennée Cc: Andrew Strauss Cc: Keith Packard Message-Id: <20210601090715.22330-1-alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- v2 - report some known information (limits) - reword the commit message v3 - rework to use the ROM blob scanning suggested by Peter - drop arch specific wrappers - dropped rb/tb tags as it's a rework v4 - search for the largest RAM which should be the main RAM - implement the biggest gap algorithm - make stackbase the inverse of heap info v5 - move rom_find_largest_gap description to above fn and reword - add documentation of sort behaviour - handle matching se flags (- -1 -1) and (- 1 1) == 0 - add helper function and sentinal - fix off-by-ones in comparisons - allow a rambase at 0 squash! semihosting/arm-compat: replace heuristic for softmmu SYS_HEAPINFO --- include/hw/loader.h | 14 ++++ hw/core/loader.c | 86 +++++++++++++++++++++++ semihosting/arm-compat-semi.c | 129 ++++++++++++++++++---------------- 3 files changed, 168 insertions(+), 61 deletions(-) diff --git a/include/hw/loader.h b/include/hw/loader.h index 4fa485bd61..5572108ba5 100644 --- a/include/hw/loader.h +++ b/include/hw/loader.h @@ -343,4 +343,18 @@ int rom_add_option(const char *file, int32_t bootindex); * overflow on real hardware too. */ #define UBOOT_MAX_GUNZIP_BYTES (64 << 20) +typedef struct RomGap { + hwaddr base; + size_t size; +} RomGap; + +/** + * rom_find_largest_gap_between: return largest gap between ROMs in given range + * + * Given a range of addresses, this function finds the largest + * contiguous subrange which has no ROMs loaded to it. That is, + * it finds the biggest gap which is free for use for other things. + */ +RomGap rom_find_largest_gap_between(hwaddr base, size_t size); + #endif diff --git a/hw/core/loader.c b/hw/core/loader.c index 19edb928e9..ca2f2431fb 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -1333,6 +1333,92 @@ static Rom *find_rom(hwaddr addr, size_t size) return NULL; } +typedef struct RomSec { + hwaddr base; + int se; /* start/end flag */ +} RomSec; + + +/* + * Sort into address order. We break ties between rom-startpoints + * and rom-endpoints in favour of the startpoint, by sorting the 0->1 + * transition before the 1->0 transition. Either way round would + * work, but this way saves a little work later by avoiding + * dealing with "gaps" of 0 length. + */ +static gint sort_secs(gconstpointer a, gconstpointer b) +{ + RomSec *ra = (RomSec *) a; + RomSec *rb = (RomSec *) b; + + if (ra->base == rb->base) { + return ra->se - rb->se; + } + return ra->base > rb->base ? 1 : -1; +} + +static GList *add_romsec_to_list(GList *secs, hwaddr base, int se) +{ + RomSec *cand = g_new(RomSec, 1); + cand->base = base; + cand->se = se; + return g_list_prepend(secs, cand); +} + +RomGap rom_find_largest_gap_between(hwaddr base, size_t size) +{ + Rom *rom; + RomSec *cand; + RomGap res = {0, 0}; + hwaddr gapstart = base; + GList *it, *secs = NULL; + int count = 0; + + QTAILQ_FOREACH(rom, &roms, next) { + /* Ignore blobs being loaded to special places */ + if (rom->mr || rom->fw_file) { + continue; + } + /* ignore anything finishing bellow base */ + if (rom->addr + rom->romsize <= base) { + continue; + } + /* ignore anything starting above the region */ + if (rom->addr >= base + size) { + continue; + } + + /* Save the start and end of each relevant ROM */ + secs = add_romsec_to_list(secs, rom->addr, 1); + + if (rom->addr + rom->romsize < base + size) { + secs = add_romsec_to_list(secs, rom->addr + rom->romsize, -1); + } + } + + /* sentinel */ + secs = add_romsec_to_list(secs, base + size, 1); + + secs = g_list_sort(secs, sort_secs); + + for (it = g_list_first(secs); it; it = g_list_next(it)) { + cand = (RomSec *) it->data; + if (count == 0 && count + cand->se == 1) { + size_t gap = cand->base - gapstart; + if (gap > res.size) { + res.base = gapstart; + res.size = gap; + } + } else if (count == 1 && count + cand->se == 0) { + gapstart = cand->base; + } + count += cand->se; + } + + g_list_free_full(secs, g_free); + return res; +} + /* * Copies memory from registered ROMs to dest. Any memory that is contained in * a ROM between addr and addr + size is copied. Note that this can involve diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index 37963becae..3704b250b2 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -44,6 +44,7 @@ #define COMMON_SEMI_HEAP_SIZE (128 * 1024 * 1024) #else #include "qemu/cutils.h" +#include "hw/loader.h" #ifdef TARGET_ARM #include "hw/arm/boot.h" #endif @@ -144,33 +145,69 @@ typedef struct GuestFD { static GArray *guestfd_array; #ifndef CONFIG_USER_ONLY -#include "exec/address-spaces.h" -/* - * Find the base of a RAM region containing the specified address + +/** + * common_semi_find_bases: find information about ram and heap base + * + * This function attempts to provide meaningful numbers for RAM and + * HEAP base addresses. The rambase is simply the lowest addressable + * RAM position. For the heapbase we ask the loader to scan the + * address space and the largest available gap by querying the "ROM" + * regions. + * + * Returns: a structure with the numbers we need. */ -static inline hwaddr -common_semi_find_region_base(hwaddr addr) + +typedef struct LayoutInfo { + target_ulong rambase; + size_t ramsize; + hwaddr heapbase; + hwaddr heaplimit; +} LayoutInfo; + +static bool find_ram_cb(Int128 start, Int128 len, const MemoryRegion *mr, + hwaddr offset_in_region, void *opaque) +{ + LayoutInfo *info = (LayoutInfo *) opaque; + uint64_t size = int128_get64(len); + + if (!mr->ram || mr->readonly) { + return false; + } + + if (size > info->ramsize) { + info->rambase = int128_get64(start); + info->ramsize = size; + } + + /* search exhaustively for largest RAM */ + return false; +} + +static LayoutInfo common_semi_find_bases(CPUState *cs) { - MemoryRegion *subregion; + FlatView *fv; + LayoutInfo info = { 0, 0, 0, 0 }; + + RCU_READ_LOCK_GUARD(); + + fv = address_space_to_flatview(cs->as); + flatview_for_each_range(fv, find_ram_cb, &info); /* - * Find the chunk of R/W memory containing the address. This is - * used for the SYS_HEAPINFO semihosting call, which should - * probably be using information from the loaded application. + * If we have found the RAM lets iterate through the ROM blobs to + * workout the best place for the remainder of RAM and split it + * equally between stack and heap. */ - QTAILQ_FOREACH(subregion, &get_system_memory()->subregions, - subregions_link) { - if (subregion->ram && !subregion->readonly) { - Int128 top128 = int128_add(int128_make64(subregion->addr), - subregion->size); - Int128 addr128 = int128_make64(addr); - if (subregion->addr <= addr && int128_lt(addr128, top128)) { - return subregion->addr; - } - } + if (info.rambase || info.ramsize > 0) { + RomGap gap = rom_find_largest_gap_between(info.rambase, info.ramsize); + info.heapbase = gap.base; + info.heaplimit = gap.base + gap.size; } - return 0; + + return info; } + #endif #ifdef TARGET_ARM @@ -204,28 +241,6 @@ common_semi_sys_exit_extended(CPUState *cs, int nr) return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr)); } -#ifndef CONFIG_USER_ONLY -#include "hw/arm/boot.h" -static inline target_ulong -common_semi_rambase(CPUState *cs) -{ - CPUArchState *env = cs->env_ptr; - const struct arm_boot_info *info = env->boot_info; - target_ulong sp; - - if (info) { - return info->loader_start; - } - - if (is_a64(env)) { - sp = env->xregs[31]; - } else { - sp = env->regs[13]; - } - return common_semi_find_region_base(sp); -} -#endif - #endif /* TARGET_ARM */ #ifdef TARGET_RISCV @@ -251,17 +266,6 @@ common_semi_sys_exit_extended(CPUState *cs, int nr) return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8); } -#ifndef CONFIG_USER_ONLY - -static inline target_ulong -common_semi_rambase(CPUState *cs) -{ - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - return common_semi_find_region_base(env->gpr[xSP]); -} -#endif - #endif /* @@ -1165,12 +1169,12 @@ target_ulong do_common_semihosting(CPUState *cs) case TARGET_SYS_HEAPINFO: { target_ulong retvals[4]; - target_ulong limit; int i; #ifdef CONFIG_USER_ONLY TaskState *ts = cs->opaque; + target_ulong limit; #else - target_ulong rambase = common_semi_rambase(cs); + LayoutInfo info = common_semi_find_bases(cs); #endif GET_ARG(0); @@ -1201,12 +1205,15 @@ target_ulong do_common_semihosting(CPUState *cs) retvals[2] = ts->stack_base; retvals[3] = 0; /* Stack limit. */ #else - limit = current_machine->ram_size; - /* TODO: Make this use the limit of the loaded application. */ - retvals[0] = rambase + limit / 2; - retvals[1] = rambase + limit; - retvals[2] = rambase + limit; /* Stack base */ - retvals[3] = rambase; /* Stack limit. */ + /* + * Reporting 0 indicates we couldn't calculate the real + * values which should force most software to fall back to + * using information it has. + */ + retvals[0] = info.heapbase; /* Heap Base */ + retvals[1] = info.heaplimit; /* Heap Limit */ + retvals[2] = info.heaplimit; /* Stack base */ + retvals[3] = info.heapbase; /* Stack limit. */ #endif for (i = 0; i < ARRAY_SIZE(retvals); i++) { From patchwork Thu Feb 10 11:30:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 541433 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp2153091imo; Thu, 10 Feb 2022 03:41:29 -0800 (PST) X-Google-Smtp-Source: ABdhPJz6k+swKoddH9yyhQ6aZTBQKJ7UMidsPJqbbGExX5U3LoyozwR7A5I4ZqGz/4e89FMcqMtu X-Received: by 2002:a81:af23:: with SMTP id n35mr6695074ywh.51.1644493288981; Thu, 10 Feb 2022 03:41:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644493288; cv=none; d=google.com; s=arc-20160816; b=AQuQzuneO90mA0Z8BTTtZe8y9worefKvOtcQ4uOPMm0IdQkShVl9zIObXZ/ZbOgYOV tPSWTdakdUtamIQA1S1urFw2hhNEOP0VEB0mp5QiGdM2dcVwiIn48useHlLcEAYmW/CH kWqidWcSiWVYyTREIjYleTRxJw2WudX8O7ssmaJ41q8w7PRpPLAw8VbxfouXLMY554mu G+GCYgVRXGOkgoX3KzcueXuxmQcQiMvKe+Lr48rU/XvlcI5eyQnueRP4V11J2XLd5kS7 91s4bpcC5oAp81+ha8oUG7UVZkiAqWs9AS23zdyu5bwkE2MCIAIjiIYGhhyFDduVRCdb sNsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9qy7IV48skw6PiK32u8+FO1zaKIr1zsoKUR1tPCSI0c=; b=YMkCjRr9PBOZaLOrdFtSWigsoVo2je+fYESU0ed+5kIqLbcFPV7GujLuFTYcybI9l1 kXt/Hhx7mOgHSwViZAqXFCxjN746lB/F/gV5A9t3gQpPwcbP5IK8LluLKNuXdR4HzKEE +W4L7jxg3QMlsovEIXb4p6kHm/X2NsUOcqWIMWQOJrbeeJybmzs8VctoZxaCnaAoJN0q GsvcaQDET4JAQoqSW3Pd8jTsaviX1OKvoLCm6wChrul2izpjZsmbIOOuun+znXVLIQO2 MWnFl63lkhINYb+C//q5lINeumz+smwegxdpXVAi/qltetMiwvQoQPFauCiRh3Ji+10q T+nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wVmNAdBG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d22si10106275yba.802.2022.02.10.03.41.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Feb 2022 03:41:28 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wVmNAdBG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43626 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nI7pI-00053K-FF for patch@linaro.org; Thu, 10 Feb 2022 06:41:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:42400) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nI7ef-0003ie-FI for qemu-devel@nongnu.org; Thu, 10 Feb 2022 06:30:32 -0500 Received: from [2a00:1450:4864:20::629] (port=45584 helo=mail-ej1-x629.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nI7ed-0002Vp-5O for qemu-devel@nongnu.org; Thu, 10 Feb 2022 06:30:29 -0500 Received: by mail-ej1-x629.google.com with SMTP id s21so14365260ejx.12 for ; Thu, 10 Feb 2022 03:30:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9qy7IV48skw6PiK32u8+FO1zaKIr1zsoKUR1tPCSI0c=; b=wVmNAdBG53HscQ0hYgt7SAJbb4aIflYY8gWqyGKt4d2ZpkFLsRK3NMoswRZanLHMGE gCytAEagVH+Bn2mykwZjtPL/DHRdA0uYjODktv+2gzleeJWs307QGicWIkeWad3/Sseu pWUx2fgq6QtKRLR7VwmwZJNrHLt0bektrPzWno9ddPcGY1QrcswLgs9M0H429CcEKPta uLRnVrXkxojsiid9ACIfsqi9qoQDLlOVogZWv9t4CvHNe84G7AWJP83ndE/ie7oDTXX1 GRHK2+PNqVcBOHpbkbmMaRNrNkoj6p0/EpqUGp74LMdhATvxPZQKOxQfH7M8V0ojnyai 6+DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9qy7IV48skw6PiK32u8+FO1zaKIr1zsoKUR1tPCSI0c=; b=2xDQ++0LsgdsmtRmNOJnQ8UogTTwHzqtmGbpzulE8i2tEUtUFQkYRtLliRX28S1oC7 QqNKQRRUWFvOUV08k2d7IKS6GA03Yr92cCObyHq1NNCMzrbw7Ua7Avn/OmoFTfEa2gj9 0nrRVMZBZqEISsuDTnmyRhSG0ZvxlbgVvoufr6YYz8QhEtZ2Q5LvCpe5ZrSkzi0c+nst ILyprRnRe1GIRx3KaelAiyBZqKrZtefF5du6NMkcr7kLCiShrtzjPe8oW94vCoHe2fca 9iWMX5B2gauCaMuebCU6FUmq/P9BkmtUiEQe9eNt75clZCve4lk1AoXXJ3MWA3SGJzKO QT6g== X-Gm-Message-State: AOAM5305T6M21wqOQK81hbbk9zAYcV86XFDoaXNVWtLDhtFzBjQk+i1w t6QIdaZnczJqBLuVbriPuZtBWA== X-Received: by 2002:a17:907:7207:: with SMTP id dr7mr5965867ejc.500.1644492625806; Thu, 10 Feb 2022 03:30:25 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id ku15sm5624043ejc.25.2022.02.10.03.30.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Feb 2022 03:30:22 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id B81B91FFBA; Thu, 10 Feb 2022 11:30:21 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v5 2/2] tests/tcg: port SYS_HEAPINFO to a system test Date: Thu, 10 Feb 2022 11:30:21 +0000 Message-Id: <20220210113021.3799514-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220210113021.3799514-1-alex.bennee@linaro.org> References: <20220210113021.3799514-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::629 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This allows us to check our new SYS_HEAPINFO implementation generates sane values. Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell --- v5 - static init of heapinfo structure - clean-up comment on why we can test stack position - add memory clobber for semicall - test we can read/write to a portion of the heap - fix MAINTAINERS --- tests/tcg/aarch64/system/semiheap.c | 93 +++++++++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 94 insertions(+) create mode 100644 tests/tcg/aarch64/system/semiheap.c diff --git a/tests/tcg/aarch64/system/semiheap.c b/tests/tcg/aarch64/system/semiheap.c new file mode 100644 index 0000000000..4ed258476d --- /dev/null +++ b/tests/tcg/aarch64/system/semiheap.c @@ -0,0 +1,93 @@ +/* + * Semihosting System HEAPINFO Test + * + * Copyright (c) 2021 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include + +#define SYS_HEAPINFO 0x16 + +uintptr_t __semi_call(uintptr_t type, uintptr_t arg0) +{ + register uintptr_t t asm("x0") = type; + register uintptr_t a0 asm("x1") = arg0; + asm("hlt 0xf000" + : "=r" (t) + : "r" (t), "r" (a0) + : "memory" ); + + return t; +} + +int main(int argc, char *argv[argc]) +{ + struct { + void *heap_base; + void *heap_limit; + void *stack_base; + void *stack_limit; + } info = { }; + void *ptr_to_info = (void *) &info; + uint32_t *ptr_to_heap; + int i; + + ml_printf("Semihosting Heap Info Test\n"); + + __semi_call(SYS_HEAPINFO, (uintptr_t) &ptr_to_info); + + if (info.heap_base == NULL || info.heap_limit == NULL) { + ml_printf("null heap: %p -> %p\n", info.heap_base, info.heap_limit); + return -1; + } + + /* Error if heap base is above limit */ + if ((uintptr_t) info.heap_base >= (uintptr_t) info.heap_limit) { + ml_printf("heap base %p >= heap_limit %p\n", + info.heap_base, info.heap_limit); + return -2; + } + + if (info.stack_base == NULL) { + ml_printf("null stack: %p -> %p\n", info.stack_base, info.stack_limit); + return -3; + } + + /* + * boot.S put our stack somewhere inside the data segment of the + * ELF file, and we know that SYS_HEAPINFO won't pick a range + * that overlaps with part of a loaded ELF file. So the info + * struct (on the stack) should not be inside the reported heap. + */ + if (ptr_to_info > info.heap_base && ptr_to_info < info.heap_limit) { + ml_printf("info appears to be inside the heap: %p in %p:%p\n", + ptr_to_info, info.heap_base, info.heap_limit); + return -4; + } + + ml_printf("heap: %p -> %p\n", info.heap_base, info.heap_limit); + ml_printf("stack: %p <- %p\n", info.stack_limit, info.stack_base); + + /* finally can we read/write the heap */ + ptr_to_heap = (uint32_t *) info.heap_base; + for (i = 0; i < 512; i++) { + *ptr_to_heap++ = i; + } + ptr_to_heap = (uint32_t *) info.heap_base; + for (i = 0; i < 512; i++) { + uint32_t tmp = *ptr_to_heap; + if (tmp != i) { + ml_printf("unexpected value in heap: %d @ %p", tmp, ptr_to_heap); + return -5; + } + ptr_to_heap++; + } + ml_printf("r/w to heap upto %p\n", ptr_to_heap); + + ml_printf("Passed HeapInfo checks\n"); + return 0; +} diff --git a/MAINTAINERS b/MAINTAINERS index b0b845f445..251f96af9e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3536,6 +3536,7 @@ S: Maintained F: semihosting/ F: include/semihosting/ F: tests/tcg/multiarch/arm-compat-semi/ +F: tests/tcg/aarch64/system/semiheap.c Multi-process QEMU M: Elena Ufimtseva