From patchwork Thu Feb 10 04:04:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 541371 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp1921917imo; Wed, 9 Feb 2022 20:08:24 -0800 (PST) X-Google-Smtp-Source: ABdhPJxi9IVPGTgdEwex28vUqRC6IhsXxjHEnTkPKrDs3omLKpu9Xm4YlpkNmTKPwgQtgmN3ebVB X-Received: by 2002:a81:b289:: with SMTP id q131mr5213869ywh.494.1644466103889; Wed, 09 Feb 2022 20:08:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644466103; cv=none; d=google.com; s=arc-20160816; b=qQbiFNhSyRCfrvb66qj9ojDLq6E6ppnugLtaW6Z3VgUq6FTRlKxaV7wNOjRoQJbVCh UXuTRXMmqDsvvAA4aIsWQcn/BtQO+lOJCqGI4ei+I3lCnjRrdscsfgNPtocsR/Z+zkoE WWtdaid+OirLoW2n4Sftc93omBce0amuqEHZIVfrggiA2aYh+EnnG1C6vE/9MXntxqBU hMstvtEM3gdai0yTIqUiLpgvM9+A8HTnc327OQN7Jvkp/+TmsJk4uGtIXPJeKmEWmnvj dkFj7ae6mSoRJYR7b7I7mYYI1DBOq6gtAxRDkiYmTzVzBaoDXBP6+A6GjJa4o2MhpxMe AiBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AwzX6nehTYEJJpMljDUaZpO2r34jA4Ju646jiPXQlwk=; b=bXk8rHvVjIq8WXg8bh6KnlOOdGcj6TlNcpdeCxs+NlDC+gGYZHwLmtYlfZGKFRu248 B9wBweGXLYNMFwAWrYMx+tKApnYYfMdkpY52/VPqai0l1aWHsHmh4ZHOZWkNiX4yW6e2 BJwjQChH9pRCod93kszjOpwflaDRW31YKLDKO4N2dLJhTBXO08Q949TkYLHc7eGjlvHD OL8YBk6234g2stpQLj0UA0ndf+mjWn+zTmJRr1VStvgd1QpGkeRszv/mmeHhivXts1fG GVJ6FkCqFiv6idGx1FeRyi1FOB3/ggguxA+bUitcQN6ljG+lE7EbRE1950R0JLNhm3vJ y/TQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fxoubPLN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z12si9729553ywz.417.2022.02.09.20.08.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Feb 2022 20:08:23 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fxoubPLN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nI0kp-0003vo-99 for patch@linaro.org; Wed, 09 Feb 2022 23:08:23 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53948) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nI0hE-0003uD-0V for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:04:40 -0500 Received: from [2607:f8b0:4864:20::636] (port=38788 helo=mail-pl1-x636.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nI0hB-00045r-02 for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:04:38 -0500 Received: by mail-pl1-x636.google.com with SMTP id c3so747255pls.5 for ; Wed, 09 Feb 2022 20:04:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AwzX6nehTYEJJpMljDUaZpO2r34jA4Ju646jiPXQlwk=; b=fxoubPLNEogn+zHRnWFJWC+02DY723o0fq2mD8X6E2s1xgD8o6Q8a3eI/T8JVd8rtq 9ZT1LBBeJTKrH1XeHWmzn1q/QJX9IjQMkZlmav6rW0XnrofDTCUk/+Ck5IJm94cA6Gsg SDBBWqh9qQ9RgT+ewtFxdOk4c1Grp9f4tLZH9kDGC4660fg89EMBZNgkruKqmyL8rTIe Z1RkqS2X/006oeS+5XAXAivHdihTmQYjNZpGtW9FdDsJjUJDasBgtgXhzbNUUW8L0wxY lo4wUWS2/Pa6s2PHUsTMGCJIDeoQLm/Am+lDVd2VJY6vQs7Vi2VAIe0cMqOQO+yIEPkq uL8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AwzX6nehTYEJJpMljDUaZpO2r34jA4Ju646jiPXQlwk=; b=4BlxNNrOe4T1LXYha8wUgwUwKKDf4z752WxHlvPqODpqRTBJB4gW3ADtyzx/1mJITF Jnb8lvVYS6USqPrYq8YpqToYEke8Rw7lTCTPtEA8WZSiG5FhEtd6sAjDxzubJSXuIlbC 3xoYM3VtXycguHi+FUY9cVQiWXOB6VsWXBJTkQhlwsu10fAEICzNkYveEveIk4YW24a7 bcMLWT0borRRQhWKG/nlvoBvaZ74o5jhNY1Gzm0q296H1YAvw8H0REPLno1VhJuJ9azd e/slruz8SNs1vQWs75E+NyzLVC+rrrkUTLFyehvbmFoPGM/5HgRPfcEsY31H04uwohN3 /9GA== X-Gm-Message-State: AOAM533hwFxq3037Eyz2C2USm9R1mDzhENRjmusJS58XHe2QnZWRqgWQ lBPjGksyNdxRdVnFfEMMbkebSfGVzai8J1oh X-Received: by 2002:a17:90b:2243:: with SMTP id hk3mr750212pjb.244.1644465875665; Wed, 09 Feb 2022 20:04:35 -0800 (PST) Received: from localhost.localdomain ([124.189.222.164]) by smtp.gmail.com with ESMTPSA id y4sm9749814pgp.5.2022.02.09.20.04.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Feb 2022 20:04:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 01/15] hw/registerfields: Add FIELD_SEX and FIELD_SDP Date: Thu, 10 Feb 2022 15:04:09 +1100 Message-Id: <20220210040423.95120-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210040423.95120-1-richard.henderson@linaro.org> References: <20220210040423.95120-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::636 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add new macros to manipulate signed fields within the register. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/hw/registerfields.h | 48 ++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index f2a3c9c41f..3a88e135d0 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -59,6 +59,19 @@ extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_SEX8(storage, reg, field) \ + sextract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_SEX16(storage, reg, field) \ + sextract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_SEX32(storage, reg, field) \ + sextract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_SEX64(storage, reg, field) \ + sextract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) + /* Extract a field from an array of registers */ #define ARRAY_FIELD_EX32(regs, reg, field) \ FIELD_EX32((regs)[R_ ## reg], reg, field) @@ -95,7 +108,40 @@ _d; }) #define FIELD_DP64(storage, reg, field, val) ({ \ struct { \ - uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \ + uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \ + } _v = { .v = val }; \ + uint64_t _d; \ + _d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ + _d; }) + +#define FIELD_SDP8(storage, reg, field, val) ({ \ + struct { \ + signed int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } _v = { .v = val }; \ + uint8_t _d; \ + _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ + _d; }) +#define FIELD_SDP16(storage, reg, field, val) ({ \ + struct { \ + signed int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } _v = { .v = val }; \ + uint16_t _d; \ + _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ + _d; }) +#define FIELD_SDP32(storage, reg, field, val) ({ \ + struct { \ + signed int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } _v = { .v = val }; \ + uint32_t _d; \ + _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ + _d; }) +#define FIELD_SDP64(storage, reg, field, val) ({ \ + struct { \ + int64_t v:R_ ## reg ## _ ## field ## _LENGTH; \ } _v = { .v = val }; \ uint64_t _d; \ _d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ From patchwork Thu Feb 10 04:04:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 541372 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp1921966imo; Wed, 9 Feb 2022 20:08:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJxSsu9Q5Fw4EcY4XPDx119WYLaI70IkprjtuJPMIFPQ9SMcNnjwNIbFL0H4PKOOF6bbjogT X-Received: by 2002:a81:354f:: with SMTP id c76mr5613910ywa.309.1644466108648; Wed, 09 Feb 2022 20:08:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644466108; cv=none; d=google.com; s=arc-20160816; b=t04YdnDlYBGJ9XKgoRXnFk/evOKuthRcD+yg7GCJmwLr+dJ1yKv/vzeb/FTQkgwIv3 +C1o/sF4Zu6/uIAhCBaUIZtsgBogKB6VXXuXSY5y/9giUGmoa3dqxxP8Cg+hW1RuPNB5 KQeK75mTgwgtFAyLSv/K7U4Mf2JsIwtLizx6OMG1VWgo+pzPJn5O972MacZi/kqwCigC RIPxK1McLWDFUu048O42rM4YwzNECAc3052mJq6jf2SOPpIF3+l0X4rAkEQiky7ijHCU XN8wyj8k7RAiUvQgE2ians7Z/jTCZ55mgccaWQ3WSaDCMCDtcW1QNzOownmZygz+aKOX 31pA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6GEKuSQX+CG8gt0Gp9cWbbYI/Mw1WHwT/DCHRQdQ0Wo=; b=rHbTuCHIyxTpxPKZoVnWFQSTei6Z2Sa1WiV0YNz2+PsfxiU4Pxs5KlFs/IiT+2bLmy JKIlIPhg+MQhWlBBSZvmqxSvlxcoXTCs1mjPYYMWRh4zGgMUNWiYTnRWRaO57caRQwzc 6+IzCfkHvNWPgO4cm47jQ36xQyLbZrws64YfVvmE1n+0CLFufqTY2XpKliXdun4BmzCi RVkDrC8Kej67n9Nkh3tRxqYQ68u7eqr8MRNwC6u9ZXbWYGhaw3z6Bk/KNBU6cviqVE3U YokJlm1aZXNetAlNVHeezy4O5w0yqVbj0ZqqW6h1WbGUtdSdu2qBRXuTmURWPNcBs9v+ 2LnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=C0+Zc979; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v17si4573194ybm.822.2022.02.09.20.08.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Feb 2022 20:08:28 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=C0+Zc979; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nI0kt-0003wz-Qd for patch@linaro.org; Wed, 09 Feb 2022 23:08:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nI0hG-0003uh-Dt for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:04:42 -0500 Received: from [2607:f8b0:4864:20::62b] (port=38778 helo=mail-pl1-x62b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nI0hE-00046X-CK for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:04:42 -0500 Received: by mail-pl1-x62b.google.com with SMTP id c3so747323pls.5 for ; Wed, 09 Feb 2022 20:04:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6GEKuSQX+CG8gt0Gp9cWbbYI/Mw1WHwT/DCHRQdQ0Wo=; b=C0+Zc979DKm0HtHVIYzphg2iahc5MEGH3giJcDjotVxWiX9WGysmtfpqykIAhJDNqL C6By6zaYx2M5lThzs4F9vLKkudL+HbEvbJB1cZ71+xPRacDan+RLcksfYKa3wkk/T2NF bN3wtfc7hgQtYW19Hea2WUF5y3wEYztDsrZnYHD4zxnqq7FUU4OfK0HBCNCZR2sbqnyf xos1qUn2DKUmsjRenneyiOO4CGbbd/cQhmtnv9os6quloGLDsrZ+8xkIvzmHXCOXAtTB tLcYfP/7TB4ItpRyh0FB6Bf7hRJFqR0On5ZLHIq+Fob8y+m/VNlxw7FParuRUi9JpOhF BdKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6GEKuSQX+CG8gt0Gp9cWbbYI/Mw1WHwT/DCHRQdQ0Wo=; b=JKqYW8Bsfb5tV87JtrfRTBBsKCAE4QQoJ6Udns7VGcBrjtNBRNqN1j4C4OwM1Mozkf U/FJxkoZmSbRltY5X3dSwui/lJh3Tt45MWFiNfwbzJs90SfUYQsLvyIzdWlA8XtJQYua vKQk2Ufe2iaTFM6jVT48w6utlL5ZpsmY90NdmRFZNmlOTf5MN7BhqoZdqqVDc7PoDarH epCD1q5T6L8okMn8/yoArlEJgQniaDuvS3A8d/M5LMsP1dtsNl7t3cf8/5VCEnDHWmKY z+X+AmUlUCxhnBAcRM7spyN5AvJiX/5uDtGVFxEEO4/8Rq82NFvMGk330ylnGl0u7gvn 0dlg== X-Gm-Message-State: AOAM533qknUkEKsw6C0A0mGeUvlU7v9Cl1x5TMZ0TUHKzqbkrADVApZS VbsHymgVNAx0bGpE3v8hPCddkfxTpvr4g4QP X-Received: by 2002:a17:902:ccc2:: with SMTP id z2mr5498369ple.145.1644465878436; Wed, 09 Feb 2022 20:04:38 -0800 (PST) Received: from localhost.localdomain ([124.189.222.164]) by smtp.gmail.com with ESMTPSA id y4sm9749814pgp.5.2022.02.09.20.04.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Feb 2022 20:04:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 02/15] target/arm: Set TCR_EL1.TSZ for user-only Date: Thu, 10 Feb 2022 15:04:10 +1100 Message-Id: <20220210040423.95120-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210040423.95120-1-richard.henderson@linaro.org> References: <20220210040423.95120-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Set this as the kernel would, to 48 bits, to keep the computation of the address space correct for PAuth. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5a9c02a256..92f19f919a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -206,10 +206,11 @@ static void arm_cpu_reset(DeviceState *dev) aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); } /* + * Enable 48-bit address space (TODO: take reserved_va into account). * Enable TBI0 but not TBI1. * Note that this must match useronly_clean_ptr. */ - env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); + env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); /* Enable MTE */ if (cpu_isar_feature(aa64_mte, cpu)) { From patchwork Thu Feb 10 04:04:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 541376 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp1924233imo; Wed, 9 Feb 2022 20:13:02 -0800 (PST) X-Google-Smtp-Source: ABdhPJx8tpxjgS817Lry50pqO08R/0wS3uL/GWxRsbQvhJ+G2W3JPrw3pPCU/i2xeWqsHw+I+DW+ X-Received: by 2002:a25:37cf:: with SMTP id e198mr5312564yba.697.1644466381941; Wed, 09 Feb 2022 20:13:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644466381; cv=none; d=google.com; s=arc-20160816; b=QzTeljDPazrvCIF9CQRTlxfRMQIrSt8C0IRjNoqY1o5S3q07raK6JZcD8OzQrixZ8A 71aGUVjJ+sHLd2utXS+rIPOZxESAmyP23Eh2uuYMwGet6xbUbsS+DxkusY8GLEAABgot cDV9WSR13OWjOhzkcL0mrx7d8m27E0DuEvyxZJmGDKcmr3+2A8X7/LfmEGP5qKfcMSWw 47TxxGMYDLWmFFtd79p7/dvqi4RehsygfwKrcEJ6i02LNsY/ipu7Sf0sF98G839ChlzL m66uJT3xCltKzdFp4hwvP9Mk3txbfkQWKpOfStTDfRGALcIe0vH8OhiGt/jfmumyHINs FtSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=M9yoHlP5X1aUjQ5+XqVVCuvodgZ7D3QrARDveNRnzPE=; b=AS4eW7hcV/ur9Ns4yYkTTuMHznLxBAkc233r27qV7fMSFKnRRVoEYSGZTRICXY7Lk5 0YZM9iE0LHhctiw5htX37LoG8MLRjEGfW7PBhm6pgKOW1xbWk4KiMKrSQ6rDVGkgfyH6 jaTf6ECdUyoJ/1h+/YJIYvkpBTQxx1f14TtW3l6jGWeQIiDSomPuImCTTDcSatxhZxFf 7qzh5yT/BTmW6CFFT0eVqdkv+V3Qm5zCF1Zjn3zlFjq6yzOiJp6TzvZMpMf4/xxXU7fD 4UHjEKpun2HsnwUYHDz//CNGJyRxiFLLfs6PE7Dw5NvQJuZIIRRwpv3w6NGcrljMcEHZ hlMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vf+owxys; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d184si8790157ybh.295.2022.02.09.20.13.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Feb 2022 20:13:01 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vf+owxys; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nI0pJ-000419-E0 for patch@linaro.org; Wed, 09 Feb 2022 23:13:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nI0hK-0003vm-5F for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:04:46 -0500 Received: from [2607:f8b0:4864:20::432] (port=34383 helo=mail-pf1-x432.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nI0hI-000471-9q for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:04:45 -0500 Received: by mail-pf1-x432.google.com with SMTP id n23so8041439pfo.1 for ; Wed, 09 Feb 2022 20:04:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M9yoHlP5X1aUjQ5+XqVVCuvodgZ7D3QrARDveNRnzPE=; b=vf+owxysXq1AM8pznsPiJhfGf5bzg13BCYLoIW72rwX1LVmWb6NA8lfNEOVK8S8LfU hBq4Q6BEi+wzv+dYGJ+gAnYw12glXMpkRhrp/W4BqQllWoCzgj29AyU0H/ShS0OKJ9La d+2hqdHAwFq4bIqK6jeKpW5ZYOMsaOzPEVm8oIQpjF1i40DNInxKTxnIr4IJsxjB1von vCNJwPdHfU/AFWfF/ufjNOE1ps18kLYH99FY6YOnTFrHieAxoapVux2nHeehYem5GmG9 FYCChhUaHgRniVdzSp6AN5zuntC91PBvEWDp9UkdhIyyynPmXuLau562rN9thkPi+CGe UUPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M9yoHlP5X1aUjQ5+XqVVCuvodgZ7D3QrARDveNRnzPE=; b=fCX/jig1OpXovcX19jzSaAXb17J7OWZBbjkq67DQlU+fsDvJPiCv3C8JjddrL/A8Yq VXg7g/nl+Cdb8+9I+S4qloJLMMN4PpVXH6NJ92dtL+XX32kjECqH4YfgdPuQeyWTtvBY 6pC2pZfXLeun3pA6H96xFuU/bfjJ1ffEz1v798rr1kWntWalMcLC3pkKEC89zDwTCL9C DCKJVf2btmDgqUzkDU6im0rV/ieISOnODZLr1Do+bDZBP2pJfWUeo+ceoUPUkcl1DE8a JMlyqnwzpj+qLaCjpugEfIvWrcNTqNE8biKf/GT4PVraG/PHhhfu30g1SG34ggA8m34B lyLA== X-Gm-Message-State: AOAM5310bai82Z4c4QkxSBFxpNpUd3q3Mn3uZ/mjxHgfebw5dzgAM1DV KvtiKU69bG6uqJWLzM0OSoUCVe5ER9siqexY X-Received: by 2002:a05:6a00:98e:: with SMTP id u14mr5590601pfg.12.1644465881227; Wed, 09 Feb 2022 20:04:41 -0800 (PST) Received: from localhost.localdomain ([124.189.222.164]) by smtp.gmail.com with ESMTPSA id y4sm9749814pgp.5.2022.02.09.20.04.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Feb 2022 20:04:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/15] target/arm: Fault on invalid TCR_ELx.TxSZ Date: Thu, 10 Feb 2022 15:04:11 +1100 Message-Id: <20220210040423.95120-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210040423.95120-1-richard.henderson@linaro.org> References: <20220210040423.95120-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::432 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Without FEAT_LVA, the behaviour of programming an invalid value is IMPLEMENTATION DEFINED. With FEAT_LVA, programming an invalid minimum value requires a Translation fault. It is most self-consistent to choose to generate the fault always. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Continue to bound in aa64_va_parameters, so that PAuth gets something it can use, but provide a flag for get_phys_addr_lpae to raise a fault. --- target/arm/internals.h | 1 + target/arm/helper.c | 32 ++++++++++++++++++++++++++++---- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3f05748ea4..ef6c25d8cb 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1055,6 +1055,7 @@ typedef struct ARMVAParameters { bool hpd : 1; bool using16k : 1; bool using64k : 1; + bool tsz_oob : 1; /* tsz has been clamped to legal range */ } ARMVAParameters; ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, diff --git a/target/arm/helper.c b/target/arm/helper.c index b5f80988c9..14cc866d8d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11188,8 +11188,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; - bool epd, hpd, using16k, using64k; - int select, tsz, tbi, max_tsz; + bool epd, hpd, using16k, using64k, tsz_oob; + int select, tsz, tbi, max_tsz, min_tsz; if (!regime_has_2_ranges(mmu_idx)) { select = 0; @@ -11230,9 +11230,17 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, } else { max_tsz = 39; } + min_tsz = 16; /* TODO: ARMv8.2-LVA */ - tsz = MIN(tsz, max_tsz); - tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ + if (tsz > max_tsz) { + tsz = max_tsz; + tsz_oob = true; + } else if (tsz < min_tsz) { + tsz = min_tsz; + tsz_oob = true; + } else { + tsz_oob = false; + } /* Present TBI as a composite with TBID. */ tbi = aa64_va_parameter_tbi(tcr, mmu_idx); @@ -11249,6 +11257,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, .hpd = hpd, .using16k = using16k, .using64k = using64k, + .tsz_oob = tsz_oob, }; } @@ -11372,6 +11381,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, param = aa64_va_parameters(env, address, mmu_idx, access_type != MMU_INST_FETCH); level = 0; + + /* + * If TxSZ is programmed to a value larger than the maximum, + * or smaller than the effective minimum, it is IMPLEMENTATION + * DEFINED whether we behave as if the field were programmed + * within bounds, or if a level 0 Translation fault is generated. + * + * With FEAT_LVA, fault on less than minimum becomes required, + * so our choice is to always raise the fault. + */ + if (param.tsz_oob) { + fault_type = ARMFault_Translation; + goto do_fault; + } + addrsize = 64 - 8 * param.tbi; inputsize = 64 - param.tsz; } else { From patchwork Thu Feb 10 04:04:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 541374 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp1923917imo; Wed, 9 Feb 2022 20:12:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJzbc+lhaiHcgF2f3v6j3TwcZqjR42093AvKjUHvisc6fzIJ1OaqyUFNVW9yYSF43ROZ9APV X-Received: by 2002:a25:d9c2:: with SMTP id q185mr5212827ybg.134.1644466334126; Wed, 09 Feb 2022 20:12:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644466334; cv=none; d=google.com; s=arc-20160816; b=IxBvltg3XSNOZhgtdYJHtCgIfWmUBcYdbILIAmtifjmjmpnBbsMuP94ION8wuGB+Sk 7mtdsTDDik1dAt0eHo40pcxV4MxJNWdELWSAnMzCttG3yxlycj5ejrxoUpgS6gkG3t/E oAa8cjIz7qZVoWkSkP1gjfOaGM3PnAToQ6VLUSqsosHWXlJGlvAZgG7RlOhjV2EK7479 tPUM3IOlgtbvRxx0Hi38mjCSkscw/UZde4fobL0BRGhW0IOk4XTrG9D2c5LFuQcr8a2D VajZLmPGm0Nn5tUMWs9hz4c/sqFD/LFf/3Y6t/odvNNGQKTSlnH0frJzKkmIOKmuPnye 7zBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hrRLKIw2UploLh3OYXeRorBfG35Au7O6BtUh3Pw46MI=; b=FrsYfwl5Nk+ui0DlLpD2pe0nkW2DEimFXoHiDoDmwWqjSVWR8nAyjWuixaJT4rNVie ihEg/Hn91UFQXAo9ltZgPqt+Dd3LKZOyK9LT5FZnpinD2ggQUahRYo8EnIYPQjS+P4ot m0q54UwlZbI08UCds/KvXNZM3H8erSf7kApYBh1SwkvFsQk5Sx+hXq2lmddfoGlsoGGo gldNEbp0cfjn2PylcCcjjy4whxMarzkyjvrNCkg+1s9diT5U1NIpbqjC80zktZ4h9+Aj qGAePUxWI32xp7k+wpt+Ja+semfjQaZJ/qcwwEraL1i3kIDmK+KISTTU11JQWFyocF27 J5NQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iBi1wrg4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c201si7831261ywa.249.2022.02.09.20.12.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Feb 2022 20:12:14 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iBi1wrg4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nI0oX-0002O9-Io for patch@linaro.org; Wed, 09 Feb 2022 23:12:13 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54048) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nI0hL-0003wa-B4 for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:04:48 -0500 Received: from [2607:f8b0:4864:20::42a] (port=41983 helo=mail-pf1-x42a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nI0hJ-00047B-K7 for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:04:47 -0500 Received: by mail-pf1-x42a.google.com with SMTP id i30so7963318pfk.8 for ; Wed, 09 Feb 2022 20:04:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hrRLKIw2UploLh3OYXeRorBfG35Au7O6BtUh3Pw46MI=; b=iBi1wrg4DQGv4B7r5taPRZ3/8W1VV57B/vUAAX7NvlrYXf1bLUL0cbPuJG7r8el9ov vvgcD4IdYSqeUPKWnRfXEsOaK5zNFQ5jgCEzjNyDVRxHs1D2VS01qfIbAeR6C20uNnSH XZNI9jsspQIPNebsQ38OCtGpwCs6oIZ83aybixWk5DlqJQBI5mqMrQILt/vuOgwQbRAM nBZQ8o9oUY/TSHsvldrfKhdlOOQlqjLSaMGgjfcTou8htfMwIl+0ZO5uCDHc8ndmUpu/ 4wacc4u5PUQ9+VekUMCybTZqhnqvbiQ931tM39Bh89U/HZwV8TOOMxAdnquP+nCDe1vL 30Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hrRLKIw2UploLh3OYXeRorBfG35Au7O6BtUh3Pw46MI=; b=rtFchY7SRUHGguh8g56LGLAEHLPIfBUNtneHygZ/22LqpMWODuH72T89baiBdts9lt QUXorjmyS4XwZAGxZoxN2FlABHTgM+qALrwGN936B9kdUI0VgRLniox5WfeaWGngiseh UBG3E4yTJS11xvRMZvG4epvTIFKSE6VEBUgqrwOSVH/NTlmxr53f6VH3AVPAjJvCJUYt kzVu+E5en/BrvPL6vEEsSoKBuhqZr692l5Li2MveyXuCo2x+CigVvGJz08UPe3q6hCq0 kEW35kIQIkliwz+G6L72J4hw6mxnfqq5VZomsijvHuDAVSRPAUYzQJ/oVtLjUS6D9Y0r pYoA== X-Gm-Message-State: AOAM533luGRSxInVQCI64ULeP6LKuldknlHYV7ENNcqsA0pbafA485jz lq65gsMkl0A4qCnFfI++uVGXlcyZ8fnyFmNi X-Received: by 2002:a62:b618:: with SMTP id j24mr5792829pff.42.1644465884304; Wed, 09 Feb 2022 20:04:44 -0800 (PST) Received: from localhost.localdomain ([124.189.222.164]) by smtp.gmail.com with ESMTPSA id y4sm9749814pgp.5.2022.02.09.20.04.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Feb 2022 20:04:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 04/15] target/arm: Move arm_pamax out of line Date: Thu, 10 Feb 2022 15:04:12 +1100 Message-Id: <20220210040423.95120-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210040423.95120-1-richard.henderson@linaro.org> References: <20220210040423.95120-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will shortly share parts of this function with other portions of address translation. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 19 +------------------ target/arm/helper.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 18 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index ef6c25d8cb..fefd1fb8d8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -243,24 +243,7 @@ static inline void update_spsel(CPUARMState *env, uint32_t imm) * Returns the implementation defined bit-width of physical addresses. * The ARMv8 reference manuals refer to this as PAMax(). */ -static inline unsigned int arm_pamax(ARMCPU *cpu) -{ - static const unsigned int pamax_map[] = { - [0] = 32, - [1] = 36, - [2] = 40, - [3] = 42, - [4] = 44, - [5] = 48, - }; - unsigned int parange = - FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); - - /* id_aa64mmfr0 is a read-only register so values outside of the - * supported mappings can be considered an implementation error. */ - assert(parange < ARRAY_SIZE(pamax_map)); - return pamax_map[parange]; -} +unsigned int arm_pamax(ARMCPU *cpu); /* Return true if extended addresses are enabled. * This is always the case if our translation regime is 64 bit, diff --git a/target/arm/helper.c b/target/arm/helper.c index 14cc866d8d..fa0824e12c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11150,6 +11150,28 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) } #endif /* !CONFIG_USER_ONLY */ +/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ +unsigned int arm_pamax(ARMCPU *cpu) +{ + static const unsigned int pamax_map[] = { + [0] = 32, + [1] = 36, + [2] = 40, + [3] = 42, + [4] = 44, + [5] = 48, + }; + unsigned int parange = + FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + + /* + * id_aa64mmfr0 is a read-only register so values outside of the + * supported mappings can be considered an implementation error. + */ + assert(parange < ARRAY_SIZE(pamax_map)); + return pamax_map[parange]; +} + static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) { if (regime_has_2_ranges(mmu_idx)) { From patchwork Thu Feb 10 04:04:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 541375 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp1924032imo; Wed, 9 Feb 2022 20:12:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJz/28BPXW1XFrQq2AoSAsv7Gxv+gQvx+WSWvw8pG3clEeAmG0FZv8dMZCk+X3xuF7rSEnqe X-Received: by 2002:a5b:dd2:: with SMTP id t18mr5436895ybr.89.1644466352568; Wed, 09 Feb 2022 20:12:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644466352; cv=none; d=google.com; s=arc-20160816; b=PPWY0bHkPoX2PGcsm3EsFmFP1W6/9gNBlFe29GlaeAx4/CaROyQGH63IWg0DB9D0G6 Sf1yUniWu8vPdqhFfDGxZA0SqKxMQW1iFhJJHrTQvTeaC+wTpfsVJh938Txm2iCULcDe WlhKAVf74TGLZAEOCJUksBqcdRIzp7j1BdmHAfE6SG/8C4DkYF71bCMCwvVAg4PyRyKc GQ6AnyPlwR2mgZjgc9rJZUwNPQaIR6Vw+fM3tG2jK9D+nm8eb8MClQwcQGTj/HYUQKDk ndnlH/qG5rE4NTqLpWj5J/StK3d3hB65r9e3e9pjExYf2pQDlvPEaoRP3ylB0Bq6hbF3 TQhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kEVSOi5UkE1IrF02F4h1WkWrzoUBduclFFK91bx08AU=; b=TD9siGQcyU9qLcTgRHebdPCdEOsvZ0WZ7OV7h2djTNId8kLmSGNILS3ivNYlQBU5fe xuJzmNORN8r/2psFR2E1kaVU6S16t9uAO9tGt7GPOu1EW7MgRTC3wOSjcJnfTS4dhqox WJFC955tjjRKvNV2EFZWBDXOB0uhhHrIATf72KDnVJegdSKRkV6IqKm1brokNCv1ae64 PEjv7mfVEYXbhqyLXbm1WzvGlpnpxzd2T50PGj2EeacXLA6iYAgV2WvOAF32zNpWoGi9 pEzUMq1bZlMGaUP8RtN4f64N6K170Cvu1r1KwHI1ZYEluFpePR6yTgdYjqVXyh15H77S gd0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YX6jH+v1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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For now this is still just PAMax, but a subsequent patch will compute the correct value from TCR_ELx.{I}PS. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index fa0824e12c..cf38ebd816 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11063,7 +11063,7 @@ do_fault: * false otherwise. */ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, - int inputsize, int stride) + int inputsize, int stride, int outputsize) { const int grainsize = stride + 3; int startsizecheck; @@ -11079,22 +11079,19 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, } if (is_aa64) { - CPUARMState *env = &cpu->env; - unsigned int pamax = arm_pamax(cpu); - switch (stride) { case 13: /* 64KB Pages. */ - if (level == 0 || (level == 1 && pamax <= 42)) { + if (level == 0 || (level == 1 && outputsize <= 42)) { return false; } break; case 11: /* 16KB Pages. */ - if (level == 0 || (level == 1 && pamax <= 40)) { + if (level == 0 || (level == 1 && outputsize <= 40)) { return false; } break; case 9: /* 4KB Pages. */ - if (level == 0 && pamax <= 42) { + if (level == 0 && outputsize <= 42) { return false; } break; @@ -11103,8 +11100,8 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, } /* Inputsize checks. */ - if (inputsize > pamax && - (arm_el_is_aa64(env, 1) || inputsize > 40)) { + if (inputsize > outputsize && + (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) { /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ return false; } @@ -11390,7 +11387,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, target_ulong page_size; uint32_t attrs; int32_t stride; - int addrsize, inputsize; + int addrsize, inputsize, outputsize; TCR *tcr = regime_tcr(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el = regime_el(env, mmu_idx); @@ -11420,11 +11417,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, addrsize = 64 - 8 * param.tbi; inputsize = 64 - param.tsz; + outputsize = arm_pamax(cpu); } else { param = aa32_va_parameters(env, address, mmu_idx); level = 1; addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32); inputsize = addrsize - param.tsz; + outputsize = 40; } /* @@ -11509,7 +11508,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* Check that the starting level is valid. */ ok = check_s2_mmu_setup(cpu, aarch64, startlevel, - inputsize, stride); + inputsize, stride, outputsize); if (!ok) { fault_type = ARMFault_Translation; goto do_fault; From patchwork Thu Feb 10 04:04:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 541382 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp1926836imo; Wed, 9 Feb 2022 20:19:00 -0800 (PST) X-Google-Smtp-Source: ABdhPJzpYwFtR4mKlVYwpqO0M67sUyoh5vWRo9bxJneOXdogjCIvnwRzKRPPNk+75D7a/hPb6d3J X-Received: by 2002:a25:abf3:: with SMTP id v106mr3845222ybi.76.1644466740521; Wed, 09 Feb 2022 20:19:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644466740; cv=none; d=google.com; s=arc-20160816; b=OW9zG+MD7b+dMcHV4fc3okDG389cfcJcHWzlEBFkeiT6oliFi06wD5rXNe6wNEfIse hQA5/ML0P630ib/iv/reSits7vwRWdytm4WpddULZQTY1den6TSxWx6Dp3IvTdM2MEZx k0x/gm9wPk1Ww5x07tCnUQC+i+GS5XgIOrUBlzz9Hine45dRb5jlWDRMJr6NcMGpEMtN +HKna08N1Wf8q/zu/v2D1bLX45U54R8+gGS6a1iVgjZxbe1ARotErQV8RjMuJyYl3n8P HmJ4hpl8X6YuE4mHTL7xwCFntsI0c1X4hqDaO0JGleQWDxVKyX/31dCjAs7kVkRW8AjX la/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=A0BDFAPkSF6UtdIiOcrkoG8O0FSVru9MSa+YtK3MJG4=; b=zUTg81jPV3SvbKUMEgNFZk6NYKCPQkVGs3i2ow/fFo7OJ2kg+FnGd9DPGUEcfj93uv rNzc9pyyOBF1ADLT6Ve38czkeQK7jDaZFY65WE2+1WZuEvARt8FW00UXyNJM0dFyaOcD rTVQTO9pPKqedVtyYLypWNbxGivbuEZLvHIhJACDtkZMvGL6419HGbkzshT20tRDy/SE MWHfgr/ITPp+jOjKEZfIgJSyr3sgliv6Sl5BHXmmcWwTvGFzypEAQjfnlTuMu4KJ/YMq cJpA8cED+Y8e6m29ZQ+GKJd9ferfUCNHfoUM1wALh8DLysfs0z2kqct81c5KbBx+iX5t OkTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VfVSvp1X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index cf38ebd816..94304804cb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11516,8 +11516,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, level = startlevel; } - indexmask_grainsize = (1ULL << (stride + 3)) - 1; - indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; + indexmask_grainsize = MAKE_64BIT_MASK(0, stride + 3); + indexmask = MAKE_64BIT_MASK(0, inputsize - (stride * (4 - level))); /* Now we can extract the actual base address from the TTBR */ descaddr = extract64(ttbr, 0, 48); From patchwork Thu Feb 10 04:04:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 541380 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp1925690imo; Wed, 9 Feb 2022 20:16:15 -0800 (PST) X-Google-Smtp-Source: ABdhPJz0O8LD4FReQ8vpK+7Mcy5BrHmzOfueDS4ibczpOBMPP/LSuTp77hxJxIp6xZYWs77qG/2f X-Received: by 2002:a81:5684:: with SMTP id k126mr5774303ywb.381.1644466574920; Wed, 09 Feb 2022 20:16:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644466574; cv=none; d=google.com; s=arc-20160816; b=W61te6uAMinAM992NmgrY3fcq31tID5RfoRcqJIIPZtBExB/ipX9XNPE0k8b+9Q1Kd dZRFPnuJO7FKKQ1rBdX6BbD8I8pA1nmfyKmCjabWtNohm34CA2PRWd7sqqfH6lsqXWix XEnGllghGHEvcOVEhDUEYsV3MxRAZB/It2/QizCpJQgnMkMrBf9HqQFl4PQb4QjM9/zD h9qfDDTzN5SJPkHaLKBeZEHASR13imBQRDA4jrBsrEmURvCVVhYoyqNLt6UXkVTt7KkI iBOHW8N+8OZTcjoz2B1PVnYerDApw8IYLN//NGRbd8OiPxNmX7UWmW/wQTK/XUqFnN/E 62Bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9unzvtzWabHumoVo2LIqZ3/KoNmw+Kj3VTUoCLWhgOA=; b=L//R5qkfQHMwtWwXiJUS446zA7RX0qwP/NSZm6Nt+tMbb5rp7W5fOIv14gpJUqcf+g 89ih/6K/LIf06N6lubll1xuchP0hlwx6s6DYga+PRPkkmqd/YOBVKjZIAL6iRCGrHPT6 +P1nT2yDLXmUWvfUfGPFgq1GqkvcUN21ZyvcOKG8PKbDrBudELzmvXKv3ytqY48pQ+wi Yo6uEeu222iqKQICCFHUndtN4+0hPYBSmfKCTdatbX/32kZEUSrIU7JVlDZbq51SMUsz 3PxXbUL2A/g4jkR8umhCTDp9LfgO9wDvF7xCX71wXlP+ovobt/JG797XnZcmdAPyQ62t PtcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=h+JwQgMi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c8si13008212ybf.208.2022.02.09.20.16.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Feb 2022 20:16:14 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=h+JwQgMi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37200 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nI0sQ-0001QV-8V for patch@linaro.org; Wed, 09 Feb 2022 23:16:14 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54144) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nI0hT-000433-Pn for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:04:56 -0500 Received: from [2607:f8b0:4864:20::432] (port=45661 helo=mail-pf1-x432.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nI0hR-00048i-R5 for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:04:55 -0500 Received: by mail-pf1-x432.google.com with SMTP id 9so5101381pfx.12 for ; Wed, 09 Feb 2022 20:04:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9unzvtzWabHumoVo2LIqZ3/KoNmw+Kj3VTUoCLWhgOA=; b=h+JwQgMiCcG0aahhuT+yB0y2quVt3pYL82kcF9qIdsWyERj151UAluYcuY7slyPR8P 8iwdBljIxk6WtBLjUyNb8lR6F6MoOVsrdWqyNq18b0Xw47khaERqTcYJBe5/7tLl1OgM AqekX6lgY3ATMIjohLnuji63vBgZizupHk1lbrmd3hPVD02M55IgENNAsiyvi2iSr0WN HvUILAaa0GwmrJyUk9ceLKja1JuHeXapBNczPqjJL7giGLQtV/Rxelz4RhrXf/a11kGA hyJwBaiXh3JTd8LIbikpfq5HMTmKY0Q1mAbsQkvzIzVJ/RPuSgFdK3MO0JPoqPwOJeaI vt/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9unzvtzWabHumoVo2LIqZ3/KoNmw+Kj3VTUoCLWhgOA=; b=2Ak4g7faoe+yLdfzID6qafFzmWSAjAzli1uMA08Ev0ZIP+VcxGjUyOvCQI635dBH2L vpfUwnvveIBjXQ2MNzHByto5It20FMBhD6rIdepnA+HFn3IxsfQM4h66S74eETjpiU1y 7bozhfyaM41U3iGFsKG1ynywKHvmh+cK0U6RVuojHVzsL5kIPLKlxnxCRXvJNtNaCUbr h482OmZ0ikUZQISgoQ5FFsj5b7wifLESPdwlu1WhYLthDIASbXxbfzaR+NEFtat+SFJM /ay/Bbl9fCVQK7s+rtqBFqo8I9gGMsxtCPjV+gVRHsb9pjrqUD8pdq12AfIwFO0R3hq9 XyAg== X-Gm-Message-State: AOAM531obEdP+9VdczyMTzGUp9PSfuoOYs3x0WBNz+PCdF7PHtvMsEI5 PtyXbnkssv9fbx6rkNg/pdb2pSIOT0WkDalS X-Received: by 2002:a65:66d5:: with SMTP id c21mr701948pgw.152.1644465892535; Wed, 09 Feb 2022 20:04:52 -0800 (PST) Received: from localhost.localdomain ([124.189.222.164]) by smtp.gmail.com with ESMTPSA id y4sm9749814pgp.5.2022.02.09.20.04.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Feb 2022 20:04:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 07/15] target/arm: Honor TCR_ELx.{I}PS Date: Thu, 10 Feb 2022 15:04:15 +1100 Message-Id: <20220210040423.95120-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210040423.95120-1-richard.henderson@linaro.org> References: <20220210040423.95120-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::432 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This field controls the output (intermediate) physical address size of the translation process. V8 requires to raise an AddressSize fault if the page tables are programmed incorrectly, such that any intermediate descriptor address, or the final translated address, is out of range. Add a PS field to ARMVAParameters, and properly compute outputsize in get_phys_addr_lpae. Test the descaddr as extracted from TTBR and from page table entries. Restrict descaddrmask so that we won't raise the fault for v7. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 1 + target/arm/helper.c | 72 ++++++++++++++++++++++++++++++++---------- 2 files changed, 57 insertions(+), 16 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fefd1fb8d8..3d3d41ba2b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1032,6 +1032,7 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) */ typedef struct ARMVAParameters { unsigned tsz : 8; + unsigned ps : 3; unsigned select : 1; bool tbi : 1; bool epd : 1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 94304804cb..015f992f02 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11147,17 +11147,19 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) } #endif /* !CONFIG_USER_ONLY */ +/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ +static const uint8_t pamax_map[] = { + [0] = 32, + [1] = 36, + [2] = 40, + [3] = 42, + [4] = 44, + [5] = 48, +}; + /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ unsigned int arm_pamax(ARMCPU *cpu) { - static const unsigned int pamax_map[] = { - [0] = 32, - [1] = 36, - [2] = 40, - [3] = 42, - [4] = 44, - [5] = 48, - }; unsigned int parange = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); @@ -11208,7 +11210,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; bool epd, hpd, using16k, using64k, tsz_oob; - int select, tsz, tbi, max_tsz, min_tsz; + int select, tsz, tbi, max_tsz, min_tsz, ps; if (!regime_has_2_ranges(mmu_idx)) { select = 0; @@ -11222,6 +11224,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, hpd = extract32(tcr, 24, 1); } epd = false; + ps = extract32(tcr, 16, 3); } else { /* * Bit 55 is always between the two regions, and is canonical for @@ -11242,6 +11245,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, epd = extract32(tcr, 23, 1); hpd = extract64(tcr, 42, 1); } + ps = extract64(tcr, 32, 3); } if (cpu_isar_feature(aa64_st, env_archcpu(env))) { @@ -11270,6 +11274,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, return (ARMVAParameters) { .tsz = tsz, + .ps = ps, .select = select, .tbi = tbi, .epd = epd, @@ -11397,6 +11402,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* TODO: This code does not support shareability levels. */ if (aarch64) { + int ps; + param = aa64_va_parameters(env, address, mmu_idx, access_type != MMU_INST_FETCH); level = 0; @@ -11417,7 +11424,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, addrsize = 64 - 8 * param.tbi; inputsize = 64 - param.tsz; - outputsize = arm_pamax(cpu); + + /* + * Bound PS by PARANGE to find the effective output address size. + * ID_AA64MMFR0 is a read-only register so values outside of the + * supported mappings can be considered an implementation error. + */ + ps = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + ps = MIN(ps, param.ps); + assert(ps < ARRAY_SIZE(pamax_map)); + outputsize = pamax_map[ps]; } else { param = aa32_va_parameters(env, address, mmu_idx); level = 1; @@ -11521,19 +11537,38 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* Now we can extract the actual base address from the TTBR */ descaddr = extract64(ttbr, 0, 48); + + /* + * If the base address is out of range, raise AddressSizeFault. + * In the pseudocode, this is !IsZero(baseregister<47:outputsize>), + * but we've just cleared the bits above 47, so simplify the test. + */ + if (descaddr >> outputsize) { + level = 0; + fault_type = ARMFault_AddressSize; + goto do_fault; + } + /* * We rely on this masking to clear the RES0 bits at the bottom of the TTBR * and also to mask out CnP (bit 0) which could validly be non-zero. */ descaddr &= ~indexmask; - /* The address field in the descriptor goes up to bit 39 for ARMv7 - * but up to bit 47 for ARMv8, but we use the descaddrmask - * up to bit 39 for AArch32, because we don't need other bits in that case - * to construct next descriptor address (anyway they should be all zeroes). + /* + * For AArch32, the address field in the descriptor goes up to bit 39 + * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0 + * or an AddressSize fault is raised. So for v8 we extract those SBZ + * bits as part of the address, which will be checked via outputsize. + * For AArch64, the address field always goes up to bit 47 (with extra + * bits for FEAT_LPA placed elsewhere). AArch64 implies v8. */ - descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & - ~indexmask_grainsize; + if (arm_feature(env, ARM_FEATURE_V8)) { + descaddrmask = MAKE_64BIT_MASK(0, 48); + } else { + descaddrmask = MAKE_64BIT_MASK(0, 40); + } + descaddrmask &= ~indexmask_grainsize; /* Secure accesses start with the page table in secure memory and * can be downgraded to non-secure at any step. Non-secure accesses @@ -11558,7 +11593,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* Invalid, or the Reserved level 3 encoding */ goto do_fault; } + descaddr = descriptor & descaddrmask; + if (descaddr >> outputsize) { + fault_type = ARMFault_AddressSize; + goto do_fault; + } if ((descriptor & 2) && (level < 3)) { /* Table entry. The top five bits are attributes which may From patchwork Thu Feb 10 04:04:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 541378 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp1925630imo; Wed, 9 Feb 2022 20:16:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJxSnmHb3XfDQqO43epI9sd7BP4m9mE0D6u8mUZD1nQTr1zP2axXjXi+Zx3jz+BkveNUZIpK X-Received: by 2002:a25:9091:: with SMTP id t17mr5313901ybl.229.1644466568269; Wed, 09 Feb 2022 20:16:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644466568; cv=none; d=google.com; s=arc-20160816; b=JgJaqLFu6fvWQ7qeyem81DL72Rsuoo6+7vLLfQTnHD8LvebIK45jP81HO+haSqSkVe MRp3KYVA7o6GAhxpeirObZficJ5dEEbsZQ98tpHmtmumj/zlujeCg3bgke6M80RngOLS 7BOhEWchduX7hPT9t2c030X6OZ+NWstk6W54ZKQTadKc0cS6RWEUAkK/KZoD7X6fmfgD 2Oi1IihtQB9h1bdKu/w4fMjP+gMZH71YSzzHu9C0ZniyCoG/VtigNgzRVgILYGjosypj 3zncEnhjt7FkPGVJfEfr5fkq113mnQSLPL5E65CY9P0cPrzd3F1ocU4eEAXuzD/Y9adJ KeuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yVExx3SXXr9h6DkfYn7yNhxsG0U7fq7HrQiNwR7HpZk=; b=gZpXotKlrTC4ZALK6vpUFuh1iJm2Q0Qd8nk6qTR85H7ny3Ue832zSEYM0hNDnysTJm lLhVF6QRATllNbrxGJjM1NiUym2c2YvoztS6p1aWjNfavLni7apNj+R34pfDysILmXgL 2+E+C9HT8H1Laxktwj5AEXWOKbNXwMR3iB/NaDieKJRJD42JMDrXwRq7OOyUoiAW8gRe 0j8B8Y8WPodU69A0px7HTVK2x+Yz6crt8lDBxhtPw8g2fkAaK4RdpGmVQwmhd9n7RvrM xv9yfykJ1aSwaZi6YvM3OeTo0yV+k1Um5WNvHddNK4vEHuYqd1qZWxQTPMl7Bpbur5pJ 6jdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fsL5LBG8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y141si3414534ywy.120.2022.02.09.20.16.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Feb 2022 20:16:08 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fsL5LBG8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36932 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nI0sJ-0001Fx-O0 for patch@linaro.org; Wed, 09 Feb 2022 23:16:07 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54186) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nI0hW-00045G-PQ for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:04:59 -0500 Received: from [2607:f8b0:4864:20::430] (port=33663 helo=mail-pf1-x430.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nI0hU-000498-GQ for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:04:58 -0500 Received: by mail-pf1-x430.google.com with SMTP id i186so8096783pfe.0 for ; Wed, 09 Feb 2022 20:04:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yVExx3SXXr9h6DkfYn7yNhxsG0U7fq7HrQiNwR7HpZk=; b=fsL5LBG8K3oCMUeM+JopWyclUVsDw32EhvAFlE6HRLkdXrVz1Nk5yOcqw6SLxGVs9V eBXZgOUdIE+wK8ttHqJlRwnvm9tmzVwsvayxQZAP/zIm67vNOmcOamGe49MVWIJUESaD /DmWuWCwx1netcN011x6pGw8Jn4huH+5Txx123X0QiVF67SQvAmjLUGZnWyH1Sqj3z8V 2DVUOuwh/j4keI3yyWke6EwfCHrfSc6HBRQGcdkO4AHuoGkzXcZBuFwFxr3lSjDwhFhx 755dlRqwk58lj+b1V2zPAdGX1bZFJi1USPe/OjCDLZqDzdL7hWLxzCO2rgK0TBrCf3Oh kt5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yVExx3SXXr9h6DkfYn7yNhxsG0U7fq7HrQiNwR7HpZk=; b=kCho54plIq8gRYGDxHxPw+A57vKr+2ggeyj6Qe6nS26n3uH+kP3L6APNT0M3OWUBuy uVbjd2FTtMDrvsp3Rq8sY8WUgy29WMIFzXXSTWJSWT/afy1VyaePXsWHeYiswLkpzp9Q v2J2u7EnnuL9lqeELTnuRP9FFlip9mXfQ7Y3CSfWMEY2r/WKgzwl3AGixFUViJMjILQq eMO+bxi5p4a2+YhaJt6VVWA+s+a8Swt3pNBBg3swn3NOFbdW/vKBVbMwHlX4RsGd7/By Mx522TD/mjlB1WxmjVd5yhScIo41/iYwcAERo4IxvO+5+lvPnk8H08IjWH45+h7mA9+G klpw== X-Gm-Message-State: AOAM533j3Kp74zBs8MWt2sjkMPG6SBp8NhS/sMh0qHPJSxgu97Ul+U9O 1Lk8WG117tnyQ77iHVmagaqDy5MdqvDBFpuX X-Received: by 2002:a63:4182:: with SMTP id o124mr4654288pga.479.1644465895232; Wed, 09 Feb 2022 20:04:55 -0800 (PST) Received: from localhost.localdomain ([124.189.222.164]) by smtp.gmail.com with ESMTPSA id y4sm9749814pgp.5.2022.02.09.20.04.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Feb 2022 20:04:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 08/15] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA Date: Thu, 10 Feb 2022 15:04:16 +1100 Message-Id: <20220210040423.95120-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210040423.95120-1-richard.henderson@linaro.org> References: <20220210040423.95120-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::430 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The original A.a revision of the AArch64 ARM required that we force-extend the addresses in these registers from 49 bits. This language has been loosened via a combination of IMPLEMENTATION DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of the entire aligned address. This means that we do not have to consider whether or not FEAT_LVA is enabled, and decide from which bit an address might need to be extended. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 015f992f02..e5050816cf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6421,11 +6421,18 @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, ARMCPU *cpu = env_archcpu(env); int i = ri->crm; - /* Bits [63:49] are hardwired to the value of bit [48]; that is, the - * register reads and behaves as if values written are sign extended. + /* * Bits [1:0] are RES0. + * + * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA) + * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if + * they contain the value written. It is CONSTRAINED UNPREDICTABLE + * whether the RESS bits are ignored when comparing an address. + * + * Therefore we are allowed to compare the entire register, which lets + * us avoid considering whether or not FEAT_LVA is actually enabled. */ - value = sextract64(value, 0, 49) & ~3ULL; + value &= ~3ULL; raw_write(env, ri, value); hw_watchpoint_update(cpu, i); @@ -6471,10 +6478,19 @@ void hw_breakpoint_update(ARMCPU *cpu, int n) case 0: /* unlinked address match */ case 1: /* linked address match */ { - /* Bits [63:49] are hardwired to the value of bit [48]; that is, - * we behave as if the register was sign extended. Bits [1:0] are - * RES0. The BAS field is used to allow setting breakpoints on 16 - * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether + /* + * Bits [1:0] are RES0. + * + * It is IMPLEMENTATION DEFINED whether bits [63:49] + * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit + * of the VA field ([48] or [52] for FEAT_LVA), or whether the + * value is read as written. It is CONSTRAINED UNPREDICTABLE + * whether the RESS bits are ignored when comparing an address. + * Therefore we are allowed to compare the entire register, which + * lets us avoid considering whether FEAT_LVA is actually enabled. + * + * The BAS field is used to allow setting breakpoints on 16-bit + * wide instructions; it is CONSTRAINED UNPREDICTABLE whether * a bp will fire if the addresses covered by the bp and the addresses * covered by the insn overlap but the insn doesn't start at the * start of the bp address range. We choose to require the insn and @@ -6487,7 +6503,7 @@ void hw_breakpoint_update(ARMCPU *cpu, int n) * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). */ int bas = extract64(bcr, 5, 4); - addr = sextract64(bvr, 0, 49) & ~3ULL; + addr = bvr & ~3ULL; if (bas == 0) { return; } From patchwork Thu Feb 10 04:04:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 541379 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp1925662imo; Wed, 9 Feb 2022 20:16:11 -0800 (PST) X-Google-Smtp-Source: ABdhPJzQq6NwhdOr7RHwpMCOcWuTav3zhQrbS1tBErZ4ojLK87Jc86T7ug+zBZQQ1FUdvKJqZSP7 X-Received: by 2002:a25:ab33:: with SMTP id u48mr5451021ybi.119.1644466571520; Wed, 09 Feb 2022 20:16:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644466571; cv=none; d=google.com; s=arc-20160816; b=RBspUWyfgVRhNDGAYC5HJ+trIlzMMI76rECOMONbxQxvXkVMtw410p09fFyTy6J8Kh B0z5a478H1WFC14B3d8aj4TkUxLn5ya16goO3kBWPuNhjZ8JAcS25qh5OeHlRouDylaC tjhoBTRkcM2htvv6SGsX5LU33krgUJZh1W0vVCsAsRnk2ocwRcRTctmKfOJM81V4Kqrp aZBTXew3PkSeusRyc31HsLOUD7S10ozwoUxi3/lAChpM73n7gGn/D7Hek7eKZB0S+oB8 w75/C6adYOGckBVEDuG+PTXmOs8wyVsxo9ie90djadK54P4bokG8yiWDX1EwGEAXLGYe DUpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Wo37py8XK0LMBdk7Dcs+T7V1N42HxeZfeXF4Go5VbHY=; b=OFkXG3aQLLaozzc3Tee1BPOdVuzYOkllI9TUzxZi6VGGURu0a5SZjvnvFW3wtWSLjB g09yae++FRF72y2Z18ZCJ2qQfolYgwMfSfqF8ojcH4OBUTPvii3BuopzrkJua+zpRKFZ 5BSiHqGs9ZRtexTDcJ2Wp+8akD7AHyjnJaOn3FSE0N5WNp7rx3boWCsqOt7l6D1dQQZf BkxR5Dc5jwQ3Nl3H11pB+igGvdptvjIRJld/hgd+EW+HNwq5eILfATEaWp+e+UD3dCms xiONqeLPgVPbAn7fmvznjQ7ypgwTrttu/Wd2hTMpdhijl5lK1nm4ZuPANJ4bW+aadqC7 UJiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KmilAzqq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v191si12853328ybg.827.2022.02.09.20.16.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Feb 2022 20:16:11 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KmilAzqq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37156 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nI0sN-0001PA-2K for patch@linaro.org; Wed, 09 Feb 2022 23:16:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54218) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nI0hZ-00046Q-6B for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:05:01 -0500 Received: from [2607:f8b0:4864:20::42e] (port=42990 helo=mail-pf1-x42e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nI0hX-00049S-9e for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:05:00 -0500 Received: by mail-pf1-x42e.google.com with SMTP id i6so6085586pfc.9 for ; Wed, 09 Feb 2022 20:04:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Wo37py8XK0LMBdk7Dcs+T7V1N42HxeZfeXF4Go5VbHY=; b=KmilAzqqzzMcK2CxmTEW+WnaO+0sT7KCHt56JNPJ8uY/BNOYDqhCDXj3KYZJx4beUA o3zyanFSUTCbH0ewp18YO7jfkDniWacZzHsQ9U/UxOkDyduLs6WR1H+8zCe2aRxfrFHq uJw0u8he6XRhPf8yhUJz1B41ouu0Kly0YmW4l1Qgc+dKh9jB6DQMKMzMrwWUgWYZXQt1 rYNVxt8GWtHjx2MrTk7jYE5ntXLmwcApE8wntYxphPSx9ivxqSPUqzXaeyjxLdNNDBx6 CiE2N9yHg1mL/yQxZxAAoq8PUqF/5KCr4/m7WjsVvjijDp7Z2sv2IcfbnFXRilm0Gcq4 nUlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wo37py8XK0LMBdk7Dcs+T7V1N42HxeZfeXF4Go5VbHY=; b=bNzldBqQT+Y+T3J+5T6l521uIs9bS41hmJBTeTQYBwz40mU6xE4fQMPnrYwsRFWd1s ti7fCAGR/G1yysigH5K7PVg/euV14ii8wol21yURjq4LQE+hjNx4URvdLU3h6QJRzLDd lnwSVpTRb5osqbIPua9/GmC/m4AjqP+p5sNhQi+QR4myoGxDoxJbK7W8AqgNPGIaKyCs wwzrNW9fArbKJR3EKoMBpZmuZAMPktPRk6m4Ia+9bnjiMxqLWfeXiCY4AQuCG2ebWE9m dJ5aPb3CbQkxtdbwXR8fYExUomuHJi414tluBQn4K3NKRyLWzpVtgcWzXd/bzHzsamlh XoKg== X-Gm-Message-State: AOAM530rJ8p0BheCdgTk9uv0F/6NHVdsCExt1rk/nbNa96iVfCChaJf0 I52DTX4BJyRhveuYsyrjdsBfgbNb3+R4f88z X-Received: by 2002:a05:6a00:a1e:: with SMTP id p30mr5625210pfh.66.1644465898043; Wed, 09 Feb 2022 20:04:58 -0800 (PST) Received: from localhost.localdomain ([124.189.222.164]) by smtp.gmail.com with ESMTPSA id y4sm9749814pgp.5.2022.02.09.20.04.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Feb 2022 20:04:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 09/15] target/arm: Implement FEAT_LVA Date: Thu, 10 Feb 2022 15:04:17 +1100 Message-Id: <20220210040423.95120-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210040423.95120-1-richard.henderson@linaro.org> References: <20220210040423.95120-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This feature is relatively small, as it applies only to 64k pages and thus requires no additional changes to the table descriptor walking algorithm, only a change to the minimum TSZ (which is the inverse of the maximum virtual address space size). Note that this feature widens VBAR_ELx, but we already treat the register as being 64 bits wide. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 5 +++++ target/arm/cpu64.c | 1 + target/arm/helper.c | 9 ++++++++- 4 files changed, 15 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 7f38d33b8e..5f9c288b1a 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -11,7 +11,7 @@ #ifdef TARGET_AARCH64 # define TARGET_LONG_BITS 64 # define TARGET_PHYS_ADDR_SPACE_BITS 48 -# define TARGET_VIRT_ADDR_SPACE_BITS 48 +# define TARGET_VIRT_ADDR_SPACE_BITS 52 #else # define TARGET_LONG_BITS 32 # define TARGET_PHYS_ADDR_SPACE_BITS 40 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6a4d50e82..c52d56f669 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4289,6 +4289,11 @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; } +static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; +} + static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8786be7783..d80a7eafac 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,6 +781,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ + t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LPA */ cpu->isar.id_aa64mmfr2 = t; t = cpu->isar.id_aa64zfr0; diff --git a/target/arm/helper.c b/target/arm/helper.c index e5050816cf..62935b06d0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11269,7 +11269,14 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, } else { max_tsz = 39; } - min_tsz = 16; /* TODO: ARMv8.2-LVA */ + + min_tsz = 16; + if (using64k) { + if (cpu_isar_feature(aa64_lva, env_archcpu(env))) { + min_tsz = 12; + } + } + /* TODO: FEAT_LPA2 */ if (tsz > max_tsz) { tsz = max_tsz; From patchwork Thu Feb 10 04:04:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 541381 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp1926831imo; Wed, 9 Feb 2022 20:19:00 -0800 (PST) X-Google-Smtp-Source: ABdhPJzIigZ/W4VGGm+ws96+4dX8SfWv4yTfz/I0pTZ5rMA2SS9uoIlfpkkn5iQAGEAG0bInQME1 X-Received: by 2002:a25:8209:: with SMTP id q9mr5346957ybk.536.1644466740260; Wed, 09 Feb 2022 20:19:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644466740; cv=none; d=google.com; s=arc-20160816; b=SvWhWtflnLqgsKaS4UzILIlQHCfxqqT84g425wbCWx0+ql2M1EFRS0EWL9lown5K7i FzSkvTCyGvyLwtjckNYdvtNfpphwcNc6I/+USTD66BYgXWUo9c84IslKRxgO1eo/76FK Q4G0TK3u9WKhTz3X2OXMwNqJ7Pc+pqhirLI+7+vwg4XJMRkkYo4FYRcLy1JKidJ8Im91 STp/u2p3gXIva7udjprjTyBVKGIgmnpiTkA9eGda+U1/lK19lZrzrzs0UpdZzPTlaeYa V8NA3jrq7axCjNAzn+YDijV6R8RtyAEpsON1HkHVWLuy5G2eq7KoaJXhvyvgKs8ZSu55 kdWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kHg4U9LRhzSdYYvCz2waEIRzlEfsFRMNDs65CPCnE5Y=; b=j4bZQqNBlxUfJnHdmQo+KPZksg2bpDBOR9A/bQdcAk3PiV6qXnFErxhpBHkL+jEsYR tPqeYCkTLzOCGs2IcbT4+mMmtPqz8SumbaxuPIgFI0lUlPQZiyuk9q3uLz8tEACGDizL mJRBtJMU7USA3LSOR4zj1sPd2cxbDG6/bcUKzS/Do3k+nRuwObUaIfhzaRT8F7bu8QY3 JMURc36Vh3ceJjUHDS+u+tdBuCRmJYtTD5stG4aF6U7LIiCTrswwSay4QwZkHAxx/r21 kCEvFl6og5I+p2UAQKlz/8yXa5EuwudBgBxGuRsIUBUBCMrW5mzSBoFx6Bw1zoygMJbj y7zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=myMuzfW7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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The only thing left at this point is to handle the extra bits in the TTBR and in the table descriptors. Note that PAR_EL1 and HPFAR_EL2 are nominally extended, but we don't mask out the high bits when writing to those registers, so no changes are required there. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu64.c | 2 +- target/arm/helper.c | 19 ++++++++++++++++--- 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 5f9c288b1a..b59d505761 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -10,7 +10,7 @@ #ifdef TARGET_AARCH64 # define TARGET_LONG_BITS 64 -# define TARGET_PHYS_ADDR_SPACE_BITS 48 +# define TARGET_PHYS_ADDR_SPACE_BITS 52 # define TARGET_VIRT_ADDR_SPACE_BITS 52 #else # define TARGET_LONG_BITS 32 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d80a7eafac..707ae7767f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -765,7 +765,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64pfr1 = t; t = cpu->isar.id_aa64mmfr0; - t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */ + t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ cpu->isar.id_aa64mmfr0 = t; t = cpu->isar.id_aa64mmfr1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 62935b06d0..9b1b1b2611 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11171,6 +11171,7 @@ static const uint8_t pamax_map[] = { [3] = 42, [4] = 44, [5] = 48, + [6] = 52, }; /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ @@ -11562,11 +11563,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, descaddr = extract64(ttbr, 0, 48); /* - * If the base address is out of range, raise AddressSizeFault. + * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR. + * + * Otherwise, if the base address is out of range, raise AddressSizeFault. * In the pseudocode, this is !IsZero(baseregister<47:outputsize>), * but we've just cleared the bits above 47, so simplify the test. */ - if (descaddr >> outputsize) { + if (outputsize > 48) { + descaddr |= extract64(ttbr, 2, 4) << 48; + } else if (descaddr >> outputsize) { level = 0; fault_type = ARMFault_AddressSize; goto do_fault; @@ -11618,7 +11623,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, } descaddr = descriptor & descaddrmask; - if (descaddr >> outputsize) { + + /* + * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12] + * of descriptor. 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Extend arm_fi_to_lfsc to handle these faults. Assert that this new translation level does not leak into faults types for which it is not defined, which allows some masking of fi->level to be removed. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3d3d41ba2b..00af41d792 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -462,28 +462,51 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) case ARMFault_None: return 0; case ARMFault_AddressSize: - fsc = fi->level & 3; + assert(fi->level >= -1 && fi->level <= 3); + if (fi->level < 0) { + fsc = 0b101001; + } else { + fsc = fi->level; + } break; case ARMFault_AccessFlag: - fsc = (fi->level & 3) | (0x2 << 2); + assert(fi->level >= 0 && fi->level <= 3); + fsc = 0b001000 | fi->level; break; case ARMFault_Permission: - fsc = (fi->level & 3) | (0x3 << 2); + assert(fi->level >= 0 && fi->level <= 3); + fsc = 0b001100 | fi->level; break; case ARMFault_Translation: - fsc = (fi->level & 3) | (0x1 << 2); + assert(fi->level >= -1 && fi->level <= 3); + if (fi->level < 0) { + fsc = 0b101011; + } else { + fsc = 0b000100 | fi->level; + } break; case ARMFault_SyncExternal: fsc = 0x10 | (fi->ea << 12); break; case ARMFault_SyncExternalOnWalk: - fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12); + assert(fi->level >= -1 && fi->level <= 3); + if (fi->level < 0) { + fsc = 0b010011; + } else { + fsc = 0b010100 | fi->level; + } + fsc |= fi->ea << 12; break; case ARMFault_SyncParity: fsc = 0x18; break; case ARMFault_SyncParityOnWalk: - fsc = (fi->level & 3) | (0x7 << 2); + assert(fi->level >= -1 && fi->level <= 3); + if (fi->level < 0) { + fsc = 0b011011; + } else { + fsc = 0b011100 | fi->level; + } break; case ARMFault_AsyncParity: fsc = 0x19; From patchwork Thu Feb 10 04:04:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 541373 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp1923578imo; Wed, 9 Feb 2022 20:11:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJwRlrecnggOrw3vjMbved/C5tKFwDLVY2Uw1ad3Ph8xaBrIB31/4b85JtGvSFFJ1erob1I7 X-Received: by 2002:a05:6902:c4:: with SMTP id i4mr5276180ybs.343.1644466288181; Wed, 09 Feb 2022 20:11:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644466288; cv=none; d=google.com; s=arc-20160816; b=GeJ5Goex+pHnPosjKmtRisEythGTd/ycPf9BEgxlvk3g/UNX5poZsq0jv28je+oIdT koKQJQ/p8hj2ljtp4rMGvwOD/hYV1SL2UDwSZ7ceoMpoFVI3qctizyVI2yvtC/siTq2R 3H6qiBwK2AOlAMxor7nL75aOPCiFyWTVTnAdZa6727Hl37/N1CRYUZ1IjaD6+SqkGpva k6bZyk74jgVgtlI3mwQVwHY+ydbDzDsRwyvOHHr5DHSy3GJcRSqpmcKDBKf+2jyMSw5B Qw6qruyWOHDro4em6LGR/74FYYgHmPMSk3vo3CXnJqP9BkBZ7QzdH9jPS51iYXfeCHIO 5ZUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GtHWBu/qD/0bUllW5Gw8BHbTDtQN4Yofcww2tVSz2tQ=; b=pFtYi+SxNXeQybcgwBjvNLcSv3kTAIEEYuImbJSxNaLfa93YnJl24/VKXE3zuYYkwE MnvBymRKpZ9Lr9lFEDRnL2VKfidU+DdVae/4y3gljeKcRh9lqX8N/EWEQgYe1Wm8Z/mJ JIwEOfE33Tj9YgqcbvYRmKC2z+/KmO8uNF/2cUlFXZq2KOHvCXRubd2Bz2ftfh0Eudzs 9tOCHOGYYK112QJrWsdBeQLld+IDTvFoZ2D1qCBwo61gcgacr8G3hWwMtiKOeCrmS9O8 K4olNbV4IejM6d03VR7AnqLh7L9S0vS70C7VC5d4dD8pRZy2YZIEfci+U+dYkUqnO2dL UFXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kCkF8KGN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r82si43821ybc.134.2022.02.09.20.11.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Feb 2022 20:11:28 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kCkF8KGN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50834 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nI0nn-0008V7-Kh for patch@linaro.org; Wed, 09 Feb 2022 23:11:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54628) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nI0jc-0004OH-UJ for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:07:08 -0500 Received: from [2607:f8b0:4864:20::636] (port=39933 helo=mail-pl1-x636.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nI0hp-0004Li-Da for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:07:03 -0500 Received: by mail-pl1-x636.google.com with SMTP id w1so742565plb.6 for ; Wed, 09 Feb 2022 20:05:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GtHWBu/qD/0bUllW5Gw8BHbTDtQN4Yofcww2tVSz2tQ=; b=kCkF8KGNhRNZoC5qieC/U/Lg9Y1J+IRE1/GYMka6glUR0MKjNGrCBltLzLbuc5XyL4 CUnknBGzSBwkiLdjW20WXSf1K+2WSwfeYvTGlQHUGZU96Wb6bo/XfonLWPyCGHpnei1g 3+NBx1RGIgyFI5MNkZI2AE1QdxY91F6ewXtA6Ed/lYtnhC6CNOVsRXl1NW0v8o6kgyJ/ MPRfsnaJWwoRjLluv2iTzVitr7gC1H/sfkCo1zn6L339XGt6vm8kgXHXeiFmmM561gWm gXV/rdd7CNos0pZv5zdS6euyp+Hx4xxUi3pC9/Le2ocGeqIPvw553eOufo2NTfbPQ8or CrRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GtHWBu/qD/0bUllW5Gw8BHbTDtQN4Yofcww2tVSz2tQ=; b=QMDaOEZc4Sm755Fo9rpGW2e/XpKjKrnn5jxNKDl5fTPK8TjuafNCnbN7ZpGSqPba/i TnGzXCFOAC2Eq8eCoDG2pl/Yl/FDejDDQFbRnykfJFBBeo/K+F+jqxC3fVv1VgUbwyoC rngzth2miZTI+jDX2zZDCPk4Hh0DW1frraOUNquvLbsOt+9iZ+JsBIfkf3ai81kLi4jH Sb7PW3TPME8KUyEbmQgWftN1Ps+5L09G1t98x8NZ0Bxwj902MQdPAOXqpelA/e181Qlp HeHzQjL9Nu5ZwOIMaw6SZeQlak2fd27ub4WMQxTuBUEe8uMEGx2d+ttde2K9IWBQOPDL ZDBA== X-Gm-Message-State: AOAM531/d/4Mx+RS6wrCiMlQ+pCZJxR4wGJp3Zdtqai3+DeZyXnJdFEu AnS0XrCkBF2cxJXnSLv03cEKYVXprbUua5tY X-Received: by 2002:a17:903:2306:: with SMTP id d6mr5018868plh.14.1644465906216; Wed, 09 Feb 2022 20:05:06 -0800 (PST) Received: from localhost.localdomain ([124.189.222.164]) by smtp.gmail.com with ESMTPSA id y4sm9749814pgp.5.2022.02.09.20.05.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Feb 2022 20:05:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 12/15] target/arm: Introduce tlbi_aa64_get_range Date: Thu, 10 Feb 2022 15:04:20 +1100 Message-Id: <20220210040423.95120-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210040423.95120-1-richard.henderson@linaro.org> References: <20220210040423.95120-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::636 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Merge tlbi_aa64_range_get_length and tlbi_aa64_range_get_base, returning a structure containing both results. Pass in the ARMMMUIdx, rather than the digested two_ranges boolean. This is in preparation for FEAT_LPA2, where the interpretation of 'value' depends on the effective value of DS for the regime. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 58 +++++++++++++++++++-------------------------- 1 file changed, 24 insertions(+), 34 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9b1b1b2611..8b1899ceef 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4509,70 +4509,60 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, } #ifdef TARGET_AARCH64 -static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, - uint64_t value) -{ - unsigned int page_shift; - unsigned int page_size_granule; - uint64_t num; - uint64_t scale; - uint64_t exponent; +typedef struct { + uint64_t base; uint64_t length; +} TLBIRange; + +static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, + uint64_t value) +{ + unsigned int page_size_granule, page_shift, num, scale, exponent; + TLBIRange ret = { }; - num = extract64(value, 39, 5); - scale = extract64(value, 44, 2); page_size_granule = extract64(value, 46, 2); if (page_size_granule == 0) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", page_size_granule); - return 0; + return ret; } page_shift = (page_size_granule - 1) * 2 + 12; - + num = extract64(value, 39, 5); + scale = extract64(value, 44, 2); exponent = (5 * scale) + 1; - length = (num + 1) << (exponent + page_shift); - return length; -} + ret.length = (num + 1) << (exponent + page_shift); -static uint64_t tlbi_aa64_range_get_base(CPUARMState *env, uint64_t value, - bool two_ranges) -{ - /* TODO: ARMv8.7 FEAT_LPA2 */ - uint64_t pageaddr; - - if (two_ranges) { - pageaddr = sextract64(value, 0, 37) << TARGET_PAGE_BITS; + if (regime_has_2_ranges(mmuidx)) { + ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS; } else { - pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS; + ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS; } - return pageaddr; + return ret; } static void do_rvae_write(CPUARMState *env, uint64_t value, int idxmap, bool synced) { ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap); - bool two_ranges = regime_has_2_ranges(one_idx); - uint64_t baseaddr, length; + TLBIRange range; int bits; - baseaddr = tlbi_aa64_range_get_base(env, value, two_ranges); - length = tlbi_aa64_range_get_length(env, value); - bits = tlbbits_for_regime(env, one_idx, baseaddr); + range = tlbi_aa64_get_range(env, one_idx, value); + bits = tlbbits_for_regime(env, one_idx, range.base); if (synced) { tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), - baseaddr, - length, + range.base, + range.length, idxmap, bits); } else { - tlb_flush_range_by_mmuidx(env_cpu(env), baseaddr, - length, idxmap, bits); + tlb_flush_range_by_mmuidx(env_cpu(env), range.base, + range.length, idxmap, bits); } } From patchwork Thu Feb 10 04:04:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 541377 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp1924781imo; Wed, 9 Feb 2022 20:14:11 -0800 (PST) X-Google-Smtp-Source: ABdhPJxrKBUI7GJn7O0eAQcSXzPyWrOxNEdI7VZQJYdIXXxeV63sXHUiDdvqsAsSyKMycBpmnajp X-Received: by 2002:a81:ae07:: with SMTP id m7mr5277731ywh.269.1644466451547; Wed, 09 Feb 2022 20:14:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644466451; cv=none; d=google.com; s=arc-20160816; b=OI8OIPaHA1sC7RUmzy7Ia96EC5iniCyPVzN304qYXLj2tuArNHYFEqJFIbERwOqWUp T6lusYlFudQrjhiYZWRQbXbx8v65LZt7ZM31vLdxEAoKdF7sRXSuVwxtebRh/69mwnw7 YIVs2sCOe0RFzmz9WUqX/6AC0mBjZ4E4NqWIoNxiGzurvQTviAYFaRg7GpIbivRqltHr XHb8bb4yjEkDeJ8F9QOaaLXx3bJUmA9qtTnFekS6TdDXfZFY6PQKJq3VXOZPyRR0V5Zg Huq2l5tgjoqak57tID9IX8eOxacn2tKZAJzgJAcqaqlp1Bt6zxKeDsUQxbuo/CjVfdQr 8w0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ySk6DI87bH3eZGMitydYEQW5NydufZmFbEicSz0knRM=; b=sxr2dglxfhUJbE41R+lKzahDEKhkO8dXPp4BoXcUNT60FLvdTdsaX1Os32TSnGfGyR M37o/5Oo5LVvGR9av05raHVocbfZx/4jkO13Tt4rghzxYucLkvvjNnqvDlmAQLswoPJf h+4REdeO/MetCRxqt5xmeLener99oHuWAhBJC4m4JLS/fndMwtP3VDb78Jv6klYLYlo0 ILeUdDW1ZAE8BfCXzzEGOkekdN1y2lge9Kud4sHl0uZte90lyTGwwatzd+JTViOc7i1T Fe+CM34dIwZbLY5mhFYVYsMpszPsb4wR1Pun8oSoL7XRNoikiYvEOklOLXStw74buIxh u5cg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="dpyNdJ/F"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fixes: 84940ed8255 ("target/arm: Add support for FEAT_TLBIRANGE") Reported-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8b1899ceef..e2551e693b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4536,10 +4536,11 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, ret.length = (num + 1) << (exponent + page_shift); if (regime_has_2_ranges(mmuidx)) { - ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS; + ret.base = sextract64(value, 0, 37); } else { - ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS; + ret.base = extract64(value, 0, 37); } + ret.base <<= page_shift; return ret; } From patchwork Thu Feb 10 04:04:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 541385 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp1929659imo; Wed, 9 Feb 2022 20:26:00 -0800 (PST) X-Google-Smtp-Source: ABdhPJzT/XI5J3XXDVicJvlslmvzOUEG02CcBp+TIGnvjonTl5XdKAJwiGRtTCmDQnx1LzrjZqih X-Received: by 2002:a05:6902:114d:: with SMTP id p13mr6065492ybu.335.1644467160415; Wed, 09 Feb 2022 20:26:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644467160; cv=none; d=google.com; s=arc-20160816; b=ojVkrvFC1cHKvuomsGm4LaDpYsn2qP6k27WoIC/B/prS0ZM0YJRCI0xis9HC8gewmr Fi9NPcfEqcI8d1qGnetzRaiaDm7eopsgcc/1O6b0o4leBp3VL5axltJVsTkiO5rjK/HM iWJJxLkS3HIaL3dKDgKhKMsQixsfDzLbZiqC7Ib2anPLfXMokjhThAkXX2QJ44yujz39 KraOtWo5Ydea8mEOgr0RGIN0Gtha3eNmG6mOos9u3Hl89ey0I5fynY28eRiYeZm+y22x 6vam1fqOe25UomWJHrVTPdh+TUrseenybr+kiLROXRbnXQYWYu4Pz1lgzBfT68sFUvYR Jcow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/PyGX3z0esgQKjWtAq0OXlyQ3FBYa3KsBIg46iOmGfg=; b=Dpv7UtdVtmoUJViy/cQ6QHNlh1f3hwGr8dUnGoxhTvfsqaGvtCLPl6zWhypBIvOrSG P0juthdfjo6GXESfrconTOZht406eFR0GR77eG+vURAoaVtFEzQRQe8W925/Iv/ptess FijO7ma8IS9MzkzLPr7TaZwoRKDEWotax6s90ANY795bNu2+qBfHxhkNv0S+W7dymtFA Nr2Do4dnYcZqLNjTmELW6SMa+CPhbKbIyIXZKagQxfYM9m34yj6ntivSbm8YMrZJJzwj QavbOfR4tTdUar0DDvQaGdI/lxH21g6KjPQRxpSGjsLGVPnAmKj8PNOJCiW1weFA5H8t bGzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kfqC3NK4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x10si18922676ybt.512.2022.02.09.20.26.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Feb 2022 20:26:00 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kfqC3NK4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55512 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nI11r-0005Vf-Us for patch@linaro.org; Wed, 09 Feb 2022 23:25:59 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54634) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nI0jd-0004OK-0N for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:07:09 -0500 Received: from [2607:f8b0:4864:20::1036] (port=43962 helo=mail-pj1-x1036.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nI0jU-0004ME-PT for qemu-devel@nongnu.org; Wed, 09 Feb 2022 23:07:04 -0500 Received: by mail-pj1-x1036.google.com with SMTP id t14-20020a17090a3e4e00b001b8f6032d96so4321719pjm.2 for ; Wed, 09 Feb 2022 20:05:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/PyGX3z0esgQKjWtAq0OXlyQ3FBYa3KsBIg46iOmGfg=; b=kfqC3NK4ri29kF9NBPjhhpz6IjztxGGBsIcc2ETKQDQVMot/koXli4OmLUFxRRQdf6 4fPCqGpCdyHxBjxgkX5fpmzdI+4n6xHK1Dbfpz2UMBEwq0MIjUInvqnZVzXhAzkcRy0w avttEZx4P4phkTLj6EtCAL4Sb9IFwISptCpcweYvX70tpCJi2Tg2nSnqI16q7Ig+2ILw K7OvAh23uar0xAKByTOcWDbqR1hlRqcPWMzrIliaZleexRI1KDAzUk101vd1q2kyRJTD RaNws58VWuIkaXJVSm0w4cmLlvWAKl1TNmGYgQX8BVp9LqlAyWlADlie3Rni/P5KvDdb 5FAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/PyGX3z0esgQKjWtAq0OXlyQ3FBYa3KsBIg46iOmGfg=; b=pQJxlPHYDwamhiUfBAGz36ull/W+ofW+wdaIscFaqDRMLR4MjKlnVPDWvj8TtkWPBV lyPASX7fvrM3DYHCa4XC+LQVf/DN+5caTucE3jn/PReHRackDqzQz3pASq1LhGv1nrpI y48+oOVsRCel2GMVuhGo3l+oyoVxVtfTyaRb8V2BaNKmyETvyLPUtIkSc9B5yTul143E JjHtB0mvsNC/Pxg33rx/dhpAoGxsRZbQAtz9xsgvcX0vVO3rgI3YRPH9CP3AcSGnZR+A QR+clFi340pe8Tbwf2EZGpOgaKmfUGu06X3QDyhW3dm84eLm2TtswCCLViNpvPywTL0s WY1g== X-Gm-Message-State: AOAM5304i1s0zd5MdZwYjzazP98FCxgcoa2CApIkgZjY+YpDQWoTQfqL KiqwQ9mA+AUgJ6J4089CnH21OLuJOf1YfVQP X-Received: by 2002:a17:90a:19c2:: with SMTP id 2mr744294pjj.132.1644465911851; Wed, 09 Feb 2022 20:05:11 -0800 (PST) Received: from localhost.localdomain ([124.189.222.164]) by smtp.gmail.com with ESMTPSA id y4sm9749814pgp.5.2022.02.09.20.05.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Feb 2022 20:05:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 14/15] target/arm: Validate tlbi TG matches translation granule in use Date: Thu, 10 Feb 2022 15:04:22 +1100 Message-Id: <20220210040423.95120-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210040423.95120-1-richard.henderson@linaro.org> References: <20220210040423.95120-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1036 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For FEAT_LPA2, we will need other ARMVAParameters, which themselves depend on the translation granule in use. We might as well validate that the given TG matches; the architecture "does not require that the instruction invalidates any entries" if this is not true. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e2551e693b..771de959dd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4518,12 +4518,16 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, uint64_t value) { unsigned int page_size_granule, page_shift, num, scale, exponent; + /* Extract one bit to represent the va selector in use. */ + uint64_t select = sextract64(value, 36, 1); + ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true); TLBIRange ret = { }; page_size_granule = extract64(value, 46, 2); - if (page_size_granule == 0) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", + /* The granule encoded in value must match the granule in use. */ + if (page_size_granule != (param.using64k ? 3 : param.using16k ? 2 : 1)) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n", page_size_granule); return ret; } @@ -4535,7 +4539,7 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, ret.length = (num + 1) << (exponent + page_shift); - if (regime_has_2_ranges(mmuidx)) { + if (param.select) { ret.base = sextract64(value, 0, 37); } else { ret.base = extract64(value, 0, 37); From patchwork Thu Feb 10 04:04:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 541384 Delivered-To: patch@linaro.org Received: by 2002:ad5:420f:0:0:0:0:0 with SMTP id e15csp1928447imo; Wed, 9 Feb 2022 20:23:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJx2OZ9QnVDFigXqubvjm5npNt+6kuuS5hkQvR0oifQZBdcfkPY7qNSZUIpqpVmKgOJem4hZ X-Received: by 2002:a81:b309:: with SMTP id r9mr5764466ywh.503.1644466994575; Wed, 09 Feb 2022 20:23:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644466994; cv=none; d=google.com; s=arc-20160816; b=AWEOEQHIHCT+6hqibGtTo8Ld8v2GF22ozSAqU/YK76BHa1OK+vEeoFRddYNUkb4aqu omZU6ZOURG3Si3p+FP58ounZiw/KTZ2SUKHxqOUMrx88SkUh4tA1tsorcRAv1jl3fSb/ NBTAyR/j37aOL4wv0nJXHLSATrGz10/ElKPmBjs93XZNFK0DMiVn18ihNifvf9liIavV n0OfJDo+vs7GabdXEaF/qrk8aCvUTDPa6WnQ2qzj0OxObHxjRAsugbEQRMQO8DQXRnUC lr0uEqp755E18tXcbUQYnG3kXp4n3k/N3jjt6sf2LMK+6NHUq/VtVCeRM+H/0amFJbXK fNCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rl+deY7CG2LcOyT6/JU0+OryAiRw3UHGvhaIal+CJ9A=; b=HAi1sdoZnhzTuJEXofq3hoUGaNLq9tSUuCC8ztKxCLEzD7Pa9AKBJZvEMs2tDs2H/W Yt620AldpGTX+Tw4ilpR66PDGpfivC9PfnD00RluSNPTUxINJxO6rt+1hyZqPMKW2212 lknZdQJ2SLLS78lwZSphFVpwkIpjiJfjT0cfVvzyg28EownkAGK1VXk0s9R1Szkgb1oy rE2XbTsJ/brwxh+KBRzo7NYNY0966Ouo3PCcXcTfid6QtfSADHHR41FxRhvb52TLpoqk PCT/TvNVlo4tpQvz5+2hnBijArsCxQYtGxbJbU6zAMo37Xj76MvgrBTX7TaAmHzq1v1U 2gng== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bWtrIFoS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This introduces the DS bit to TCR_ELx, which is RES0 unless the page size is enabled and supports LPA2, resulting in the effective value of DS for a given table walk. The DS bit changes the format of the page table descriptor slightly, moving the PS field out to TCR so that all pages have the same sharability and repurposing those bits of the page table descriptor for the highest bits of the output address. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Check DS in tlbi_aa64_get_range. Check TGRAN4_2 and TGRAN16_2. --- target/arm/cpu.h | 22 +++++++++ target/arm/internals.h | 2 + target/arm/cpu64.c | 4 ++ target/arm/helper.c | 102 +++++++++++++++++++++++++++++++++++------ 4 files changed, 115 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c52d56f669..24d9fff170 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4284,6 +4284,28 @@ static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; } +static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; +} + +static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); +} + +static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; +} + +static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); +} + static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; diff --git a/target/arm/internals.h b/target/arm/internals.h index 00af41d792..a34be2e459 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1056,6 +1056,7 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) typedef struct ARMVAParameters { unsigned tsz : 8; unsigned ps : 3; + unsigned sh : 2; unsigned select : 1; bool tbi : 1; bool epd : 1; @@ -1063,6 +1064,7 @@ typedef struct ARMVAParameters { bool using16k : 1; bool using64k : 1; bool tsz_oob : 1; /* tsz has been clamped to legal range */ + bool ds : 1; } ARMVAParameters; ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 707ae7767f..9382c19e54 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -766,6 +766,10 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64mmfr0; t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* FEAT_LPA2: 52 bits */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* FEAT_LPA2: 52 bits */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* FEAT_LPA2: 52 bits */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* FEAT_LPA2: 52 bits */ cpu->isar.id_aa64mmfr0 = t; t = cpu->isar.id_aa64mmfr1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 771de959dd..bf694d8324 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4544,6 +4544,14 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, } else { ret.base = extract64(value, 0, 37); } + if (param.ds) { + /* + * With DS=1, BaseADDR is always shifted 16 so that it is able + * to address all 52 va bits. The input address is perforce + * aligned on a 64k boundary regardless of translation granule. + */ + page_shift = 16; + } ret.base <<= page_shift; return ret; @@ -11079,8 +11087,13 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, const int grainsize = stride + 3; int startsizecheck; - /* Negative levels are never allowed. */ - if (level < 0) { + /* + * Negative levels are usually not allowed... + * Except for FEAT_LPA2, 4k page table, 52-bit address space, which + * begins with level -1. Note that previous feature tests will have + * eliminated this combination if it is not enabled. + */ + if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) { return false; } @@ -11221,8 +11234,9 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; - bool epd, hpd, using16k, using64k, tsz_oob; - int select, tsz, tbi, max_tsz, min_tsz, ps; + bool epd, hpd, using16k, using64k, tsz_oob, ds; + int select, tsz, tbi, max_tsz, min_tsz, ps, sh; + ARMCPU *cpu = env_archcpu(env); if (!regime_has_2_ranges(mmu_idx)) { select = 0; @@ -11236,7 +11250,9 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, hpd = extract32(tcr, 24, 1); } epd = false; + sh = extract32(tcr, 12, 2); ps = extract32(tcr, 16, 3); + ds = extract64(tcr, 32, 1); } else { /* * Bit 55 is always between the two regions, and is canonical for @@ -11246,6 +11262,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, if (!select) { tsz = extract32(tcr, 0, 6); epd = extract32(tcr, 7, 1); + sh = extract32(tcr, 12, 2); using64k = extract32(tcr, 14, 1); using16k = extract32(tcr, 15, 1); hpd = extract64(tcr, 41, 1); @@ -11255,24 +11272,51 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, using64k = tg == 3; tsz = extract32(tcr, 16, 6); epd = extract32(tcr, 23, 1); + sh = extract32(tcr, 28, 2); hpd = extract64(tcr, 42, 1); } ps = extract64(tcr, 32, 3); + ds = extract64(tcr, 59, 1); } - if (cpu_isar_feature(aa64_st, env_archcpu(env))) { + if (cpu_isar_feature(aa64_st, cpu)) { max_tsz = 48 - using64k; } else { max_tsz = 39; } + /* + * DS is RES0 unless FEAT_LPA2 is supported for the given page size; + * adjust the effective value of DS, as documented. + */ min_tsz = 16; if (using64k) { - if (cpu_isar_feature(aa64_lva, env_archcpu(env))) { + if (cpu_isar_feature(aa64_lva, cpu)) { + min_tsz = 12; + } + ds = false; + } else if (ds) { + switch (mmu_idx) { + case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: + if (using16k) { + ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu); + } else { + ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu); + } + break; + default: + if (using16k) { + ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu); + } else { + ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu); + } + break; + } + if (ds) { min_tsz = 12; } } - /* TODO: FEAT_LPA2 */ if (tsz > max_tsz) { tsz = max_tsz; @@ -11294,6 +11338,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, return (ARMVAParameters) { .tsz = tsz, .ps = ps, + .sh = sh, .select = select, .tbi = tbi, .epd = epd, @@ -11301,6 +11346,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, .using16k = using16k, .using64k = using64k, .tsz_oob = tsz_oob, + .ds = ds, }; } @@ -11526,10 +11572,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * VTCR_EL2.SL0 field (whose interpretation depends on the page size) */ uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); + uint32_t sl2 = extract64(tcr->raw_tcr, 33, 1); uint32_t startlevel; bool ok; - if (!aarch64 || stride == 9) { + /* SL2 is RES0 unless DS=1 & 4kb granule. */ + if (param.ds && stride == 9 && sl2) { + if (sl0 != 0) { + level = 0; + fault_type = ARMFault_Translation; + goto do_fault; + } + startlevel = -1; + } else if (!aarch64 || stride == 9) { /* AArch32 or 4KB pages */ startlevel = 2 - sl0; @@ -11583,10 +11638,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0 * or an AddressSize fault is raised. So for v8 we extract those SBZ * bits as part of the address, which will be checked via outputsize. - * For AArch64, the address field always goes up to bit 47 (with extra - * bits for FEAT_LPA placed elsewhere). AArch64 implies v8. + * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2; + * the highest bits of a 52-bit output are placed elsewhere. */ - if (arm_feature(env, ARM_FEATURE_V8)) { + if (param.ds) { + descaddrmask = MAKE_64BIT_MASK(0, 50); + } else if (arm_feature(env, ARM_FEATURE_V8)) { descaddrmask = MAKE_64BIT_MASK(0, 48); } else { descaddrmask = MAKE_64BIT_MASK(0, 40); @@ -11621,11 +11678,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, /* * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12] - * of descriptor. Otherwise, if descaddr is out of range, raise - * AddressSizeFault. + * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of + * descaddr are in [9:8]. Otherwise, if descaddr is out of range, + * raise AddressSizeFault. */ if (outputsize > 48) { - descaddr |= extract64(descriptor, 12, 4) << 48; + if (param.ds) { + descaddr |= extract64(descriptor, 8, 2) << 50; + } else { + descaddr |= extract64(descriptor, 12, 4) << 48; + } } else if (descaddr >> outputsize) { fault_type = ARMFault_AddressSize; goto do_fault; @@ -11719,7 +11781,17 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, assert(attrindx <= 7); cacheattrs->attrs = extract64(mair, attrindx * 8, 8); } - cacheattrs->shareability = extract32(attrs, 6, 2); + + /* + * For FEAT_LPA2 and effective DS, the SH field in the attributes + * was re-purposed for output address bits. The SH attribute in + * that case comes from TCR_ELx, which we extracted earlier. + */ + if (param.ds) { + cacheattrs->shareability = param.sh; + } else { + cacheattrs->shareability = extract32(attrs, 6, 2); + } *phys_ptr = descaddr; *page_size_ptr = page_size;