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[81.169.180.215]) by mx.google.com with ESMTP id b22-v6si1929362ejp.176.2018.11.27.04.50.43; Tue, 27 Nov 2018 04:50:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=WXsV0kn8; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 2549BC222DF; Tue, 27 Nov 2018 12:50:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2970BC2226A; Tue, 27 Nov 2018 12:50:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 94E20C220EC; Tue, 27 Nov 2018 12:50:10 +0000 (UTC) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by lists.denx.de (Postfix) with ESMTPS id 1573AC21FE1 for ; Tue, 27 Nov 2018 12:50:10 +0000 (UTC) Received: by mail-wr1-f67.google.com with SMTP id l9so22535978wrt.13 for ; Tue, 27 Nov 2018 04:50:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ea3uDBv7pbwJWSxJpcTNsN8/cJRauGsBIduTy0qIefs=; b=WXsV0kn85bSVJVLMue0c0oqmz0PhOAj+M365Y+49csFWBtRi7xMZpxw05RbZnZMqHK CdqcnjFpTP1yJJpJE8jWEPheqvHyW6prg9szsaZvl0mrMyB+1pYqAdlw4xVVuqodOMTV emrjbRUUQC2TaaAp6paQepbSej/YNc34C0B7Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ea3uDBv7pbwJWSxJpcTNsN8/cJRauGsBIduTy0qIefs=; b=GCAtGvDNFKiD8RN50s4RQJG7DV5SkDFjBoRMc2oKef+ueFCBYaR11PwD0fuWyN6vB6 NJmPT9bsU0vS5xv0hlIibXCLmK92Rnhz4p2csPqUH97Ypb+qxhK5UrS1GqHwVihsafM2 5ILt4ktIDj0C/LNwDG51ooNGaSlOsZCsQTvlgm9VGv7oEy+tDwvZ/W+AzOLRnuq+vM6b sCTEFneYdK1OFmhMgrzzuljb4kLJ+7pThTIK22SUjYe5h1ledeGUry8yguJM9e80Plo/ uDlKIaNhc6zKMM671UNpQKh0aAcdacQmJQVNvrZ07HeVINaZ2XX4s/MFx/HEGUJTxgR7 P0ow== X-Gm-Message-State: AA+aEWbbHWfZe73x8hDLFgPl39WGIcLIupk15S2/t3As76TSexeHy/4T VcITMgVwSdc/5RefUxB5bnAlDA== X-Received: by 2002:adf:9246:: with SMTP id 64mr12420066wrj.130.1543323009359; Tue, 27 Nov 2018 04:50:09 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1087:3904:205d:1327:2414:27b8]) by smtp.gmail.com with ESMTPSA id p14sm3098056wrt.37.2018.11.27.04.50.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Nov 2018 04:50:08 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com, trini@konsulko.com Date: Tue, 27 Nov 2018 13:49:50 +0100 Message-Id: <20181127124953.4458-2-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181127124953.4458-1-benjamin.gaignard@st.com> References: <20181127124953.4458-1-benjamin.gaignard@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de, Benjamin Gaignard Subject: [U-Boot] [PATCH v5 1/4] dm: Add Hardware Spinlock class X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is uclass for Hardware Spinlocks. It implements two mandatory operations: lock and unlock and one optional relax operation. Signed-off-by: Benjamin Gaignard Reviewed-by: Simon Glass Reviewed-by: Patrice Chotard --- version 5 - rebased on top of master branch version 4: - make timeout loop more robust arch/sandbox/dts/test.dts | 4 + arch/sandbox/include/asm/state.h | 1 + configs/sandbox_defconfig | 2 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/hwspinlock/Kconfig | 16 ++++ drivers/hwspinlock/Makefile | 6 ++ drivers/hwspinlock/hwspinlock-uclass.c | 144 ++++++++++++++++++++++++++++++++ drivers/hwspinlock/sandbox_hwspinlock.c | 56 +++++++++++++ include/dm/uclass-id.h | 1 + include/hwspinlock.h | 140 +++++++++++++++++++++++++++++++ test/dm/Makefile | 1 + test/dm/hwspinlock.c | 40 +++++++++ 13 files changed, 414 insertions(+) create mode 100644 drivers/hwspinlock/Kconfig create mode 100644 drivers/hwspinlock/Makefile create mode 100644 drivers/hwspinlock/hwspinlock-uclass.c create mode 100644 drivers/hwspinlock/sandbox_hwspinlock.c create mode 100644 include/hwspinlock.h create mode 100644 test/dm/hwspinlock.c diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 2c6b422312..c438fa500c 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -731,6 +731,10 @@ pinctrl { compatible = "sandbox,pinctrl"; }; + + hwspinlock@0 { + compatible = "sandbox,hwspinlock"; + }; }; #include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 8fabe70a86..92c8ab508e 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -100,6 +100,7 @@ struct sandbox_state { ulong next_tag; /* Next address tag to allocate */ struct list_head mapmem_head; /* struct sandbox_mapmem_entry */ + bool hwspinlock; /* Hardware Spinlock status */ }; /* Minimum space we guarantee in the state FDT when calling read/write*/ diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 5a744f4791..f4a50d5df3 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -95,6 +95,8 @@ CONFIG_BOARD=y CONFIG_BOARD_SANDBOX=y CONFIG_PM8916_GPIO=y CONFIG_SANDBOX_GPIO=y +CONFIG_DM_HWSPINLOCK=y +CONFIG_HWSPINLOCK_SANDBOX=y CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y diff --git a/drivers/Kconfig b/drivers/Kconfig index 4ac823d962..e9fbadd13d 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -40,6 +40,8 @@ source "drivers/fpga/Kconfig" source "drivers/gpio/Kconfig" +source "drivers/hwspinlock/Kconfig" + source "drivers/i2c/Kconfig" source "drivers/input/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 55de10926e..c425831b58 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -113,4 +113,5 @@ obj-$(CONFIG_W1) += w1/ obj-$(CONFIG_W1_EEPROM) += w1-eeprom/ obj-$(CONFIG_MACH_PIC32) += ddr/microchip/ +obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/ endif diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig new file mode 100644 index 0000000000..de367fd2a9 --- /dev/null +++ b/drivers/hwspinlock/Kconfig @@ -0,0 +1,16 @@ +menu "Hardware Spinlock Support" + +config DM_HWSPINLOCK + bool "Enable U-Boot hardware spinlock support" + help + This option enables U-Boot hardware spinlock support + +config HWSPINLOCK_SANDBOX + bool "Enable Hardware Spinlock support for Sandbox" + depends on SANDBOX && DM_HWSPINLOCK + help + Enable hardware spinlock support in Sandbox. This is a dummy device that + can be probed and support all the methods of HWSPINLOCK, but does not + really do anything. + +endmenu diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile new file mode 100644 index 0000000000..2704d6814f --- /dev/null +++ b/drivers/hwspinlock/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved + +obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock-uclass.o +obj-$(CONFIG_HWSPINLOCK_SANDBOX) += sandbox_hwspinlock.o diff --git a/drivers/hwspinlock/hwspinlock-uclass.c b/drivers/hwspinlock/hwspinlock-uclass.c new file mode 100644 index 0000000000..195f079707 --- /dev/null +++ b/drivers/hwspinlock/hwspinlock-uclass.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include + +static inline const struct hwspinlock_ops * +hwspinlock_dev_ops(struct udevice *dev) +{ + return (const struct hwspinlock_ops *)dev->driver->ops; +} + +static int hwspinlock_of_xlate_default(struct hwspinlock *hws, + struct ofnode_phandle_args *args) +{ + if (args->args_count > 1) { + debug("Invaild args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (args->args_count) + hws->id = args->args[0]; + else + hws->id = 0; + + return 0; +} + +int hwspinlock_get_by_index(struct udevice *dev, int index, + struct hwspinlock *hws) +{ + int ret; + struct ofnode_phandle_args args; + struct udevice *dev_hws; + const struct hwspinlock_ops *ops; + + assert(hws); + hws->dev = NULL; + + ret = dev_read_phandle_with_args(dev, "hwlocks", "#hwlock-cells", 1, + index, &args); + if (ret) { + dev_dbg(dev, "%s: dev_read_phandle_with_args: err=%d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_ofnode(UCLASS_HWSPINLOCK, + args.node, &dev_hws); + if (ret) { + dev_dbg(dev, + "%s: uclass_get_device_by_of_offset failed: err=%d\n", + __func__, ret); + return ret; + } + + hws->dev = dev_hws; + + ops = hwspinlock_dev_ops(dev_hws); + + if (ops->of_xlate) + ret = ops->of_xlate(hws, &args); + else + ret = hwspinlock_of_xlate_default(hws, &args); + if (ret) + dev_dbg(dev, "of_xlate() failed: %d\n", ret); + + return ret; +} + +int hwspinlock_lock_timeout(struct hwspinlock *hws, unsigned int timeout) +{ + const struct hwspinlock_ops *ops; + ulong start; + int ret; + + assert(hws); + + if (!hws->dev) + return -EINVAL; + + ops = hwspinlock_dev_ops(hws->dev); + if (!ops->lock) + return -ENOSYS; + + start = get_timer(0); + do { + ret = ops->lock(hws->dev, hws->id); + if (!ret) + return ret; + + if (ops->relax) + ops->relax(hws->dev); + } while (get_timer(start) < timeout); + + return -ETIMEDOUT; +} + +int hwspinlock_unlock(struct hwspinlock *hws) +{ + const struct hwspinlock_ops *ops; + + assert(hws); + + if (!hws->dev) + return -EINVAL; + + ops = hwspinlock_dev_ops(hws->dev); + if (!ops->unlock) + return -ENOSYS; + + return ops->unlock(hws->dev, hws->id); +} + +static int hwspinlock_post_bind(struct udevice *dev) +{ +#if defined(CONFIG_NEEDS_MANUAL_RELOC) + struct hwspinlock_ops *ops = device_get_ops(dev); + static int reloc_done; + + if (!reloc_done) { + if (ops->lock) + ops->lock += gd->reloc_off; + if (ops->unlock) + ops->unlock += gd->reloc_off; + if (ops->relax) + ops->relax += gd->reloc_off; + + reloc_done++; + } +#endif + return 0; +} + +UCLASS_DRIVER(hwspinlock) = { + .id = UCLASS_HWSPINLOCK, + .name = "hwspinlock", + .post_bind = hwspinlock_post_bind, +}; diff --git a/drivers/hwspinlock/sandbox_hwspinlock.c b/drivers/hwspinlock/sandbox_hwspinlock.c new file mode 100644 index 0000000000..be920f5f99 --- /dev/null +++ b/drivers/hwspinlock/sandbox_hwspinlock.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include + +static int sandbox_lock(struct udevice *dev, int index) +{ + struct sandbox_state *state = state_get_current(); + + if (index != 0) + return -1; + + if (state->hwspinlock) + return -1; + + state->hwspinlock = true; + + return 0; +} + +static int sandbox_unlock(struct udevice *dev, int index) +{ + struct sandbox_state *state = state_get_current(); + + if (index != 0) + return -1; + + if (!state->hwspinlock) + return -1; + + state->hwspinlock = false; + + return 0; +} + +static const struct hwspinlock_ops sandbox_hwspinlock_ops = { + .lock = sandbox_lock, + .unlock = sandbox_unlock, +}; + +static const struct udevice_id sandbox_hwspinlock_ids[] = { + { .compatible = "sandbox,hwspinlock" }, + {} +}; + +U_BOOT_DRIVER(hwspinlock_sandbox) = { + .name = "hwspinlock_sandbox", + .id = UCLASS_HWSPINLOCK, + .of_match = sandbox_hwspinlock_ids, + .ops = &sandbox_hwspinlock_ops, +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index c91dca1f82..d0df2b505a 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -40,6 +40,7 @@ enum uclass_id { UCLASS_ETH, /* Ethernet device */ UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ + UCLASS_HWSPINLOCK, /* Hardware semaphores */ UCLASS_FIRMWARE, /* Firmware */ UCLASS_I2C, /* I2C bus */ UCLASS_I2C_EEPROM, /* I2C EEPROM device */ diff --git a/include/hwspinlock.h b/include/hwspinlock.h new file mode 100644 index 0000000000..99389c13c2 --- /dev/null +++ b/include/hwspinlock.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#ifndef _HWSPINLOCK_H_ +#define _HWSPINLOCK_H_ + +/** + * Implement a hwspinlock uclass. + * Hardware spinlocks are used to perform hardware protection of + * critical sections and synchronisation between multiprocessors. + */ + +struct udevice; + +/** + * struct hwspinlock - A handle to (allowing control of) a single hardware + * spinlock. + * + * @dev: The device which implements the hardware spinlock. + * @id: The hardware spinlock ID within the provider. + */ +struct hwspinlock { + struct udevice *dev; + unsigned long id; +}; + +#if CONFIG_IS_ENABLED(DM_HWSPINLOCK) + +/** + * hwspinlock_get_by_index - Get a hardware spinlock by integer index + * + * This looks up and request a hardware spinlock. The index is relative to the + * client device; each device is assumed to have n hardware spinlock associated + * with it somehow, and this function finds and requests one of them. + * + * @dev: The client device. + * @index: The index of the hardware spinlock to request, within the + * client's list of hardware spinlock. + * @hws: A pointer to a hardware spinlock struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int hwspinlock_get_by_index(struct udevice *dev, + int index, struct hwspinlock *hws); + +/** + * Lock the hardware spinlock + * + * @hws: A hardware spinlock struct that previously requested by + * hwspinlock_get_by_index + * @timeout: Timeout value in msecs + * @return: 0 if OK, -ETIMEDOUT if timeout, -ve on other errors + */ +int hwspinlock_lock_timeout(struct hwspinlock *hws, unsigned int timeout); + +/** + * Unlock the hardware spinlock + * + * @hws: A hardware spinlock struct that previously requested by + * hwspinlock_get_by_index + * @return: 0 if OK, -ve on error + */ +int hwspinlock_unlock(struct hwspinlock *hws); + +#else + +static inline int hwspinlock_get_by_index(struct udevice *dev, + int index, + struct hwspinlock *hws) +{ + return -ENOSYS; +} + +static inline int hwspinlock_lock_timeout(struct hwspinlock *hws, + int timeout) +{ + return -ENOSYS; +} + +static inline int hwspinlock_unlock(struct hwspinlock *hws) +{ + return -ENOSYS; +} + +#endif /* CONFIG_DM_HWSPINLOCK */ + +struct ofnode_phandle_args; + +/** + * struct hwspinlock_ops - Driver model hwspinlock operations + * + * The uclass interface is implemented by all hwspinlock devices which use + * driver model. + */ +struct hwspinlock_ops { + /** + * of_xlate - Translate a client's device-tree (OF) hardware specifier. + * + * The hardware core calls this function as the first step in + * implementing a client's hwspinlock_get_by_*() call. + * + * @hws: The hardware spinlock struct to hold the translation + * result. + * @args: The hardware spinlock specifier values from device tree. + * @return 0 if OK, or a negative error code. + */ + int (*of_xlate)(struct hwspinlock *hws, + struct ofnode_phandle_args *args); + + /** + * Lock the hardware spinlock + * + * @dev: hwspinlock Device + * @index: index of the lock to be used + * @return 0 if OK, -ve on error + */ + int (*lock)(struct udevice *dev, int index); + + /** + * Unlock the hardware spinlock + * + * @dev: hwspinlock Device + * @index: index of the lock to be unlocked + * @return 0 if OK, -ve on error + */ + int (*unlock)(struct udevice *dev, int index); + + /** + * Relax - optional + * Platform-specific relax method, called by hwspinlock core + * while spinning on a lock, between two successive call to + * lock + * + * @dev: hwspinlock Device + */ + void (*relax)(struct udevice *dev); +}; + +#endif /* _HWSPINLOCK_H_ */ diff --git a/test/dm/Makefile b/test/dm/Makefile index 213e0fda94..7355fe18e2 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_CLK) += clk.o obj-$(CONFIG_DM_ETH) += eth.o obj-$(CONFIG_FIRMWARE) += firmware.o obj-$(CONFIG_DM_GPIO) += gpio.o +obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o obj-$(CONFIG_DM_I2C) += i2c.o obj-$(CONFIG_LED) += led.o obj-$(CONFIG_DM_MAILBOX) += mailbox.o diff --git a/test/dm/hwspinlock.c b/test/dm/hwspinlock.c new file mode 100644 index 0000000000..09ec38b4f3 --- /dev/null +++ b/test/dm/hwspinlock.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Test that hwspinlock driver functions are called */ +static int dm_test_hwspinlock_base(struct unit_test_state *uts) +{ + struct sandbox_state *state = state_get_current(); + struct hwspinlock hws; + + ut_assertok(uclass_get_device(UCLASS_HWSPINLOCK, 0, &hws.dev)); + ut_assertnonnull(hws.dev); + ut_asserteq(false, state->hwspinlock); + + hws.id = 0; + ut_assertok(hwspinlock_lock_timeout(&hws, 1)); + ut_asserteq(true, state->hwspinlock); + + ut_assertok(hwspinlock_unlock(&hws)); + ut_asserteq(false, state->hwspinlock); + + ut_assertok(hwspinlock_lock_timeout(&hws, 1)); + ut_assertok(!hwspinlock_lock_timeout(&hws, 1)); + + ut_assertok(hwspinlock_unlock(&hws)); + ut_assertok(!hwspinlock_unlock(&hws)); + + return 0; +} + +DM_TEST(dm_test_hwspinlock_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); From patchwork Tue Nov 27 12:49:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 152122 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1221645ljp; Tue, 27 Nov 2018 04:52:32 -0800 (PST) X-Google-Smtp-Source: AFSGD/XpeItZfCWcpivHIz+HdNqSLA7L/waN4UIrY0ks9krRL3C25+O1Nz1MQk7eNxw/Ukjd7R5n X-Received: by 2002:a17:906:5d10:: with SMTP id g16-v6mr903446ejt.212.1543323152209; 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[81.169.180.215]) by mx.google.com with ESMTP id g5-v6si1933000ejp.46.2018.11.27.04.52.31; Tue, 27 Nov 2018 04:52:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=YBJtrHZF; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id D1283C22220; Tue, 27 Nov 2018 12:51:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E3F9AC222EA; Tue, 27 Nov 2018 12:50:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EF7B2C22283; Tue, 27 Nov 2018 12:50:15 +0000 (UTC) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by lists.denx.de (Postfix) with ESMTPS id 8B7E4C220EC for ; Tue, 27 Nov 2018 12:50:11 +0000 (UTC) Received: by mail-wm1-f66.google.com with SMTP id n133so5297067wmd.4 for ; Tue, 27 Nov 2018 04:50:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oLp9ZZs9aCvjbUr7WBcd79aLnWxjPpZLbs2+aMbjkOE=; b=YBJtrHZFpCVlMh3Lmf0IIbCOeUZv9wPhVAgVcFdoSmYU9o1UwCik/Dr48Vkz2Xn4h1 t58FTawzJDfNi2UPUW2A7JiA/EB1L/OVZ7z5rg9G51NyOUUhk3hsnoTnsz1UuO3ss3T/ qXzAbW0O4874orUfnhxcevA2aJzkVahIwhco0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oLp9ZZs9aCvjbUr7WBcd79aLnWxjPpZLbs2+aMbjkOE=; b=OwdGEalOX/M+VWAux5ZF5ahYpPbbPZcd2xkJRHBFrlu3MH2sT7YteEk4vKljGTxIel 8Z7fhg+tGJ3ayyS1lGn797WpwIvF5ZLZ6vynUKFuRa4t1gQhsQmSO8sKvCzp3IViU+// TxPnofOQPaB3xar5q9vt8ry0MWsWr75chRPZ3Uvj4GzjDXqhVjo/i+TLdEYNYj3sUIrJ R1cseQna8I1u+EBI+/YcgXsHADPZgKH4hjCqOWZIPL234bjYeLzJjQmCNvne6RB4RPFJ Ze3PTbgj6hpc5a7ZuX7aYoFU9fFrgCiGpTpgaCHuegY+yfVe353Wp5gaol4d2/CrtL7s bhrw== X-Gm-Message-State: AA+aEWZnYw6xoHqJv5yVHQSwBF5qHnohS20/ar+dUjQNmAh0/Se6bXba mxYvoP1Axfa/j5vQFgh8pCs7Z1HXZ0U= X-Received: by 2002:a1c:b687:: with SMTP id g129mr9506855wmf.59.1543323011216; Tue, 27 Nov 2018 04:50:11 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1087:3904:205d:1327:2414:27b8]) by smtp.gmail.com with ESMTPSA id p14sm3098056wrt.37.2018.11.27.04.50.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Nov 2018 04:50:10 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com, trini@konsulko.com Date: Tue, 27 Nov 2018 13:49:51 +0100 Message-Id: <20181127124953.4458-3-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181127124953.4458-1-benjamin.gaignard@st.com> References: <20181127124953.4458-1-benjamin.gaignard@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de Subject: [U-Boot] [PATCH v5 2/4] clk: stm32: add hardware spinlock clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Benjamin Gaignard Add hardware spinlock in the list of the clocks. Signed-off-by: Benjamin Gaignard Reviewed-by: Simon Glass Reviewed-by: Patrice Chotard --- drivers/clk/clk_stm32mp1.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 6a8c7b754f..b7c5d34fe0 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -104,6 +104,7 @@ #define RCC_MP_APB2ENSETR 0XA08 #define RCC_MP_APB3ENSETR 0xA10 #define RCC_MP_AHB2ENSETR 0xA18 +#define RCC_MP_AHB3ENSETR 0xA20 #define RCC_MP_AHB4ENSETR 0xA28 /* used for most of SELR register */ @@ -534,6 +535,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), From patchwork Tue Nov 27 12:49:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 152121 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1221594ljp; Tue, 27 Nov 2018 04:52:29 -0800 (PST) X-Google-Smtp-Source: AFSGD/WgY1qHk4B4OtJNPY2CTmSniwEI7CJF+HiCJziUO3AjMe/B50GNzyV30xVqLAA1o8mcb/oJ X-Received: by 2002:a50:98c5:: with SMTP id j63mr26155878edb.273.1543323149696; Tue, 27 Nov 2018 04:52:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543323149; cv=none; d=google.com; s=arc-20160816; b=RHAHt7tVteeLgb6LPtwZ52QnkNOMNXi51RYd88O7gvYHBUGOof27wsL/W8Ndg31hy6 LinLFHhNk71gPp8+qxUdEutuunmlFW4hxQ4Zz+2OyeMRW9c9w7zAS/Lqkt+hvEdmUv9g uop+pZyEkVwH5vCVJUfx2jWhsxr/9CoSI18eVRYNGeHhiVTYAhWFtNr0D4Bus8tCCwoC R8OOxuLTurixZVlcs+wyQt6SsuDn9J9TUA0X5toebcpuFSbr2PeH6Mukbwh3nE1lfh/G cN3HkdxLIBiigKjSpqt9uWPZZBXzIGXJCEq8BgNxFPLq+CRXbhmJMayGoPf+01ncXyf3 mt4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=QYn7m6BH31WJSFZAwoZUpvWA2AEZlG7H20+urwS80W8=; b=j2y6iFbchDiwJSzSk/NnHicU+buRmW/q/NMpa2FtLGvASnqu6jgrEVsWiirULDub0R jh0KkGndMTT26LLpHOVwxdmFJatGTrhRl5ktNmuoxBSP5GeH386uxLmLKgC4YAhxI75v D2maXXCW76DYPInx7oj89Lb+68ensT33Rb2mSyCuRivTWuRXyU4yEr2cgl/MKfIQCP/7 85eHowiosI4BXUlEwm9qCkPfWvJmz8w6xz0gIi7XEd3KGtSiF3rPBU+tmvZb+HY7BfHv h6MdBEGtmvGnK78/eV16P8HzoQpZoa1o7Axs8fkbPuCqfAvuLkdGziQWZOyCGO1Z0rJN YLzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="Nuy4fH/p"; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id n14si1871179edy.344.2018.11.27.04.52.29; Tue, 27 Nov 2018 04:52:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="Nuy4fH/p"; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 3696FC22271; Tue, 27 Nov 2018 12:51:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CDAC9C222BD; Tue, 27 Nov 2018 12:50:23 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 44C59C2224A; Tue, 27 Nov 2018 12:50:17 +0000 (UTC) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by lists.denx.de (Postfix) with ESMTPS id 8BDD5C222C0 for ; Tue, 27 Nov 2018 12:50:13 +0000 (UTC) Received: by mail-wm1-f66.google.com with SMTP id g67so8599897wmd.2 for ; Tue, 27 Nov 2018 04:50:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sOPemw7CQBPO+68fqz/LsUMUZWB/gj4l8Fem4wYOt3s=; b=Nuy4fH/pG4RPuSZiu/MS9/3djI0/fZ3SSgJAGniyT3fXbPcTMhxoCCaCA2bAhnA5ry dZFFwRT3JsM+IXpgIu+55qr0GYAKhNwJ+Nc7zc2cUlr9JXnauTRGzvu7stCcJpzPPAUO cAyPTKAkJyrUBRQHFmsRLuUMk4Q0ANj3qUUl0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sOPemw7CQBPO+68fqz/LsUMUZWB/gj4l8Fem4wYOt3s=; b=pSw7DQYr+11+APxCODNFR1yxzQMEJSVoCZJ1/4dqEK6o3AVipyHerrxF78nDk9cxx2 hsJwkKMYPDBt9nKextDJJ9X2RCFX+/l8YiiqDn/lekVR3KfvAcmiGH8BWzFZY1/zMdo0 e9/BgHwpUjSCuamgcKW5leMbUskpahIIDFmCBamra1uKChbL7LILxOqt1gee+lxBEhPZ gkT5AhZKkqZR3N7BswudfwvB+V0gBOpE2lfK5Vm3wP+6cwJi/RAruCa1YrM19weUs7gP d7NUItp2y34uCwVwxD6BmxyW+yo3sdqnQe5f7b/LUtXwLM6UwbEu3Y2reyj8j1nL4gMC xakA== X-Gm-Message-State: AA+aEWa5FVx9mhEhDWS1Vhb+35EuhG3vGsqM+ESDW+Y9m/SBaty12wmf VKcLONOc2J2PRC21J6n0U9TlWA== X-Received: by 2002:a1c:a05:: with SMTP id 5mr26249492wmk.49.1543323012986; Tue, 27 Nov 2018 04:50:12 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1087:3904:205d:1327:2414:27b8]) by smtp.gmail.com with ESMTPSA id p14sm3098056wrt.37.2018.11.27.04.50.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Nov 2018 04:50:12 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com, trini@konsulko.com Date: Tue, 27 Nov 2018 13:49:52 +0100 Message-Id: <20181127124953.4458-4-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181127124953.4458-1-benjamin.gaignard@st.com> References: <20181127124953.4458-1-benjamin.gaignard@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de, Benjamin Gaignard Subject: [U-Boot] [PATCH v5 3/4] hwspinlock: add stm32 hardware spinlock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Implement hardware spinlock support for STM32MP1. Signed-off-by: Benjamin Gaignard Reviewed-by: Simon Glass Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp157c-ed1.dts | 4 ++ arch/arm/dts/stm32mp157c.dtsi | 9 ++++ configs/stm32mp15_basic_defconfig | 2 + drivers/hwspinlock/Kconfig | 8 +++ drivers/hwspinlock/Makefile | 1 + drivers/hwspinlock/stm32_hwspinlock.c | 92 +++++++++++++++++++++++++++++++++++ 6 files changed, 116 insertions(+) create mode 100644 drivers/hwspinlock/stm32_hwspinlock.c diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index f8b7701167..fc277dd7d2 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -365,6 +365,10 @@ usb33d-supply = <&usb33>; }; +&hwspinlock { + status = "okay"; +}; + &usbphyc_port0 { phy-supply = <&vdd_usb>; vdda1v1-supply = <®11>; diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index 33c5981869..37cadfa30c 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -690,6 +690,15 @@ status = "disabled"; }; + hwspinlock: hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <1>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hwspinlock"; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 3bf7538089..c8409fd04e 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" CONFIG_STM32_ADC=y +CONFIG_DM_HWSPINLOCK=y +CONFIG_HWSPINLOCK_STM32=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig index de367fd2a9..96d4f5d6ca 100644 --- a/drivers/hwspinlock/Kconfig +++ b/drivers/hwspinlock/Kconfig @@ -13,4 +13,12 @@ config HWSPINLOCK_SANDBOX can be probed and support all the methods of HWSPINLOCK, but does not really do anything. +config HWSPINLOCK_STM32 + bool "Enable Hardware Spinlock support for STM32" + depends on ARCH_STM32MP && DM_HWSPINLOCK + help + Enable hardware spinlock support in STM32MP. Hardware spinlocks are + hardware mutex which provide a synchronisation mechanism for the + various processors on the SoC. + endmenu diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile index 2704d6814f..289b12a256 100644 --- a/drivers/hwspinlock/Makefile +++ b/drivers/hwspinlock/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock-uclass.o obj-$(CONFIG_HWSPINLOCK_SANDBOX) += sandbox_hwspinlock.o +obj-$(CONFIG_HWSPINLOCK_STM32) += stm32_hwspinlock.o diff --git a/drivers/hwspinlock/stm32_hwspinlock.c b/drivers/hwspinlock/stm32_hwspinlock.c new file mode 100644 index 0000000000..a32bde4906 --- /dev/null +++ b/drivers/hwspinlock/stm32_hwspinlock.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include + +#define STM32_MUTEX_COREID BIT(8) +#define STM32_MUTEX_LOCK_BIT BIT(31) +#define STM32_MUTEX_NUM_LOCKS 32 + +struct stm32mp1_hws_priv { + fdt_addr_t base; +}; + +static int stm32mp1_lock(struct udevice *dev, int index) +{ + struct stm32mp1_hws_priv *priv = dev_get_priv(dev); + u32 status; + + if (index >= STM32_MUTEX_NUM_LOCKS) + return -EINVAL; + + status = readl(priv->base + index * sizeof(u32)); + if (status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID)) + return -EBUSY; + + writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID, + priv->base + index * sizeof(u32)); + + status = readl(priv->base + index * sizeof(u32)); + if (status != (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID)) + return -EINVAL; + + return 0; +} + +static int stm32mp1_unlock(struct udevice *dev, int index) +{ + struct stm32mp1_hws_priv *priv = dev_get_priv(dev); + + if (index >= STM32_MUTEX_NUM_LOCKS) + return -EINVAL; + + writel(STM32_MUTEX_COREID, priv->base + index * sizeof(u32)); + + return 0; +} + +static int stm32mp1_hwspinlock_probe(struct udevice *dev) +{ + struct stm32mp1_hws_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret; + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + clk_free(&clk); + + return ret; +} + +static const struct hwspinlock_ops stm32mp1_hwspinlock_ops = { + .lock = stm32mp1_lock, + .unlock = stm32mp1_unlock, +}; + +static const struct udevice_id stm32mp1_hwspinlock_ids[] = { + { .compatible = "st,stm32-hwspinlock" }, + {} +}; + +U_BOOT_DRIVER(hwspinlock_stm32mp1) = { + .name = "hwspinlock_stm32mp1", + .id = UCLASS_HWSPINLOCK, + .of_match = stm32mp1_hwspinlock_ids, + .ops = &stm32mp1_hwspinlock_ops, + .probe = stm32mp1_hwspinlock_probe, + .priv_auto_alloc_size = sizeof(struct stm32mp1_hws_priv), +}; From patchwork Tue Nov 27 12:49:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 152123 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1221842ljp; Tue, 27 Nov 2018 04:52:47 -0800 (PST) X-Google-Smtp-Source: AJdET5dLJTc2rvE/YIjTZxZPQSC9D+29ud1yxKiKq0qRnK2pHuZju3YQ8uKaPAGLhzIH8Wk8ioYZ X-Received: by 2002:a17:906:9708:: with SMTP id k8-v6mr22754889ejx.205.1543323166982; Tue, 27 Nov 2018 04:52:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543323166; cv=none; d=google.com; s=arc-20160816; b=0KjzX9HtjSWq8+lDhKJWCJ/hkR6103NTttNFeJ26UXddhXFr29TUwv2Z5NzVa8dBaW V7FcuAk2fWNXkgHtEMdREodfthwyBAL1LDCqG3p2YR3tWlx/OTIwt+A3habUV8dV0z8Y b6RJJCWIcz4NkTjMKanM2mnbp0KN9sTr48FFw8F9P/ZMh/ahtF06goyNPnE3w4EdyzVU vMPyhBmivIpdaP38Ntsva0REGf9SBdr94GL9IpUTwcdCqt1wMiDkDTbTYJBJ+XKm1lzh yDHQexXOx4Mqyjmhvajmdd1iZaxSkk7wHBgmXb4u4p+wM7KwbUYMM7gPTjBEbgBNHWn0 p5Sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature; bh=8H4xG+VwSFJ5a7CRGR/smDbMluUOFxZxtaYCYcJJ75s=; b=1ABQ9Z9ynqND7oJ9a2/umQJG0v/9Yh+MCrXnvaAtDO56kOALwf9NNyhVXmuCT7ZC0j dIqKyJjdJ1MeiXv28sAIkd5uEkt4z5CPQWXZwz5nVenSpGGXfsdLJRwKkYT8Ufi3u2Ui NhmEoF+1kNUQxG/OgZQHMzH0iaU3oEsPmQXXvNEbtIOCw94nxFWkCO4QWbQzNowkH6QX wAsTwJttpNsh78k2PaHKYwf63G0CusVNTqaCpD6EXz0s1MNU9oIM4WPALUaUHThD71eo kMyzSPT+ytX1xby08Li6ylkmymEbEeHg1Hr4b3yChyxJMkXKpvWbyvA/pch/vtbGzKeI Vr1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=c9a5uyg1; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id h11si801910edw.123.2018.11.27.04.52.46; Tue, 27 Nov 2018 04:52:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=c9a5uyg1; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 884FCC222C0; Tue, 27 Nov 2018 12:51:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CD59EC222E7; Tue, 27 Nov 2018 12:50:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 59E78C22220; Tue, 27 Nov 2018 12:50:19 +0000 (UTC) Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by lists.denx.de (Postfix) with ESMTPS id 7A30CC222E2 for ; Tue, 27 Nov 2018 12:50:15 +0000 (UTC) Received: by mail-wr1-f65.google.com with SMTP id r10so22540759wrs.10 for ; Tue, 27 Nov 2018 04:50:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WWMCIyh/1tnrKtJsr1WR40GPCSUe2CSAco7WXy3DfX4=; b=c9a5uyg15dZzjqXNgtMdMrblovgL1vHITa4A1iIlRHqJuCp6D7JwY6/aYA+IxPYUef pVF/JyYDtv21H1LyCghEtPWcTK6Say/oQgHvrSq5yIfaJfyxtTBBGbF0G9NNK6dVIOmA 1HBL62Z4oqRWcR12rdzTwn+9ENfPo9EI3PeZA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WWMCIyh/1tnrKtJsr1WR40GPCSUe2CSAco7WXy3DfX4=; b=QFelNI1E7L05sSsWX7oDcYy1R8y6Vv1HjEJ0zBfvrVaRSUGv2oRFtxX3cW01HljVZe IlkZRvVfZetQTtJEpIVtUtBG8J+rc8f5w6AUw2lITKdA/zKk+CTcL6j0VpkYAv7HOaJm 2hvVkSjReW4zUWfyyIw2mrLffxK+ppnCEDU6rpAVKakuedi5R1FfyTzTfOsSk8HMIwH7 Bwp5F7tjc8/whQBzUmiHA2N4OrUWRvjUBY3lPL1Z4zKdw4n1ITMGOgxPNCFAoRIz4elK uC120CMFOaDrKNchsWWbN9yrZ4HZjsO7TYDLjyFcgo2DLlJv/VjZGdfynw0wDJN5NmQY 4HTg== X-Gm-Message-State: AA+aEWad6lHRCrbUXM9IzZ6fiY2MIpzdvq/qqGCg+cBUrFZ3avKlyrw5 uFSDx+ky7UM2yBde2/JQ1fz5QQ== X-Received: by 2002:adf:f189:: with SMTP id h9mr27308146wro.35.1543323015003; Tue, 27 Nov 2018 04:50:15 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1087:3904:205d:1327:2414:27b8]) by smtp.gmail.com with ESMTPSA id p14sm3098056wrt.37.2018.11.27.04.50.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Nov 2018 04:50:14 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com, trini@konsulko.com Date: Tue, 27 Nov 2018 13:49:53 +0100 Message-Id: <20181127124953.4458-5-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181127124953.4458-1-benjamin.gaignard@st.com> References: <20181127124953.4458-1-benjamin.gaignard@st.com> MIME-Version: 1.0 Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de, Benjamin Gaignard Subject: [U-Boot] [PATCH v5 4/4] pinctrl: stm32: make pinctrl use hwspinlock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard Reviewed-by: Simon Glass Reviewed-by: Patrice Chotard --- version 5: ²- rebased on top of master branch arch/arm/dts/stm32mp157c-ed1.dts | 4 ++++ drivers/pinctrl/pinctrl_stm32.c | 27 +++++++++++++++++++++++---- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index fc277dd7d2..7a9b742d36 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -369,6 +369,10 @@ status = "okay"; }; +&pinctrl { + hwlocks = <&hwspinlock 0>; +}; + &usbphyc_port0 { phy-supply = <&vdd_usb>; vdda1v1-supply = <®11>; diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 6d4117d941..bb63da3739 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -1,6 +1,7 @@ #include #include #include +#include #include #include #include @@ -14,8 +15,8 @@ DECLARE_GLOBAL_DATA_PTR; #define OTYPE_MSK 1 #define AFR_MASK 0xF -#ifndef CONFIG_SPL_BUILD struct stm32_pinctrl_priv { + struct hwspinlock hws; int pinctrl_ngpios; struct list_head gpio_dev; }; @@ -25,6 +26,8 @@ struct stm32_gpio_bank { struct list_head list; }; +#ifndef CONFIG_SPL_BUILD + #define MAX_PIN_PER_BANK 16 static char pin_name[PINNAME_SIZE]; @@ -166,6 +169,8 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, return 0; } +#endif + int stm32_pinctrl_probe(struct udevice *dev) { struct stm32_pinctrl_priv *priv = dev_get_priv(dev); @@ -198,21 +203,35 @@ int stm32_pinctrl_probe(struct udevice *dev) list_add_tail(&gpio_bank->list, &priv->gpio_dev); } + /* hwspinlock property is optional, just log the error */ + ret = hwspinlock_get_by_index(dev, 0, &priv->hws); + if (ret) + debug("%s: hwspinlock_get_by_index may have failed (%d)\n", + __func__, ret); + return 0; } -#endif static int stm32_gpio_config(struct gpio_desc *desc, const struct stm32_gpio_ctl *ctl) { struct stm32_gpio_priv *priv = dev_get_priv(desc->dev); struct stm32_gpio_regs *regs = priv->regs; + struct stm32_pinctrl_priv *ctrl_priv; + int ret; u32 index; if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 || ctl->pupd > 2 || ctl->speed > 3) return -EINVAL; + ctrl_priv = dev_get_priv(dev_get_parent(desc->dev)); + ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10); + if (ret == -ETIME) { + dev_err(desc->dev, "HWSpinlock timeout\n"); + return ret; + } + index = (desc->offset & 0x07) * 4; clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index, ctl->af << index); @@ -227,6 +246,8 @@ static int stm32_gpio_config(struct gpio_desc *desc, index = desc->offset; clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index); + hwspinlock_unlock(&ctrl_priv->hws); + return 0; } @@ -393,8 +414,6 @@ U_BOOT_DRIVER(pinctrl_stm32) = { .of_match = stm32_pinctrl_ids, .ops = &stm32_pinctrl_ops, .bind = dm_scan_fdt_dev, -#ifndef CONFIG_SPL_BUILD .probe = stm32_pinctrl_probe, .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv), -#endif };