From patchwork Tue Feb 8 15:18:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sankeerth Billakanti \(QUIC\)" X-Patchwork-Id: 540906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32210C433FE for ; Tue, 8 Feb 2022 15:19:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379750AbiBHPTa (ORCPT ); Tue, 8 Feb 2022 10:19:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379708AbiBHPTa (ORCPT ); Tue, 8 Feb 2022 10:19:30 -0500 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFB95C061579; Tue, 8 Feb 2022 07:19:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644333569; x=1675869569; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=AehZw/m0Nas6LkoMeQNIU5pK46BRtTYHOumWG56ikG0=; b=hgOJBvAlxmLb6nUD6tlDoriP0Zd2ycn9SAir6pqC6cSfeWj4D0Eg4wFK KYSTkDxIFzeamgFC9sywTM354BPXsFPDXyFRWwDQ7CvVaFCPQxgAEl2mD jWz0wK4TFL2MSSxvqYlk8X+B4mGsYhlVH0VdQ+JFjg3ALZry5FDJ8+14t c=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 08 Feb 2022 07:19:29 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 07:19:30 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 8 Feb 2022 07:19:28 -0800 Received: from sbillaka-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 8 Feb 2022 07:19:22 -0800 From: Sankeerth Billakanti To: , , , , , , , , , , , , , , , , CC: Sankeerth Billakanti , , , , Subject: [PATCH v2 3/4] drm/panel-edp: Add eDP sharp panel support Date: Tue, 8 Feb 2022 20:48:44 +0530 Message-ID: <1644333525-30920-4-git-send-email-quic_sbillaka@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644333525-30920-1-git-send-email-quic_sbillaka@quicinc.com> References: <1644333525-30920-1-git-send-email-quic_sbillaka@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the 14" sharp,lq140m1jw46 eDP panel. Signed-off-by: Sankeerth Billakanti --- Changes in v2: - add mode when not using hpd - add delays - put dt-bindings drivers/gpu/drm/panel/panel-edp.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c index a394a15..5d13ccc 100644 --- a/drivers/gpu/drm/panel/panel-edp.c +++ b/drivers/gpu/drm/panel/panel-edp.c @@ -1605,6 +1605,34 @@ static const struct panel_desc sharp_lq123p1jx31 = { }, }; +static const struct drm_display_mode sharp_lq140m1jw46_mode = { + .clock = 144370, + .hdisplay = 1920, + .hsync_start = 1920 + 48, + .hsync_end = 1920 + 48 + 32, + .htotal = 1920 + 48 + 32 + 80, + .vdisplay = 1080, + .vsync_start = 1080 + 3, + .vsync_end = 1080 + 3 + 5, + .vtotal = 1080 + 3 + 5 + 69, + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, +}; + +static const struct panel_desc sharp_lq140m1jw46 = { + .modes = &sharp_lq140m1jw46_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 309, + .height = 174, + }, + .delay = { + .hpd_absent = 80, + .enable = 50, + .unprepare = 500, + }, +}; + static const struct drm_display_mode starry_kr122ea0sra_mode = { .clock = 147000, .hdisplay = 1920, @@ -1719,6 +1747,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "sharp,lq123p1jx31", .data = &sharp_lq123p1jx31, }, { + .compatible = "sharp,lq140m1jw46", + .data = &sharp_lq140m1jw46, + }, { .compatible = "starry,kr122ea0sra", .data = &starry_kr122ea0sra, }, { From patchwork Tue Feb 8 15:18:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sankeerth Billakanti \(QUIC\)" X-Patchwork-Id: 540905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 072D8C433FE for ; Tue, 8 Feb 2022 15:21:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379787AbiBHPVl (ORCPT ); Tue, 8 Feb 2022 10:21:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230234AbiBHPVk (ORCPT ); Tue, 8 Feb 2022 10:21:40 -0500 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2CCAC061576; Tue, 8 Feb 2022 07:21:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644333700; x=1675869700; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=ZLy+VydtbyF6fTJrG/RozIsN85Y7hFPmu++UBQG8hPc=; b=gDKHFg22HCSKZ+v8QVAgHmw+lfZFlzrMD7kBMf5hTkhgcrSsk73jHCAf Y5KJZFpNN1EV5ijqzDT1xS7FGx1hssrKHXDXkr4P1Y2vJsPQQOhw2wx5/ WOz1ugRBFAC+ECYwnICBRaA1KhFKLU/WqR6osiYtWB5Mv6Lxj6SMpnyUx E=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-01.qualcomm.com with ESMTP; 08 Feb 2022 07:19:37 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 07:19:36 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 8 Feb 2022 07:19:36 -0800 Received: from sbillaka-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 8 Feb 2022 07:19:30 -0800 From: Sankeerth Billakanti To: , , , , , , , , , , , , , , , , CC: Sankeerth Billakanti , , , , Subject: [PATCH v2 4/4] drm/msm/dp: Add driver support to utilize drm panel Date: Tue, 8 Feb 2022 20:48:45 +0530 Message-ID: <1644333525-30920-5-git-send-email-quic_sbillaka@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644333525-30920-1-git-send-email-quic_sbillaka@quicinc.com> References: <1644333525-30920-1-git-send-email-quic_sbillaka@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support in the DP driver to utilize the custom eDP panels from drm/panels. An eDP panel is always connected to the platform. So, the eDP connector can be reported as always connected. The display mode will be sourced from the panel. The panel mode will be set after the link training is completed. The eDP driver needs to register for IRQ_HPD only. This support will be added later. Signed-off-by: Sankeerth Billakanti --- drivers/gpu/drm/msm/dp/dp_display.c | 8 ++++++ drivers/gpu/drm/msm/dp/dp_drm.c | 54 +++++++++++++++++++++++++++++++++---- drivers/gpu/drm/msm/dp/dp_parser.h | 3 +++ 3 files changed, 60 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 7cc4d21..410fda4 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1513,6 +1513,10 @@ int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder) return -EINVAL; } + /* handle eDP on */ + if (dp->connector_type == DRM_MODE_CONNECTOR_eDP) + dp_hpd_plug_handle(dp_display, 0); + mutex_lock(&dp_display->event_mutex); /* stop sentinel checking */ @@ -1577,6 +1581,10 @@ int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder) dp_display = container_of(dp, struct dp_display_private, dp_display); + /* handle edp off */ + if (dp->connector_type == DRM_MODE_CONNECTOR_eDP) + dp_hpd_unplug_handle(dp_display, 0); + mutex_lock(&dp_display->event_mutex); /* stop sentinel checking */ diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index d4d360d..12fa8c1 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -39,6 +39,10 @@ static enum drm_connector_status dp_connector_detect(struct drm_connector *conn, dp = to_dp_connector(conn)->dp_display; + /* eDP is always connected */ + if (dp->connector_type == DRM_MODE_CONNECTOR_eDP) + return connector_status_connected; + DRM_DEBUG_DP("is_connected = %s\n", (dp->is_connected) ? "true" : "false"); @@ -123,6 +127,35 @@ static enum drm_mode_status dp_connector_mode_valid( return dp_display_validate_mode(dp_disp, mode->clock); } +static int edp_connector_get_modes(struct drm_connector *connector) +{ + struct msm_dp *dp; + + if (!connector) + return 0; + + dp = to_dp_connector(connector)->dp_display; + + return drm_bridge_get_modes(dp->panel_bridge, connector); +} + +static enum drm_mode_status edp_connector_mode_valid( + struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct msm_dp *dp; + + if (!connector) + return 0; + + dp = to_dp_connector(connector)->dp_display; + + if (mode->clock > EDP_MAX_PIXEL_CLK_KHZ) + return MODE_BAD; + + return MODE_OK; +} + static const struct drm_connector_funcs dp_connector_funcs = { .detect = dp_connector_detect, .fill_modes = drm_helper_probe_single_connector_modes, @@ -137,6 +170,12 @@ static const struct drm_connector_helper_funcs dp_connector_helper_funcs = { .mode_valid = dp_connector_mode_valid, }; +static const struct drm_connector_helper_funcs edp_connector_helper_funcs = { + .get_modes = edp_connector_get_modes, + .mode_valid = edp_connector_mode_valid, + +}; + /* connector initialization */ struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display) { @@ -160,12 +199,17 @@ struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display) if (ret) return ERR_PTR(ret); - drm_connector_helper_add(connector, &dp_connector_helper_funcs); + if (dp_display->connector_type == DRM_MODE_CONNECTOR_eDP) { + drm_connector_helper_add(connector, + &edp_connector_helper_funcs); + } else { + drm_connector_helper_add(connector, &dp_connector_helper_funcs); - /* - * Enable HPD to let hpd event is handled when cable is connected. - */ - connector->polled = DRM_CONNECTOR_POLL_HPD; + /* + * Enable HPD to let hpd event is handled when cable is connected. + */ + connector->polled = DRM_CONNECTOR_POLL_HPD; + } drm_connector_attach_encoder(connector, dp_display->encoder); diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index 3172da0..58c4f27 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -17,6 +17,9 @@ #define DP_MAX_PIXEL_CLK_KHZ 675000 #define DP_MAX_NUM_DP_LANES 4 +/* Maximum validated clock */ +#define EDP_MAX_PIXEL_CLK_KHZ 285550 + enum dp_pm_type { DP_CORE_PM, DP_CTRL_PM,