From patchwork Tue Feb 8 15:35:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 540827 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02337C433F5 for ; Tue, 8 Feb 2022 15:35:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1380670AbiBHPfp (ORCPT ); Tue, 8 Feb 2022 10:35:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380673AbiBHPfk (ORCPT ); Tue, 8 Feb 2022 10:35:40 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14CD0C061576; Tue, 8 Feb 2022 07:35:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644334540; x=1675870540; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=7ZQlDQCf+14boNm4JKmpv2b7alWc5ogeZKII3lt9FVc=; b=ATJC8mKoYZXRWX5UewVay5NGs1EZLo73ao02c2SnegWqSNAinFaScGYK GUd7y7bgn8gBitBwWbLFi0Tj+T1MiQdwRLHCjTmSDdcp2xrnC31jSnrDf sY1O+A8/YNPAEsxkmkiNHg2kkwgScLt9Es/9L7K4V94WVRwv7AZJtmx7D 4=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 08 Feb 2022 07:35:39 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 07:35:40 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 8 Feb 2022 07:35:39 -0800 Received: from kathirav-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 8 Feb 2022 07:35:36 -0800 From: Kathiravan T To: , , , , , CC: Kathiravan T Subject: [PATCH 1/2] arm64: dts: qcom: ipq8074: enable the GICv2m support Date: Tue, 8 Feb 2022 21:05:24 +0530 Message-ID: <1644334525-11577-2-git-send-email-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644334525-11577-1-git-send-email-quic_kathirav@quicinc.com> References: <1644334525-11577-1-git-send-email-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GIC used in the IPQ8074 SoCs has one instance of the GICv2m extension, which supports upto 32 MSI interrupts. Lets add support for the same. Signed-off-by: Kathiravan T --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 26ba7ce9222c..7b0258407d10 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -620,9 +620,18 @@ intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; + #address-cells = <1>; + #size-cells = <1>; interrupt-controller; #interrupt-cells = <0x3>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + ranges = <0 0xb00a000 0xffd>; + + v2m@0 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xffd>; + }; }; timer { From patchwork Tue Feb 8 15:35:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 540825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8D74C4332F for ; Tue, 8 Feb 2022 15:37:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1380986AbiBHPhr (ORCPT ); Tue, 8 Feb 2022 10:37:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381047AbiBHPhq (ORCPT ); Tue, 8 Feb 2022 10:37:46 -0500 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D8A2C0612C2; Tue, 8 Feb 2022 07:37:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644334664; x=1675870664; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=GyEkYt3zPrC9WZkiqFj1y/fTCDu3JwZi72OcFHHW+0I=; b=HJOTMw/53m8XaU4bsqCMp26LKrICQ9FWGCGfJRWsP/ZCiWNfM37cnCqW m4IVWO+rh9TxHH4rvUQ3GJJCA06+1lrH2Dorr3m2/t4StHuMK4O8Mmcj9 7ck9rT2dbIxEaLM9KfH6w4YX7955KOFTDly0FCxsXBceBMiZcTDKcgjoR Q=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-01.qualcomm.com with ESMTP; 08 Feb 2022 07:35:42 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 07:35:42 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 8 Feb 2022 07:35:42 -0800 Received: from kathirav-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 8 Feb 2022 07:35:39 -0800 From: Kathiravan T To: , , , , , CC: Kathiravan T Subject: [PATCH 2/2] arm64: dts: qcom: ipq6018: enable the GICv2m support Date: Tue, 8 Feb 2022 21:05:25 +0530 Message-ID: <1644334525-11577-3-git-send-email-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644334525-11577-1-git-send-email-quic_kathirav@quicinc.com> References: <1644334525-11577-1-git-send-email-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GIC used in the IPQ6018 SoCs has one instance of the GICv2m extension, which supports upto 32 MSI interrupts. Lets add support for the same. Signed-off-by: Kathiravan T --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 66ec5615651d..b8171548f0e1 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -373,6 +373,8 @@ intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; + #address-cells = <2>; + #size-cells = <2>; interrupt-controller; #interrupt-cells = <0x3>; reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ @@ -380,6 +382,13 @@ <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ interrupts = ; + ranges = <0 0 0 0xb00a000 0 0xffd>; + + v2m@0 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x0 0x0 0xffd>; + }; }; pcie_phy: phy@84000 {