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[209.132.180.67]) by mx.google.com with ESMTP id 28si795694pgw.364.2018.11.26.08.52.00; Mon, 26 Nov 2018 08:52:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726457AbeK0Dqi (ORCPT + 32 others); Mon, 26 Nov 2018 22:46:38 -0500 Received: from foss.arm.com ([217.140.101.70]:42520 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726203AbeK0Dqi (ORCPT ); Mon, 26 Nov 2018 22:46:38 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3A2C015AD; Mon, 26 Nov 2018 08:51:58 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0A68A3F59C; Mon, 26 Nov 2018 08:51:58 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 83F711AE0839; Mon, 26 Nov 2018 16:52:15 +0000 (GMT) From: Will Deacon To: corbet@lwn.net Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Will Deacon , Benjamin Herrenschmidt , Arnd Bergmann , David Laight , Alan Stern , Peter Zijlstra , "Paul E. McKenney" Subject: [PATCH] docs/memory-barriers.txt: Enforce heavy ordering for port I/O accesses Date: Mon, 26 Nov 2018 16:52:14 +0000 Message-Id: <1543251134-29867-1-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org David Laight explains: | A long time ago there was a document from Intel that said that | inb/outb weren't necessarily synchronised wrt memory accesses. | (Might be P-pro era). However no processors actually behaved that | way and more recent docs say that inb/outb are fully ordered. This also reflects the situation on other architectures, the the port accessor macros tend to be implemented in terms of readX/writeX. Update Documentation/memory-barriers.txt to reflect reality. Cc: Benjamin Herrenschmidt Cc: Arnd Bergmann Cc: David Laight Cc: Alan Stern Cc: Peter Zijlstra Cc: "Paul E. McKenney" Signed-off-by: Will Deacon --- Just remembered I had this patch kicking around in my tree... Documentation/memory-barriers.txt | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) -- 2.1.4 diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index c1d913944ad8..0c34c5dac138 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -2619,10 +2619,8 @@ functions: intermediary bridges (such as the PCI host bridge) may not fully honour that. - They are guaranteed to be fully ordered with respect to each other. - - They are not guaranteed to be fully ordered with respect to other types of - memory and I/O operation. + They are guaranteed to be fully ordered with respect to each other and + also with respect to other types of memory and I/O operation. (*) readX(), writeX():