From patchwork Sun Feb 6 13:58:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 541006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92EDEC43217 for ; Sun, 6 Feb 2022 14:04:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237838AbiBFOEN (ORCPT ); Sun, 6 Feb 2022 09:04:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235128AbiBFOEM (ORCPT ); Sun, 6 Feb 2022 09:04:12 -0500 Received: from smtp-relay-internal-0.canonical.com (smtp-relay-internal-0.canonical.com [185.125.188.122]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C68A7C043184 for ; Sun, 6 Feb 2022 06:04:10 -0800 (PST) Received: from mail-wm1-f70.google.com (mail-wm1-f70.google.com [209.85.128.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id 7817C3FE4B for ; Sun, 6 Feb 2022 13:58:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1644155893; bh=LVkBfcJOPMoVnmBu9J91WfcjMU5SYQeGsSEAA+YrpAs=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AryksRk+2D1zcf/s3e1Cc4eEvYNcB/g713wOdiXa95tLNeOeadiuZamVXLs3glpjU IYPRrR1bjTxMjYJ7VTQl2Yfcda3dhFU4aSMf3xpV0CfF+Vw2vHBUG6Z0UNSX2Juk8V xnD2YrhELNHpLZwyYIup2Qc210nH/5y5ouU3b/pgY6TH4sjpI6aj/naM2Vf/8toGv0 zN31A0MfSKoOKEg8KHa6JLbQK0o/KrM9tf4wlLzVXFKqCh69UYtr1+EPmxgOGV9Uot 0hFfm8ZTMBYnJzn/cBowcQw4AZv96DHf2TJhg31C/j8YE9pK/TKIMscwmS4raqpZG6 0zIMzHLXWgbDQ== Received: by mail-wm1-f70.google.com with SMTP id t2-20020a7bc3c2000000b003528fe59cb9so4235774wmj.5 for ; Sun, 06 Feb 2022 05:58:13 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LVkBfcJOPMoVnmBu9J91WfcjMU5SYQeGsSEAA+YrpAs=; b=iHaErHs197rfQYZM8U4Y3YPlJetvvAuutDLFX2MYiO5oh8xBzSIUpguxBHwhuOwpC5 N7bYzAUg6DJFvbstt/47M5EI20lq9RHlLKGyUEuNlloQ329wqW08g8yRJkWOHqMbEks5 yoiRmPjsENEX+QBmCvknQgHVYoBWirzRQ2AzGWPgscJNHLLozMVUwvRdtacQXuuvtENj Gqre38rtb7pKCyyTxgW+PzcKXeKI2So0caefeTL2isAAHMG9h174V9gi5O6DcWvM3VF2 xm5CmASStQYMACtLIjNgHPyx7mjm+MSOYUTgaqphAnpxd9Whzm9zxsO/B21Ebk9EkxBD og3Q== X-Gm-Message-State: AOAM530jsRKAZmB61wP1Kf6KA4zC92OKtMS7ygTjZLVd0aGRcdMnAJbb XN64kOQuqi1nfS+Og6W3hFCPeczOtSAc+ME8ovpb7jNqlWwfuNI1cIjpdtiRwj/c0Qzw4BuV4Bl MZa69acDPV0/qIqCO8X/G0dFPQGQ4MWv6Ar36 X-Received: by 2002:a05:600c:1f06:: with SMTP id bd6mr10672610wmb.117.1644155893040; Sun, 06 Feb 2022 05:58:13 -0800 (PST) X-Google-Smtp-Source: ABdhPJxYAnQuw3LCcmq/e4CR+JXZGoGIgFwhwnXz5ZwEcWLTAFqDgscNcdXs2ZRPGLL13HutYDee4Q== X-Received: by 2002:a05:600c:1f06:: with SMTP id bd6mr10672589wmb.117.1644155892812; Sun, 06 Feb 2022 05:58:12 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id e9sm8296888wrg.60.2022.02.06.05.58.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 05:58:12 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Lukasz Luba , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/8] dt-bindings: memory: lpddr2-timings: convert to dtschema Date: Sun, 6 Feb 2022 14:58:00 +0100 Message-Id: <20220206135807.211767-2-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> References: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Convert the LPDDR2 memory timings bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Osipenko --- .../ddr/jedec,lpddr2-timings.yaml | 135 ++++++++++++++++++ .../memory-controllers/ddr/jedec,lpddr2.yaml | 6 +- .../memory-controllers/ddr/lpddr2-timings.txt | 52 ------- 3 files changed, 137 insertions(+), 56 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml new file mode 100644 index 000000000000..f3e62ee07126 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR2 SDRAM AC timing parameters for a given speed-bin + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + const: jedec,lpddr2-timings + + max-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Maximum DDR clock frequency for the speed-bin, in Hz. + + min-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Minimum DDR clock frequency for the speed-bin, in Hz. + + tCKESR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in pico seconds. + + tDQSCK-max: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + DQS output data access time from CK_t/CK_c in pico seconds. + + tDQSCK-max-derated: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + DQS output data access time from CK_t/CK_c, temperature de-rated, in pico + seconds. + + tFAW: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Four-bank activate window in pico seconds. + + tRAS-max-ns: + description: | + Row active time in nano seconds. + + tRAS-min: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row active time in pico seconds. + + tRCD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + RAS-to-CAS delay in pico seconds. + + tRPab: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row precharge time (all banks) in pico seconds. + + tRRD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Active bank A to active bank B in pico seconds. + + tRTP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal READ to PRECHARGE command delay in pico seconds. + + tWR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WRITE recovery time in pico seconds. + + tWTR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal WRITE-to-READ command delay in pico seconds. + + tXP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Exit power-down to next valid command delay in pico seconds. + + tZQCL: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Long calibration time in pico seconds. + + tZQCS: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Short calibration time in pico seconds. + + tZQinit: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Initialization calibration time in pico seconds. + +required: + - compatible + - min-freq + - max-freq + +additionalProperties: false + +examples: + - | + timings { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tRAS-max-ns = <70000>; + tRAS-min = <42000>; + tRPab = <21000>; + tRCD = <18000>; + tRRD = <10000>; + tRTP = <7500>; + tWR = <15000>; + tWTR = <7500>; + tXP = <7500>; + tZQCL = <360000>; + tZQCS = <90000>; + tZQinit = <1000000>; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml index 25ed0266f6dd..2d8a701e2a05 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml @@ -142,14 +142,12 @@ properties: patternProperties: "^lpddr2-timings": - type: object + $ref: jedec,lpddr2-timings.yaml description: | The lpddr2 node may have one or more child nodes of type "lpddr2-timings". "lpddr2-timings" provides AC timing parameters of the device for a given speed-bin. The user may provide the timings for as many - speed-bins as is required. Please see Documentation/devicetree/ - bindings/memory-controllers/ddr/lpddr2-timings.txt for more information - on "lpddr2-timings". + speed-bins as is required. required: - compatible diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt deleted file mode 100644 index 9ceb19e0c7fd..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt +++ /dev/null @@ -1,52 +0,0 @@ -* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin - -Required properties: -- compatible : Should be "jedec,lpddr2-timings" -- min-freq : minimum DDR clock frequency for the speed-bin. Type is -- max-freq : maximum DDR clock frequency for the speed-bin. Type is - -Optional properties: - -The following properties represent AC timing parameters from the memory -data-sheet of the device for a given speed-bin. All these properties are -of type and the default unit is ps (pico seconds). Parameters with -a different unit have a suffix indicating the unit such as 'tRAS-max-ns' -- tRCD -- tWR -- tRAS-min -- tRRD -- tWTR -- tXP -- tRTP -- tDQSCK-max -- tFAW -- tZQCS -- tZQinit -- tRPab -- tZQCL -- tCKESR -- tRAS-max-ns -- tDQSCK-max-derated - -Example: - -timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <400000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; -}; From patchwork Sun Feb 6 13:58:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 541005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB5FDC4167D for ; Sun, 6 Feb 2022 14:04:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234263AbiBFOEP (ORCPT ); Sun, 6 Feb 2022 09:04:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239564AbiBFOEP (ORCPT ); Sun, 6 Feb 2022 09:04:15 -0500 Received: from smtp-relay-internal-0.canonical.com (smtp-relay-internal-0.canonical.com [185.125.188.122]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6FA9C043184 for ; Sun, 6 Feb 2022 06:04:12 -0800 (PST) Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id 95BFD40327 for ; Sun, 6 Feb 2022 13:58:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1644155894; bh=lOiKlVY+li7+FmiBN2L8P4Y/x6OELAmIkj/zsUkdPsw=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=k0Rfp2/5WDHPc0bLLLn9cyz/70mefXYyLY9R2lBhGUcQ+7JRt1S4GBFanY9On9+f/ 5iKA39yR1QBUkcndsZuqkRGKe6UduOCqixw9WtxjdPQNlxMfQRJ+sb9wLRgstZnvPr FwK76U9+/Nq8z1rhX3Bx3eHxxoaZ8ilLtUcfgSKbq9pUo6y5CYfOlDLvpGHnmOCeU6 BON1Qj2isCQ+qYwKIFXYXc1VNvajneSE9jBi7J1eBNhbNjKCHuGETfHxAQZKgPZhj9 imvmcKoeG33/O6sHRm1dSaKxWvoLTf2dkrH47KISihGf0WxjwqiC9zHVd7t4HSS+Mp 0qhnO18k76Kug== Received: by mail-wm1-f71.google.com with SMTP id i8-20020a1c3b08000000b0037bb9f6feeeso1552984wma.5 for ; Sun, 06 Feb 2022 05:58:14 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lOiKlVY+li7+FmiBN2L8P4Y/x6OELAmIkj/zsUkdPsw=; b=6UqODeBz7l/7T3QIY+TPgfvxD5q9TTBNklC3C0jKpVTj6syaZSJXkqbrKGZ/i0jnIJ 1H3P0dYZRQob9zr+Kn9vlW5q6cKxLC9dScfoG/XjThcFJnNi6cEe0n2xJurHWrEhhwmT Jwy40sKxD0NGnObg4x6/nh44juUsPKQF0OsY5de7FJ2RHP3MQKxFJ40A993WSPDwij4C RRXBbDZPPbqYzncy8y0NHwMLjkAaqV3fXUo3n3CWAOBODr4E669X2238lf/t3n1KLNha kKUmGdqFcrNg0bA4qG+sjjhKVfqpL7cpTTEEwHbg/2Nfu9zYknutM25zJPF8T/cshYRG yyDA== X-Gm-Message-State: AOAM530kYW4jR/d9ZRFoYTpqO9n4/qBEBtjE31bLwV1Cx6H/TDieuYpV gV5A+1/wKDPbeqQVNfEtrqx3vfVN3HCx1KWIPDH0kh0g2VR4FZBiTiFmNyq/gXYNuAS0wvWAfqw Dokxz0KGLLIC6SpFvoHcEK9be2nSo43XWQiuG X-Received: by 2002:a1c:a187:: with SMTP id k129mr10736764wme.194.1644155894249; Sun, 06 Feb 2022 05:58:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJwlhe4nNbdnLxL2YSPguLC5yr1KsrO1jPoWlnLroSOGauoLKGrgo4Z8u8tDCDm7WLYdWBcOgw== X-Received: by 2002:a1c:a187:: with SMTP id k129mr10736749wme.194.1644155894090; Sun, 06 Feb 2022 05:58:14 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id e9sm8296888wrg.60.2022.02.06.05.58.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 05:58:13 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Lukasz Luba , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 2/8] dt-bindings: memory: lpddr3-timings: convert to dtschema Date: Sun, 6 Feb 2022 14:58:01 +0100 Message-Id: <20220206135807.211767-3-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> References: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Convert the LPDDR3 memory timings bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Osipenko --- .../ddr/jedec,lpddr3-timings.yaml | 153 ++++++++++++++++++ .../memory-controllers/ddr/lpddr3-timings.txt | 58 ------- 2 files changed, 153 insertions(+), 58 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml new file mode 100644 index 000000000000..98bc219e8a25 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR3 SDRAM AC timing parameters for a given speed-bin + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + const: jedec,lpddr3-timings + + reg: + maxItems: 1 + description: | + Maximum DDR clock frequency for the speed-bin, in Hz. + + min-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Minimum DDR clock frequency for the speed-bin, in Hz. + + tCKE: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds. + + tCKESR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in pico seconds. + + tFAW: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Four-bank activate window in pico seconds. + + tMRD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Mode register set command delay in pico seconds. + + tR2R-C2C: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Additional READ-to-READ delay in chip-to-chip cases in pico seconds. + + tRAS: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row active time in pico seconds. + + tRC: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + ACTIVATE-to-ACTIVATE command period in pico seconds. + + tRCD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + RAS-to-CAS delay in pico seconds. + + tRFC: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Refresh Cycle time in pico seconds. + + tRPab: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row precharge time (all banks) in pico seconds. + + tRPpb: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row precharge time (single banks) in pico seconds. + + tRRD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Active bank A to active bank B in pico seconds. + + tRTP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal READ to PRECHARGE command delay in pico seconds. + + tW2W-C2C: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds. + + tWR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WRITE recovery time in pico seconds. + + tWTR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal WRITE-to-READ command delay in pico seconds. + + tXP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Exit power-down to next valid command delay in pico seconds. + + tXSR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SELF REFRESH exit to next valid command delay in pico seconds. + +required: + - compatible + - min-freq + - reg + +additionalProperties: false + +examples: + - | + lpddr3 { + #address-cells = <1>; + #size-cells = <0>; + + timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; + min-freq = <100000000>; + tCKE = <3750>; + tCKESR = <3750>; + tFAW = <25000>; + tMRD = <7000>; + tR2R-C2C = <0>; + tRAS = <23000>; + tRC = <33750>; + tRCD = <10000>; + tRFC = <65000>; + tRPab = <12000>; + tRPpb = <12000>; + tRRD = <6000>; + tRTP = <3750>; + tW2W-C2C = <0>; + tWR = <7500>; + tWTR = <3750>; + tXP = <3750>; + tXSR = <70000>; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt deleted file mode 100644 index 84705e50a3fd..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt +++ /dev/null @@ -1,58 +0,0 @@ -* AC timing parameters of LPDDR3 memories for a given speed-bin. - -The structures are based on LPDDR2 and extended where needed. - -Required properties: -- compatible : Should be "jedec,lpddr3-timings" -- min-freq : minimum DDR clock frequency for the speed-bin. Type is -- reg : maximum DDR clock frequency for the speed-bin. Type is - -Optional properties: - -The following properties represent AC timing parameters from the memory -data-sheet of the device for a given speed-bin. All these properties are -of type and the default unit is ps (pico seconds). -- tRFC -- tRRD -- tRPab -- tRPpb -- tRCD -- tRC -- tRAS -- tWTR -- tWR -- tRTP -- tW2W-C2C -- tR2R-C2C -- tFAW -- tXSR -- tXP -- tCKE -- tCKESR -- tMRD - -Example: - -timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { - compatible = "jedec,lpddr3-timings"; - reg = <800000000>; /* workaround: it shows max-freq */ - min-freq = <100000000>; - tRFC = <65000>; - tRRD = <6000>; - tRPab = <12000>; - tRPpb = <12000>; - tRCD = <10000>; - tRC = <33750>; - tRAS = <23000>; - tWTR = <3750>; - tWR = <7500>; - tRTP = <3750>; - tW2W-C2C = <0>; - tR2R-C2C = <0>; - tFAW = <25000>; - tXSR = <70000>; - tXP = <3750>; - tCKE = <3750>; - tCKESR = <3750>; - tMRD = <7000>; -}; From patchwork Sun Feb 6 13:58:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 540523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0875CC4167E for ; Sun, 6 Feb 2022 14:04:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238117AbiBFOEQ (ORCPT ); Sun, 6 Feb 2022 09:04:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240173AbiBFOEP (ORCPT ); Sun, 6 Feb 2022 09:04:15 -0500 Received: from smtp-relay-internal-0.canonical.com (smtp-relay-internal-0.canonical.com [185.125.188.122]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7300C043185 for ; Sun, 6 Feb 2022 06:04:13 -0800 (PST) Received: from mail-wm1-f70.google.com (mail-wm1-f70.google.com [209.85.128.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id 0AA0B3F32B for ; Sun, 6 Feb 2022 13:58:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1644155896; bh=rFw9l+85dJtOxzK1IePAzxypjCG9mduHp5NIQ70SgQY=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=k9IVOEpp+QjShU0hv9yfDtjs+2u4p6QaepxjLZS6Ej7BzDPrcYGY+HXlVQer3F03E eIk0vloihPLNmw4TjHUl9qS6D2rPGOZD69riGEFmzqwvsFMX0tUPTPYKkx7q6uIQ6t 93jixoe0+HYHRi//q4bZyh3dAnFRLH598611zVh4tVx0F3h7dzy0e0ogV+oqaXQUL2 jIha36EXZUIM+XVWS9XMnD1JrrtX2RGrUP7mGxwKh4QV9uR28s7a1EyCmSTAYl+WWl QnwiKd7TssWT/84ynyJeeC2uN4kpXoQ1yFvLvxuqFOtSnCFDiz2tewhjp72Yaiuz/o 5oaD1s+7ZHw5w== Received: by mail-wm1-f70.google.com with SMTP id s187-20020a1ca9c4000000b0037bb8547d64so1850972wme.0 for ; Sun, 06 Feb 2022 05:58:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rFw9l+85dJtOxzK1IePAzxypjCG9mduHp5NIQ70SgQY=; b=b1BbtFH38VTIGoxQ8leKcTkTnNQfMT7MeC9jlVUJHiKYNIP5xa42QPCg1iECZvz5Lw pkugo492EdZLU9W9KXMIPaGCcNa0ynRVyLLaHtQS30PJ8AQ78FX3bPdn90ml+/xWZbJw 97S6UiSTd/pWfMnRzrp3pRCh+bgumLK5XVgir5UU1C6dVMxClmerptprZFXQsF3fOEeF Fj4FpKnbJ13guizJVG8QW3bTNL0/8L3IrXNPaFjOF2HsBLxpdBoX/zYXlVD8eoGAvvBX OfRxPSDTQjBb5WwsItfs87scePzpcktu1WKV8nyh7DUJLYhZKq5b07LJq5XzwEOsgD4I ZGtg== X-Gm-Message-State: AOAM532LmTj8X2Kmc5v3jxIIqMtxhv+BKGTQpltXHzNgZIQwe4v1WTh1 R5OjXefd9xNAGgiGO6KECti+Cu6rViiMA2IrO+ksRfegAZ5LNlNxizfLYKW7nAENHIwyHKZgfFn jLWN4MplRftO6QYRJvFKrdyRy590lcxeP1AIY X-Received: by 2002:a05:600c:491:: with SMTP id d17mr10092572wme.130.1644155895562; Sun, 06 Feb 2022 05:58:15 -0800 (PST) X-Google-Smtp-Source: ABdhPJw1IZBDNXRWJ0qWdLWUtZri4Y1fEcK37M2Hc8URD6XUC5A9Ckq9s/y+aIikyLKZ0ScCl082xw== X-Received: by 2002:a05:600c:491:: with SMTP id d17mr10092552wme.130.1644155895343; Sun, 06 Feb 2022 05:58:15 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id e9sm8296888wrg.60.2022.02.06.05.58.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 05:58:14 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Lukasz Luba , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 3/8] dt-bindings: memory: lpddr3: convert to dtschema Date: Sun, 6 Feb 2022 14:58:02 +0100 Message-Id: <20220206135807.211767-4-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> References: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Convert the LPDDR3 memory bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Osipenko --- .../memory-controllers/ddr/jedec,lpddr3.yaml | 265 ++++++++++++++++++ .../memory-controllers/ddr/lpddr3.txt | 107 ------- .../samsung,exynos5422-dmc.yaml | 3 +- 3 files changed, 266 insertions(+), 109 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml new file mode 100644 index 000000000000..e36f3607e25a --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -0,0 +1,265 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR3 SDRAM compliant to JEDEC JESD209-3 + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + items: + - enum: + - samsung,K3QF2F20DB + - const: jedec,lpddr3 + + '#address-cells': + const: 1 + + density: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Density in megabits of SDRAM chip. + enum: + - 4096 + - 8192 + - 16384 + - 32768 + + io-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + IO bus width in bits of SDRAM chip. + enum: + - 64 + - 32 + - 16 + - 8 + + manufacturer-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Manufacturer ID value read from Mode Register 5. + + revision-id: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + items: + maximum: 255 + description: | + Revision value of SDRAM chip read from Mode Registers 6 and 7. + + '#size-cells': + const: 0 + + tCKE-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + CKE minimum pulse width (HIGH and LOW pulse width) in terms of number + of clock cycles. + + tCKESR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in terms of number of clock cycles. + + tDQSCK-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + DQS output data access time from CK_t/CK_c in terms of number of clock + cycles. + + tFAW-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 63 + description: | + Four-bank activate window in terms of number of clock cycles. + + tMRD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Mode register set command delay in terms of number of clock cycles. + + tR2R-C2C-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + Additional READ-to-READ delay in chip-to-chip cases in terms of number + of clock cycles. + + tRAS-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 63 + description: | + Row active time in terms of number of clock cycles. + + tRC-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 63 + description: | + ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles. + + tRCD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + RAS-to-CAS delay in terms of number of clock cycles. + + tRFC-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 255 + description: | + Refresh Cycle time in terms of number of clock cycles. + + tRL-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + READ data latency in terms of number of clock cycles. + + tRPab-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Row precharge time (all banks) in terms of number of clock cycles. + + tRPpb-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Row precharge time (single banks) in terms of number of clock cycles. + + tRRD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Active bank A to active bank B in terms of number of clock cycles. + + tRTP-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Internal READ to PRECHARGE command delay in terms of number of clock + cycles. + + tW2W-C2C-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number + of clock cycles. + + tWL-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + WRITE data latency in terms of number of clock cycles. + + tWR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + WRITE recovery time in terms of number of clock cycles. + + tWTR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Internal WRITE-to-READ command delay in terms of number of clock cycles. + + tXP-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 255 + description: | + Exit power-down to next valid command delay in terms of number of clock + cycles. + + tXSR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 1023 + description: | + SELF REFRESH exit to next valid command delay in terms of number of clock + cycles. + +patternProperties: + "^timings@[0-9a-f]+$": + $ref: jedec,lpddr3-timings.yaml + description: | + The lpddr3 node may have one or more child nodes with timings. + Each timing node provides AC timing parameters of the device for a given + speed-bin. The user may provide the timings for as many speed-bins as is + required. + +required: + - compatible + - '#address-cells' + - density + - io-width + - '#size-cells' + +additionalProperties: false + +examples: + - | + lpddr3 { + compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tDQSCK-min-tck = <5>; + tFAW-min-tck = <5>; + tMRD-min-tck = <5>; + tR2R-C2C-min-tck = <0>; + tRAS-min-tck = <5>; + tRC-min-tck = <6>; + tRCD-min-tck = <3>; + tRFC-min-tck = <17>; + tRL-min-tck = <14>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRRD-min-tck = <2>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tWR-min-tck = <7>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tXSR-min-tck = <12>; + + timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; + min-freq = <100000000>; + tCKE = <3750>; + tCKESR = <3750>; + tFAW = <25000>; + tMRD = <7000>; + tR2R-C2C = <0>; + tRAS = <23000>; + tRC = <33750>; + tRCD = <10000>; + tRFC = <65000>; + tRPab = <12000>; + tRPpb = <12000>; + tRRD = <6000>; + tRTP = <3750>; + tW2W-C2C = <0>; + tWR = <7500>; + tWTR = <3750>; + tXP = <3750>; + tXSR = <70000>; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt deleted file mode 100644 index 031af5fb0379..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt +++ /dev/null @@ -1,107 +0,0 @@ -* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C - -Required properties: -- compatible : Should be ",", and generic value "jedec,lpddr3". - Example "," values: - "samsung,K3QF2F20DB" - -- density : representing density in Mb (Mega bits) -- io-width : representing bus width. Possible values are 8, 16, 32, 64 -- #address-cells: Must be set to 1 -- #size-cells: Must be set to 0 - -Optional properties: - -- manufacturer-id : Manufacturer ID value read from Mode Register 5 -- revision-id : Revision IDs read from Mode Registers 6 and 7 - -The following optional properties represent the minimum value of some AC -timing parameters of the DDR device in terms of number of clock cycles. -These values shall be obtained from the device data-sheet. -- tRFC-min-tck -- tRRD-min-tck -- tRPab-min-tck -- tRPpb-min-tck -- tRCD-min-tck -- tRC-min-tck -- tRAS-min-tck -- tWTR-min-tck -- tWR-min-tck -- tRTP-min-tck -- tW2W-C2C-min-tck -- tR2R-C2C-min-tck -- tWL-min-tck -- tDQSCK-min-tck -- tRL-min-tck -- tFAW-min-tck -- tXSR-min-tck -- tXP-min-tck -- tCKE-min-tck -- tCKESR-min-tck -- tMRD-min-tck - -Child nodes: -- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". - "lpddr3-timings" provides AC timing parameters of the device for - a given speed-bin. Please see - Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt - for more information on "lpddr3-timings" - -Example: - -samsung_K3QF2F20DB: lpddr3 { - compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; - density = <16384>; - io-width = <32>; - manufacturer-id = <1>; - revision-id = <123 234>; - #address-cells = <1>; - #size-cells = <0>; - - tRFC-min-tck = <17>; - tRRD-min-tck = <2>; - tRPab-min-tck = <2>; - tRPpb-min-tck = <2>; - tRCD-min-tck = <3>; - tRC-min-tck = <6>; - tRAS-min-tck = <5>; - tWTR-min-tck = <2>; - tWR-min-tck = <7>; - tRTP-min-tck = <2>; - tW2W-C2C-min-tck = <0>; - tR2R-C2C-min-tck = <0>; - tWL-min-tck = <8>; - tDQSCK-min-tck = <5>; - tRL-min-tck = <14>; - tFAW-min-tck = <5>; - tXSR-min-tck = <12>; - tXP-min-tck = <2>; - tCKE-min-tck = <2>; - tCKESR-min-tck = <2>; - tMRD-min-tck = <5>; - - timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { - compatible = "jedec,lpddr3-timings"; - /* workaround: 'reg' shows max-freq */ - reg = <800000000>; - min-freq = <100000000>; - tRFC = <65000>; - tRRD = <6000>; - tRPab = <12000>; - tRPpb = <12000>; - tRCD = <10000>; - tRC = <33750>; - tRAS = <23000>; - tWTR = <3750>; - tWR = <7500>; - tRTP = <3750>; - tW2W-C2C = <0>; - tR2R-C2C = <0>; - tFAW = <25000>; - tXSR = <70000>; - tXP = <3750>; - tCKE = <3750>; - tCKESR = <3750>; - tMRD = <7000>; - }; -} diff --git a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml index 895c3b5c9aaa..f152243f6b18 100644 --- a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml @@ -53,8 +53,7 @@ properties: $ref: '/schemas/types.yaml#/definitions/phandle' description: | phandle of the connected DRAM memory device. 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[188.155.168.84]) by smtp.gmail.com with ESMTPSA id e9sm8296888wrg.60.2022.02.06.05.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 05:58:15 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Lukasz Luba , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 4/8] dt-bindings: memory: lpddr3: adjust IO width to spec Date: Sun, 6 Feb 2022 14:58:03 +0100 Message-Id: <20220206135807.211767-5-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> References: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org According to JEDEC Standard No. 209-3 (table 3.4.1 "Mode Register Assignment and Definition in LPDDR3 SDRAM"), the LPDDR3 supports only 16- and 32-bit IO width. Drop the unsupported others. Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/ddr/jedec,lpddr3.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml index e36f3607e25a..d6787b5190ee 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -34,10 +34,8 @@ properties: description: | IO bus width in bits of SDRAM chip. enum: - - 64 - 32 - 16 - - 8 manufacturer-id: $ref: /schemas/types.yaml#/definitions/uint32 From patchwork Sun Feb 6 13:58:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 540522 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AC67C4332F for ; Sun, 6 Feb 2022 14:05:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237347AbiBFOFM (ORCPT ); Sun, 6 Feb 2022 09:05:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236705AbiBFOFL (ORCPT ); Sun, 6 Feb 2022 09:05:11 -0500 Received: from smtp-relay-internal-1.canonical.com (smtp-relay-internal-1.canonical.com [185.125.188.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C138FC043185 for ; Sun, 6 Feb 2022 06:05:10 -0800 (PST) Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id 89C9240314 for ; Sun, 6 Feb 2022 13:58:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1644155899; bh=lowbJ9HbAqgBRMehsHM/qhZ+cS05q8+wNRQlqfDefTM=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QzuUqcXvAqovUwxK3ArDV/ylG8vKI2OUpZo6Mx4IjolMhoLB7VKSAxJjBuAxdvVDq f1qFXncLcRwIEpKXNB/wVC05BGVSRs2eWHIcWx+lQY+Cw6ymtE4izdZkODbfp8yEJc pXJ3iOAJg2G8Ya67ns9bcdzFqBCsVd8zCkQ6s8c4fqTDgalAH7U+SneeyDO2oDFr7k RWKh0Rl3PEV329QFmZxg6tO+ptBr/k41K++a0vdN6oa3cuZYO9xD6JUHjbneXhgc09 wKLgN1ZH1kP9XQPucoFLhrARdMmcgjaNQsABrrgCIiCF3y4a6MjWrftd+54r/3ia3f 1jEmSHkdHkmCg== Received: by mail-wm1-f71.google.com with SMTP id h82-20020a1c2155000000b003552c13626cso6186288wmh.3 for ; Sun, 06 Feb 2022 05:58:19 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lowbJ9HbAqgBRMehsHM/qhZ+cS05q8+wNRQlqfDefTM=; b=2OdCD82Ij6S/NM0s2pX9WweUs8Nm3YH13GW8tijSfrQzHaQiHmgoVjrhvJlBDoT1wk NDPpmA4eh+zx0U3J43Gl93yi/Qgwri4ZCe721B/7mZmlabKBYcgqeONHXVyByq8DoQVF +JTt3oLnu18Hlcr/yy3v+WBdDFGDyuVQUSI5UZkERtZQdyRKAT2lFuQYhmpBXv4cikiq ks4XuO+v/FE0J5R/jeH7zGqVMuMpc1EukC6gg/eGZqMXBca+ZkFTak3L1Azi1qH+4teB +9wCwpJBeh7In5SQ6zq8jiYgBeCWz26zvxu/dtWpO2KKrQ7otGbJ9cQTik1XjknscAIZ cG8Q== X-Gm-Message-State: AOAM533Xoaaamx03EYSmb4XoN167I7VSgE30xoaubZVVee6rTcQHvXbk D/uszBf0uUy8SshZCKInXWHrZwskD61rMTR9QneSNF1EOtLbGdNbypv7oGC8seb3XCbyDBTR0Z0 DbW5OI6fsAvFraGcI9F8V7HkAezJoN57BFn7F X-Received: by 2002:a05:600c:218:: with SMTP id 24mr7316482wmi.95.1644155897618; Sun, 06 Feb 2022 05:58:17 -0800 (PST) X-Google-Smtp-Source: ABdhPJzFbHkfXy9mwKBU3YQJK1xswUXUcJeL2qs8UreyNLnbIswkcL4WL2NExoBBoPLmzdhlDF7SCw== X-Received: by 2002:a05:600c:218:: with SMTP id 24mr7316471wmi.95.1644155897470; Sun, 06 Feb 2022 05:58:17 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id e9sm8296888wrg.60.2022.02.06.05.58.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 05:58:16 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Lukasz Luba , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 5/8] dt-bindings: memory: lpddr3: deprecate manufacturer ID Date: Sun, 6 Feb 2022 14:58:04 +0100 Message-Id: <20220206135807.211767-6-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> References: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The memory manufacturer should be described in vendor part of compatible, so there is no need to duplicate it in a separate property. Similarly is done in LPDDR2 bindings. Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/ddr/jedec,lpddr3.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml index d6787b5190ee..3bcba15098ea 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -40,7 +40,9 @@ properties: manufacturer-id: $ref: /schemas/types.yaml#/definitions/uint32 description: | - Manufacturer ID value read from Mode Register 5. + Manufacturer ID value read from Mode Register 5. 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[188.155.168.84]) by smtp.gmail.com with ESMTPSA id e9sm8296888wrg.60.2022.02.06.05.58.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 05:58:18 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Lukasz Luba , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 6/8] dt-bindings: memory: lpddr3: deprecate passing timings frequency as unit address Date: Sun, 6 Feb 2022 14:58:05 +0100 Message-Id: <20220206135807.211767-7-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> References: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The timings node maximum frequency was passed as an unit address, which is actually a workaround. Such workaround and unit address are not needed at all, because the device memory node (parent) can contain multiple timing nodes without unit addresses but with suffix used for nodenames, e.g. timings-1. LPDDR2 bindings already use such version, so unify the LPDDR3 with them. Suggested-by: Dmitry Osipenko Signed-off-by: Krzysztof Kozlowski --- .../ddr/jedec,lpddr3-timings.yaml | 16 ++++++++++------ .../memory-controllers/ddr/jedec,lpddr3.yaml | 12 +++++------- 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml index 98bc219e8a25..97c3e988af5f 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml @@ -17,6 +17,13 @@ properties: maxItems: 1 description: | Maximum DDR clock frequency for the speed-bin, in Hz. + Property is deprecated, use max-freq. + deprecated: true + + max-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Maximum DDR clock frequency for the speed-bin, in Hz. min-freq: $ref: /schemas/types.yaml#/definitions/uint32 @@ -117,19 +124,16 @@ properties: required: - compatible - min-freq - - reg + - max-freq additionalProperties: false examples: - | lpddr3 { - #address-cells = <1>; - #size-cells = <0>; - - timings@800000000 { + timings { compatible = "jedec,lpddr3-timings"; - reg = <800000000>; + max-freq = <800000000>; min-freq = <100000000>; tCKE = <3750>; tCKESR = <3750>; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml index 3bcba15098ea..c542f32c39fa 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -18,6 +18,7 @@ properties: '#address-cells': const: 1 + deprecated: true density: $ref: /schemas/types.yaml#/definitions/uint32 @@ -55,6 +56,7 @@ properties: '#size-cells': const: 0 + deprecated: true tCKE-min-tck: $ref: /schemas/types.yaml#/definitions/uint32 @@ -191,7 +193,7 @@ properties: cycles. patternProperties: - "^timings@[0-9a-f]+$": + "^timings((-[0-9])+|(@[0-9a-f]+))?$": $ref: jedec,lpddr3-timings.yaml description: | The lpddr3 node may have one or more child nodes with timings. @@ -201,10 +203,8 @@ patternProperties: required: - compatible - - '#address-cells' - density - io-width - - '#size-cells' additionalProperties: false @@ -214,8 +214,6 @@ examples: compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; density = <16384>; io-width = <32>; - #address-cells = <1>; - #size-cells = <0>; tCKE-min-tck = <2>; tCKESR-min-tck = <2>; @@ -239,9 +237,9 @@ examples: tXP-min-tck = <2>; tXSR-min-tck = <12>; - timings@800000000 { + timings { compatible = "jedec,lpddr3-timings"; - reg = <800000000>; + max-freq = <800000000>; min-freq = <100000000>; tCKE = <3750>; tCKESR = <3750>; From patchwork Sun Feb 6 13:58:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 541004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9B02C433EF for ; Sun, 6 Feb 2022 14:05:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239973AbiBFOFM (ORCPT ); Sun, 6 Feb 2022 09:05:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234145AbiBFOFL (ORCPT ); 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[188.155.168.84]) by smtp.gmail.com with ESMTPSA id e9sm8296888wrg.60.2022.02.06.05.58.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 05:58:19 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Lukasz Luba , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 7/8] memory: of: parse max-freq property Date: Sun, 6 Feb 2022 14:58:06 +0100 Message-Id: <20220206135807.211767-8-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> References: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Passing the memory timings maximum frequency as an unit address was a workaround and instead 'max-freq' is preferred. Look for 'max-freq' first and then fallback to 'reg'. Signed-off-by: Krzysztof Kozlowski --- drivers/memory/of_memory.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c index b94408954d85..bac5c7f34936 100644 --- a/drivers/memory/of_memory.c +++ b/drivers/memory/of_memory.c @@ -212,8 +212,10 @@ static int of_lpddr3_do_get_timings(struct device_node *np, { int ret; - /* The 'reg' param required since DT has changed, used as 'max-freq' */ - ret = of_property_read_u32(np, "reg", &tim->max_freq); + ret = of_property_read_u32(np, "max-freq", &tim->max_freq); + if (ret) + /* Deprecated way of passing max-freq as 'reg' */ + ret = of_property_read_u32(np, "reg", &tim->max_freq); ret |= of_property_read_u32(np, "min-freq", &tim->min_freq); ret |= of_property_read_u32(np, "tRFC", &tim->tRFC); ret |= of_property_read_u32(np, "tRRD", &tim->tRRD); From patchwork Sun Feb 6 13:59:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 540525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31814C433F5 for ; Sun, 6 Feb 2022 13:59:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241401AbiBFN7o (ORCPT ); Sun, 6 Feb 2022 08:59:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242513AbiBFN7g (ORCPT ); Sun, 6 Feb 2022 08:59:36 -0500 X-Greylist: delayed 64 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Sun, 06 Feb 2022 05:59:24 PST Received: from smtp-relay-internal-1.canonical.com (smtp-relay-internal-1.canonical.com [185.125.188.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B2D1C0401E3 for ; Sun, 6 Feb 2022 05:59:23 -0800 (PST) Received: from mail-wm1-f70.google.com (mail-wm1-f70.google.com [209.85.128.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id C2D9340038 for ; Sun, 6 Feb 2022 13:59:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1644155962; bh=SJklMGC7T/EUcj3Xgr8zoxCnRlerqEqIREG1cOIIgnU=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YW11ea5uXVN444CaJ2jZT7W4kgqT1ZRyL2/QzBK50Z2ItGNbp+ceYLP6v8vYtNBK6 U2JdUAWg1IE3U0PzRMjfB6AMOibK7+VGFN28FFIBwGG4XvqwgkrWDxZgkHIIXSf/X+ A5QHfOxl6UR1iRdWZqi/iKhGRmqC5s9IlN+8Z34aXqq0D7gOoMb3PrOSANnNJt5+NP 4AbAshSsf5doUktYI6SbPEdqb77D3X9xEdFCzZJJQZnbdf0BmWtrjzTIRjKWyliGsd 5tW9Y4mVSJytwFXjWjtjWHQ+Q9ECgjeH5W3sDx1vMmk4Uvz556riByr72IBzooj84w gj5tCzNuTKidA== Received: by mail-wm1-f70.google.com with SMTP id r16-20020a05600c2c5000b0037bb20c50b8so1438966wmg.3 for ; Sun, 06 Feb 2022 05:59:22 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SJklMGC7T/EUcj3Xgr8zoxCnRlerqEqIREG1cOIIgnU=; b=7aliQz18Ex2WdlMGYjQnTSTg6YOYmGfBAV3SRVFCYa6vzHaFhMJ+eEbPhqlFmvDAZN AmdtvxYQWo/gTbj84s4UaP4X3dm4hxyWBLPRrvu03emHjB+YsTw6jGqoKuVKLRDEvN7p AxjgA4aDZTI5lIEqT4gZSsCAtNac/B2kVk1WmWP5KjdqTjd0NAtfgjkjrtKJz1vK/PhE OzLKMIzkwMZHmT3743ANZIrmlN9XoaoPuDrrGCuhijj/TG6IUOXOfZI50Dt+rCN8Yaj5 kP8aOGmZuiWGu/IEvjZBMQg3UnHTipEvMUQprsMGF7kSzPHOpF7wzzjXDxlACd9N+nzd lkUA== X-Gm-Message-State: AOAM530GQn+I1sz+Ys1XBjyxUpqaG9b4DU9k5NL6wAqfsESn0aFeq4oT QlV7Z5DAG6R5Ke+WUuUmjbHy4RWYsU5wBaRHRgO+7jw8cSd6RXVYK82OWUR/NL8Vk+ytaIhdI2w qkVFFYINsbseBSbnGBrsIQu1cXku8NrnVcVfn X-Received: by 2002:a05:600c:502b:: with SMTP id n43mr10478970wmr.67.1644155962525; Sun, 06 Feb 2022 05:59:22 -0800 (PST) X-Google-Smtp-Source: ABdhPJzUW+CjZnoeRLOh3DLXJaGbc+rfq4URa9GWOKXq/P5jT8JUcEp9PlU4lZBC6zLP0TImsGzKjQ== X-Received: by 2002:a05:600c:502b:: with SMTP id n43mr10478958wmr.67.1644155962408; Sun, 06 Feb 2022 05:59:22 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id m14sm9018167wrp.4.2022.02.06.05.59.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 05:59:21 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Lukasz Luba , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 8/8] ARM: dts: exynos: remove deprecated unit address for LPDDR3 timings on Odroid Date: Sun, 6 Feb 2022 14:59:18 +0100 Message-Id: <20220206135918.211990-1-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> References: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Passing maximum frequency of LPDDR3 memory timings as unit address was deprecated in favor of 'max-freq' property. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 2f65dcf6ba73..35818c4cd852 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -333,8 +333,6 @@ samsung_K3QF2F20DB: lpddr3 { compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; density = <16384>; io-width = <32>; - #address-cells = <1>; - #size-cells = <0>; tRFC-min-tck = <17>; tRRD-min-tck = <2>; @@ -358,10 +356,9 @@ samsung_K3QF2F20DB: lpddr3 { tCKESR-min-tck = <2>; tMRD-min-tck = <5>; - timings_samsung_K3QF2F20DB_800mhz: timings@800000000 { + timings_samsung_K3QF2F20DB_800mhz: timings { compatible = "jedec,lpddr3-timings"; - /* workaround: 'reg' shows max-freq */ - reg = <800000000>; + max-freq = <800000000>; min-freq = <100000000>; tRFC = <65000>; tRRD = <6000>;