From patchwork Sun Feb 6 10:31:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 540401 Delivered-To: patch@linaro.org Received: by 2002:ac0:f7d2:0:0:0:0:0 with SMTP id i18csp4630869imr; Sun, 6 Feb 2022 02:37:04 -0800 (PST) X-Google-Smtp-Source: ABdhPJwOwJIPs1Y9hI+49voiDWYBgmHZ7Go7kHNcSFQwkw8chu6Eit6TfHNFzE7sgju/0fQwGNv1 X-Received: by 2002:a05:6214:f2b:: with SMTP id iw11mr7346972qvb.125.1644143824775; Sun, 06 Feb 2022 02:37:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644143824; cv=none; d=google.com; s=arc-20160816; b=m6GIVVw4mEwFb6HkijO6EPnIdr+5CWhhWh9QiApbEGMQGQqHpp5F7kt3BHvkgPljCr LCo2wYHQc327EWS1FwBHly5rQqUdCz349lvUbk6LQFeonq98YossaDX15BLMZgcvjmFK aWYBvLWlrFmUiH+4XhjlX4ZrdReXRn9AVFl5fB+FQY2mRh6iaTJAVfZ9QfVoEfpSt/8b ATuzNzidFl3ncLJj5nDnWWswsUSNPstfNLztbgWA1joUzapj6XMafzPZrH9+zrzMiRoq WxtxyTx4/Ovu0ZVR51KbmggWwlzUyPSMzgoUdOA+elHlEREt34QoRaHqc4mogwWDGjkl +0yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aVBv6wXuSbvaamtrblJpDcCL0BFzSBoSOUStalUh64I=; b=jc8I50XEpei5iyfCV/c3SlbIodJ0B5NXxcNDvH8pvu3T5bErwDVFlgdH6m3Bu6QVYO 3Q/adC0MuXkvIDOLDSmS5ualYF2+cd3UnRNaPkqWPKmY0hLE0mjE58Xm9OX4nw8Vwoea A6m/J6Z7s6jN2JAueqMZBY9fMaHl0pZFw93MDU+OhlCfx6P6jnUTKPZm/RAN1yFSX2r5 PMWcyPuFVlDGg34GVeLrV3f0DWHurs03aYYBvtWDPerlv6VTbj0ko2fu0GfQtOpMDdbt mrqBVeXVluqO0Z4OnnLgp+g0Ih1phkqLkphbuSLfp6FyxIGt12qzXP/sfFi4mpxI/xo0 hlIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iDqTqcAc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id gg8si1850683qvb.578.2022.02.06.02.37.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 06 Feb 2022 02:37:04 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iDqTqcAc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60292 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nGeum-0007na-CR for patch@linaro.org; Sun, 06 Feb 2022 05:37:04 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nGepi-0004TU-Cv for qemu-devel@nongnu.org; Sun, 06 Feb 2022 05:31:50 -0500 Received: from [2607:f8b0:4864:20::52a] (port=33470 helo=mail-pg1-x52a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nGepg-0002Nr-8g for qemu-devel@nongnu.org; Sun, 06 Feb 2022 05:31:49 -0500 Received: by mail-pg1-x52a.google.com with SMTP id 77so6223829pgc.0 for ; Sun, 06 Feb 2022 02:31:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aVBv6wXuSbvaamtrblJpDcCL0BFzSBoSOUStalUh64I=; b=iDqTqcAcJUrN6B7JmxYsW/Or4AhFTMD0r05xC4UO8D8pljCPLTaDbUCv+F0zG1TUIi 3GAy4mo7g2vEO19J1rlHikP6z7KhEuqhoXCANjHk8sdlS5kqPkzxZ9sNsSDbiue2t7Hj qwrv6Wfauz1o6K5PapaVFdHJF6BZCvtPQRbs7DcOPHEN0qEXJ0IdyvgqpVWLQ0wMxaoO 4IXu4aTRlODnn3d3J+pFz3CJ6VQY9Hy/l4V2RsyHvYkHSC/GmaAD7vxpd0Z/bsXpvFXO bA4MZGSGEChLK320h8pb3pyLVNrcs/RPVZagnq3xOxy9CwdHFnhYHGhzFx29sSOkBQ04 L40Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aVBv6wXuSbvaamtrblJpDcCL0BFzSBoSOUStalUh64I=; b=pCJffqVSM59x8C1BpIjcE7o+xQrMKe0+XVJhggcay7AUYY7yqzC0RL8y+jr73v3OQA S/ONnkY19fHWN52Ms1XJ3UfTR7Hj4Z0DFnQK8UJLQ5oStA9Gdqz6LgE4p3a0jArHx1EB OeoCjGz9BwhxneK3DQpzt9+B6UqpNEIfGr3HfHtv1LmNKbx+yRkwiuPD9eboCZzX8B6i DZipfULiTDgxIMMPhFYTG6JbbS+MMNMywD1gbx1e/VhW93Fx51jNTMs5asA9q3aG36ez x/RVMU5jwsS4FA8RkZ/tYa6qIkIxq1OPjWRRRytW5sLnUVr/DI+UaAf5EoptdyJT5Blz pEaw== X-Gm-Message-State: AOAM530O0g7buzD4PAGrrc1XMkYtpUeI2vPbC/BYXostXMdGNppITNi6 EXEqO8u8gMmRUS0NjAaYNfo2vFmwJzE405Ah X-Received: by 2002:a63:8049:: with SMTP id j70mr931477pgd.295.1644143506756; Sun, 06 Feb 2022 02:31:46 -0800 (PST) Received: from localhost.localdomain ([220.235.247.127]) by smtp.gmail.com with ESMTPSA id s2sm5605937pgl.21.2022.02.06.02.31.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 02:31:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 1/6] tcg/sparc: Add scratch argument to tcg_out_movi_int Date: Sun, 6 Feb 2022 21:31:33 +1100 Message-Id: <20220206103138.36105-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220206103138.36105-1-richard.henderson@linaro.org> References: <20220206103138.36105-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will allow us to control exactly what scratch register is used for loading the constant. Also, fix a theoretical problem in recursing through tcg_out_movi, which may provide a different value for in_prologue. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 0c062c60eb..8c3671f56a 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -414,7 +414,8 @@ static void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg) } static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long arg, bool in_prologue) + tcg_target_long arg, bool in_prologue, + TCGReg scratch) { tcg_target_long hi, lo = (int32_t)arg; tcg_target_long test, lsb; @@ -471,22 +472,25 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, /* A 64-bit constant decomposed into 2 32-bit pieces. */ if (check_fit_i32(lo, 13)) { hi = (arg - lo) >> 32; - tcg_out_movi(s, TCG_TYPE_I32, ret, hi); + tcg_out_movi_int(s, TCG_TYPE_I32, ret, hi, in_prologue, scratch); tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); } else { + tcg_debug_assert(scratch != TCG_REG_G0); hi = arg >> 32; - tcg_out_movi(s, TCG_TYPE_I32, ret, hi); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T2, lo); + tcg_out_movi_int(s, TCG_TYPE_I32, ret, hi, in_prologue, scratch); + tcg_out_movi_int(s, TCG_TYPE_I32, scratch, lo, in_prologue, TCG_REG_G0); tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); - tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR); + tcg_out_arith(s, ret, ret, scratch, ARITH_OR); } } static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { - tcg_out_movi_int(s, type, ret, arg, false); + /* When outputting to T2, we have no scratch available. */ + TCGReg scratch = ret != TCG_REG_T2 ? TCG_REG_T2 : TCG_REG_G0; + tcg_out_movi_int(s, type, ret, arg, false, scratch); } static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, @@ -837,7 +841,7 @@ static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, } else { uintptr_t desti = (uintptr_t)dest; tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, - desti & ~0xfff, in_prologue); + desti & ~0xfff, in_prologue, TCG_REG_O7); tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL); } } @@ -1013,7 +1017,8 @@ static void tcg_target_qemu_prologue(TCGContext *s) #ifndef CONFIG_SOFTMMU if (guest_base != 0) { - tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, + true, TCG_REG_T1); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif From patchwork Sun Feb 6 10:31:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 540405 Delivered-To: patch@linaro.org Received: by 2002:ac0:f7d2:0:0:0:0:0 with SMTP id i18csp4634185imr; Sun, 6 Feb 2022 02:44:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJwSvG6OOCGbOWIjUECzy3w6LtyeE2Cb6rAxoN0yYk+ujfrVZO/453TbIqsfufaKoF33D7VP X-Received: by 2002:a05:622a:1b8b:: with SMTP id bp11mr4714631qtb.662.1644144271305; Sun, 06 Feb 2022 02:44:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644144271; cv=none; d=google.com; s=arc-20160816; b=BK4iNo0elmIGpa12MOjHvb7H7NRzkcGYupjaO33nLUz4efEco7GsG3/BQhjjK73jrY k0yytMbcH6hiDjajCLYzTlH4TYWsOUCJC1d+QeGbC0s2XzEBPWr4U7BMX45qqbFVnd3y /kUfkDqXxEAiEafr1dcEfCkYYkoyeE2RLyMl+vhQc1IFjyeRjmtk8475f7X89X1xp+Xs Vdu6CQ7WLHLyQ6Uh+goVHNUqXLwjBWT8Kf5skR6ah9HoFrpewez+3+GMz8IYvkHltWJA ikMqjj3I5q6Uec6DWg6FAKznH1KHowZTbWmE5uMjmRL0Egy8OFgg7qgnJ+zX0T/TA9kd VnYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bn51JgtZkfipNb1j4v1ZZK9UKAPKwd08pZI1+ol2wL8=; b=Ys8trQMlU6QY6+0rXeiSl+A0vuNUfjrKW/dJ9rHnwPwabwIuARYFTSBUnkWpUUL1tV h21fyVU9KYZ6ptrkrWo7BU1vEIjq3w/JtsQo+X8KxMUGGSIAn/1aO8VW0LDxvSUYOqnL 6FFhqmH2rJ/sEp0fXlOGaJw94Pwww6pqy0QFCGXVAqAKAf5N9KVFtjoKb8IPf8GZuLap FJ7SX8nna6u6KaEC+Lyk4+/LMrWAjk5/sqSURdujPhbXaieRFiJh8hhnh7pzCTLa+uE5 WskAEHM3PKXIOrlwjuxNndEort1cKp5lNwNPu2C6Cq0ZGap8DJcJopd9BKP3c4lEnSIH wB/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cEEXS683; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t125si1560002qkf.413.2022.02.06.02.44.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 06 Feb 2022 02:44:31 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cEEXS683; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47914 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nGf1y-0001P8-U6 for patch@linaro.org; Sun, 06 Feb 2022 05:44:30 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51796) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nGepk-0004V2-8G for qemu-devel@nongnu.org; Sun, 06 Feb 2022 05:31:52 -0500 Received: from [2607:f8b0:4864:20::435] (port=37795 helo=mail-pf1-x435.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nGepi-0002OD-Dv for qemu-devel@nongnu.org; Sun, 06 Feb 2022 05:31:51 -0500 Received: by mail-pf1-x435.google.com with SMTP id y5so8218075pfe.4 for ; Sun, 06 Feb 2022 02:31:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bn51JgtZkfipNb1j4v1ZZK9UKAPKwd08pZI1+ol2wL8=; b=cEEXS683kQUIKX+Q7O8VTvtlYUzLC0DXv0kOygqWTh5w9qU6FinSxoS3tkpJlWA0iq UjTBfTtITlcAzYQy9CEJ9/V53XJyYWTST3HPDK7OZaX4dYyYAOTuNhGrjt9Kb7jjcGSI +nf4jXQ/BTr1450zcHfq/Zr6nQTAXgBoBKYaeXE2ZysCjGGKowbhrMV8Oy8KuYrHdXP8 x8VVz+L+PTRfKV7OfVLTi5flrle/BEI2fYIgAE8E8sWMxUQc863SbL/qKDEJPI3VQF9V Yr85LauFII56mNNP390yf1QtxxjKC8+RfurSd+QvNBrNxXJ1gFt66gZE1j97fZcg1OJR SNzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bn51JgtZkfipNb1j4v1ZZK9UKAPKwd08pZI1+ol2wL8=; b=zYCFdlv58tq9eIrdqZSK8ZpNdgcS6JOj4nCmCrDVRv1xmydSskssbcb7fdMa0d0bRX KB6j49i3P4i4KEgN1s4oLr+Dl6CP8km/flUaC+GDDXSUFPv4cISrt6mXJlXN5rHev6NW WpBnoPxQyxhpBwpRx132HNcKu2vqAHCBU0kxMlnd9N3dh1RRdhL+EN0kjxZyaYF5QJZY skZz6oVNujDrOqTZxdgp2JxUBluZKeztam87OujUQ6FLMkKe32MweEJWNgbLCgThRYGg jiBi9D5RpadGY0wYxtCy7Cdnhcfzz+VhMZaHhM5j5Jc9Ve1rfSBM2P/8iOZI8ge1mgb9 IrUQ== X-Gm-Message-State: AOAM533Vlp99ZwgBu6gn68DCyzvrcPrV4HukPou6h/Wl8wzyxg7651P+ +1/nKnzaYcqe0WQdF4/MmawBElbP/BYwz+/p X-Received: by 2002:a63:8649:: with SMTP id x70mr5505000pgd.564.1644143509200; Sun, 06 Feb 2022 02:31:49 -0800 (PST) Received: from localhost.localdomain ([220.235.247.127]) by smtp.gmail.com with ESMTPSA id s2sm5605937pgl.21.2022.02.06.02.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 02:31:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 2/6] tcg/sparc: Improve code gen for shifted 32-bit constants Date: Sun, 6 Feb 2022 21:31:34 +1100 Message-Id: <20220206103138.36105-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220206103138.36105-1-richard.henderson@linaro.org> References: <20220206103138.36105-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::435 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We had code for checking for 13 and 21-bit shifted constants, but we can do better and allow 32-bit shifted constants. This is still 2 insns shorter than the full 64-bit sequence. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 8c3671f56a..f9afb1bffc 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -456,17 +456,17 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, return; } - /* A 21-bit constant, shifted. */ + /* A 32-bit constant, shifted. */ lsb = ctz64(arg); test = (tcg_target_long)arg >> lsb; - if (check_fit_tl(test, 13)) { - tcg_out_movi_imm13(s, ret, test); - tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); - return; - } else if (lsb > 10 && test == extract64(test, 0, 21)) { + if (lsb > 10 && test == extract64(test, 0, 21)) { tcg_out_sethi(s, ret, test << 10); tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); return; + } else if (test == (uint32_t)test || test == (int32_t)test) { + tcg_out_movi_int(s, TCG_TYPE_I64, ret, test, in_prologue, scratch); + tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); + return; } /* A 64-bit constant decomposed into 2 32-bit pieces. */ From patchwork Sun Feb 6 10:31:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 540406 Delivered-To: patch@linaro.org Received: by 2002:ac0:f7d2:0:0:0:0:0 with SMTP id i18csp4635442imr; Sun, 6 Feb 2022 02:47:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJzLts5ZBXwC+ArL9j0NgzW2tAgNlIlDOmIY9+WPJmdXgD2JOVd3btvJpseo92EVYYiLCZCx X-Received: by 2002:a05:620a:f13:: with SMTP id v19mr3885841qkl.84.1644144464166; Sun, 06 Feb 2022 02:47:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644144464; cv=none; d=google.com; s=arc-20160816; b=zBxyj64IYJhDTm9fIqlinAw6Yytdbpj4cQRBZUQCY1p5wFyifAWhBYWLQVqIgLEAZQ U3NySCOJ2opwO/WV+k1kQogN5VYB9J8d1lg58Z6cpQhnGLmUaOPk3CMQJAGFP4RrH8c2 Qb09NOinMki1kwPheXo4JFlW8u/2hp8665jp4D+dJcWCzC1iQp1cjhw+W49p/0jdG7wY 7YEZN7CE2vBImF71nZCOh7ibuH0xCR0rVDkO733Syl0ZkxJQXvkJQVJt6RqVU0yJZKHX +Juxa3FWjWdRdR6t5gVxylI+v2NSDfvLNuhkgNYbQz9hQDTjf/eiK1aDE8VlbWCOqWCA IRjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=veQnK6WaTjZ3A8j4hv7hC4c+w1i5jtwOSMWU/0mqUcQ=; b=BYQbDsVJBq4qQyTBlF4KiumH2c9nyeHEFHd3Azq+fXHFnkR/WNB+pRrZAi7I+6TqBY icR6j6s5SFlhfeZUxLV9jOyJ2zNv6lQdof/8gC52s8GWlyCY5pcsP76x/wC5jIMuBBDy ixaZ6XtAZHxsZJd0jxnR5gtzEsbU0fWeQit+xHd7yEymfLRdmA9aCMco+YfEmoVaLjia 0hgPf1da6c1h0HsKOiBDmVgrpBDz9Mis8UFGMDe+LY2SftOsJnMNgMl/8gMHBeyVBzlT GnFIIg2sO+9WRBaWjG6y4/QM0Lb8nZFpyBq/PpPEdTcVBOHgl8UgJaxrOqcuhx5Q09LO 0CtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s2H2kKG5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Sparc had its function signature changed, but not the logic. Replace assert with return false. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/sparc/tcg-target.c.inc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index f9afb1bffc..f3043e6833 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -323,12 +323,16 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type, switch (type) { case R_SPARC_WDISP16: - assert(check_fit_ptr(pcrel >> 2, 16)); + if (!check_fit_ptr(pcrel >> 2, 16)) { + return false; + } insn &= ~INSN_OFF16(-1); insn |= INSN_OFF16(pcrel); break; case R_SPARC_WDISP19: - assert(check_fit_ptr(pcrel >> 2, 19)); + if (!check_fit_ptr(pcrel >> 2, 19)) { + return false; + } insn &= ~INSN_OFF19(-1); insn |= INSN_OFF19(pcrel); break; From patchwork Sun Feb 6 10:31:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 540400 Delivered-To: patch@linaro.org Received: by 2002:ac0:f7d2:0:0:0:0:0 with SMTP id i18csp4629922imr; Sun, 6 Feb 2022 02:34:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJz+8MNef+x4kUxB/g4YUVZ72+Cfwrhvu0lXVeTSO+ygxYib11nykuy11kLtRmZFBxCq6TLI X-Received: by 2002:a05:6214:1cce:: with SMTP id g14mr7236254qvd.108.1644143685838; Sun, 06 Feb 2022 02:34:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644143685; cv=none; d=google.com; s=arc-20160816; b=PMTogWTdLXKPT6au4Me41WEBFZhsfAkVsGpblpHQcp9M2Lo+Cea2WA1HmONDWGvFdT +18Hb3FP1d1n/2Kn95Wm0uRluWsi7f8S0P1U/fj0cQQNpRl5u0EHpPOj0WZQrdncmVqP 1yUU+SMwBdHK221r8Tv76PxtSY09Z6No7PJItyld8dKzvM+Et/RDK/IEPxzlazBO/m9Z 5CCTg9O2Gl3nrn1WT+P6BkcupGza5zyQ9B+Lx9PDmf9UHsMfCNOPBsdM13Qwj35+8u/X fJcmtvJIsDhqrkgTfLCw3BnKo1jIL4xJdpADbcGGidant/kGg5rsOLQnPEz/wNbQCs8H y7aQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qJCEm5RzzhXFwEaNpyHXU7iJl0JP4KgfJFsTaZhBw3w=; b=AbMZAg/G7WgArZHhDwePbYGXxn+0X59IwgU9IDW7TUqVRFv5sSyvLxYpuET/IAS8bn aB0YiVRPSPcyQJ8tKIFJlia470fHYrWsC5LMKrgsHgd5pkTf7NrzYCJmBJief5HaMnn3 QoUBEJ33pMGy6vzJgGjhxhMUWK95aMdR+xIoX2TBbdcQCgCFKPSKfgZM5gH8YVpVanIs 2wPHnXpSGNkC4FQqTe+1e5UY4HiJCJuml6JcM01mUT/A5DkoLUOtb0ubdqxePATSZ39q 3HT/Gt8z7pOBkIOw3pRAnlLJ4lk7Q3EdC57yGOaRjnOq90L2cTVsNQtYKzp1UGIE4yWt L0bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UGfJznfb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Sun, 06 Feb 2022 02:31:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 4/6] tcg/sparc: Use the constant pool for 64-bit constants Date: Sun, 6 Feb 2022 21:31:36 +1100 Message-Id: <20220206103138.36105-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220206103138.36105-1-richard.henderson@linaro.org> References: <20220206103138.36105-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index f3043e6833..074fb25af2 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -336,6 +336,13 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type, insn &= ~INSN_OFF19(-1); insn |= INSN_OFF19(pcrel); break; + case R_SPARC_13: + if (!check_fit_ptr(value, 13)) { + return false; + } + insn &= ~INSN_IMM13(-1); + insn |= INSN_IMM13(value); + break; default: g_assert_not_reached(); } @@ -473,6 +480,14 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, return; } + /* Use the constant pool, if possible. */ + if (!in_prologue && USE_REG_TB) { + new_pool_label(s, arg, R_SPARC_13, s->code_ptr, + tcg_tbrel_diff(s, NULL)); + tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(TCG_REG_TB)); + return; + } + /* A 64-bit constant decomposed into 2 32-bit pieces. */ if (check_fit_i32(lo, 13)) { hi = (arg - lo) >> 32; From patchwork Sun Feb 6 10:31:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 540402 Delivered-To: patch@linaro.org Received: by 2002:ac0:f7d2:0:0:0:0:0 with SMTP id i18csp4632384imr; Sun, 6 Feb 2022 02:40:17 -0800 (PST) X-Google-Smtp-Source: ABdhPJzgukwU4NL75Z8yIqzIBGXXtIKuuk5kJF1gN2WesSQBp2fmaOEvk/st118nzEJxD9ubQ5gU X-Received: by 2002:a05:620a:1271:: with SMTP id b17mr3819276qkl.50.1644144017217; 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Which means that direct calls will now rarely be in range. So, always use indirect calls for tail calls, which allows us to avoid clobbering %o7, and therefore we need not save and restore it. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 074fb25af2..c81782d6ce 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -850,6 +850,19 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); } +static void tcg_out_jmpl_const(TCGContext *s, const tcg_insn_unit *dest, + bool in_prologue, bool tail_call) +{ + uintptr_t desti = (uintptr_t)dest; + + /* Be careful not to clobber %o7 for a tail call. */ + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, + desti & ~0xfff, in_prologue, + tail_call ? TCG_REG_G2 : TCG_REG_O7); + tcg_out_arithi(s, tail_call ? TCG_REG_G0 : TCG_REG_O7, + TCG_REG_T1, desti & 0xfff, JMPL); +} + static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, bool in_prologue) { @@ -858,10 +871,7 @@ static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, if (disp == (int32_t)disp) { tcg_out32(s, CALL | (uint32_t)disp >> 2); } else { - uintptr_t desti = (uintptr_t)dest; - tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, - desti & ~0xfff, in_prologue, TCG_REG_O7); - tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL); + tcg_out_jmpl_const(s, dest, in_prologue, false); } } @@ -952,11 +962,10 @@ static void build_trampolines(TCGContext *s) /* Set the retaddr operand. */ tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); - /* Set the env operand. */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); /* Tail call. */ - tcg_out_call_nodelay(s, qemu_ld_helpers[i], true); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); + tcg_out_jmpl_const(s, qemu_ld_helpers[i], true, true); + /* delay slot -- set the env argument */ + tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); } for (i = 0; i < ARRAY_SIZE(qemu_st_helpers); ++i) { @@ -998,14 +1007,14 @@ static void build_trampolines(TCGContext *s) if (ra >= TCG_REG_O6) { tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK, TCG_TARGET_CALL_STACK_OFFSET); - ra = TCG_REG_G1; + } else { + tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); } - tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); - /* Set the env operand. */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); + /* Tail call. */ - tcg_out_call_nodelay(s, qemu_st_helpers[i], true); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); + tcg_out_jmpl_const(s, qemu_st_helpers[i], true, true); + /* delay slot -- set the env argument */ + tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); } } #endif From patchwork Sun Feb 6 10:31:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 540404 Delivered-To: patch@linaro.org Received: by 2002:ac0:f7d2:0:0:0:0:0 with SMTP id i18csp4633927imr; Sun, 6 Feb 2022 02:43:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJzK7u9Ro/5RKLz6tiQ+WzsMPfnvfP1cb14XocA1n8rHeI/iUpYzyufJL6GW4mxMf5uAOp5z X-Received: by 2002:ac8:7fca:: with SMTP id b10mr4808776qtk.62.1644144223391; Sun, 06 Feb 2022 02:43:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1644144223; cv=none; d=google.com; s=arc-20160816; b=IruUuIZCkJvi8lV54FhaKiHlbXp2qERSRLLk1oNEJXHZEEQCgDaENcN+nupPUP5u7n i6mIGrtN0MD0jmLzW9iIVpbo7S37nwrQMmnmeztY15UZ8ny0rzsSK/mJqPt2dL8QT/Aj aEuiB2caJo6EOkH3LupQ076MJOtMoNxuNRli8qcReqNmD5AgqRG3WoslEz2ngGuB4W9U Onhsq3q786GKAAvLJbW3LnIAlEdkPFF+fQ3J+Py3r8cykucHmN9vBcH9Z82HU76K6u4i MXJoAECfxmgz5a1O2lIO+vgBVyNQp48NO60mGc2E1cjpEGkpzbGCC7jflLtza/qq0A4c rauw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iCU9gFCcyd2kPLFMOJRQp/mjQ+1whOIZ+XoBMnbCDWs=; b=bl3BXjyrxH5CEpDAdl5cVwrDnFgdYtWk8DzbwEk34eZjoBfSzP5HDFCNFTP53/4L1p MUNF/dI/amWhDBUwVljuUal2/UFCxUPWB4dCPGLoKbhf0PE2NzWr96PXI2EFYoLHzR1V pptGbVED0YZYY2bclyc9Q1TVsh1hhWq+5mozmkAx6ayIvATkwGAyTcMoRmwRBYUGT6GJ roVsCFKA+vLS3H9fNSTvH0McJJ1OaGZJiKXMClGWe36DLPZ4Bh5rLMo22uCYy/4hvo0W 9UdVfCBSHrT+mlxA7gcjpLqKcMmUUXo2Pluqvl9EZFqee39EqdMqwNcgJdBBrHpWHrLO wCAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BxfMCqy0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This inline code expansion is somewhat large, but it takes quite a few instructions to make a function call to a helper anyway. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/sparc/tcg-target.c.inc | 219 +++++++++++++++++++++++++++++++++++-- 1 file changed, 211 insertions(+), 8 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index c81782d6ce..e5d2115e94 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -211,6 +211,7 @@ static const int tcg_target_call_oarg_regs[] = { #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) +#define ARITH_ANDCC (INSN_OP(2) | INSN_OP3(0x11)) #define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) @@ -1017,6 +1018,38 @@ static void build_trampolines(TCGContext *s) tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); } } +#else +static const tcg_insn_unit *qemu_unalign_ld_trampoline; +static const tcg_insn_unit *qemu_unalign_st_trampoline; + +static void build_trampolines(TCGContext *s) +{ + for (int ld = 0; ld < 2; ++ld) { + void *helper; + + while ((uintptr_t)s->code_ptr & 15) { + tcg_out_nop(s); + } + + if (ld) { + helper = helper_unaligned_ld; + qemu_unalign_ld_trampoline = tcg_splitwx_to_rx(s->code_ptr); + } else { + helper = helper_unaligned_st; + qemu_unalign_st_trampoline = tcg_splitwx_to_rx(s->code_ptr); + } + + if (!SPARC64 && TARGET_LONG_BITS == 64) { + /* Install the high part of the address. */ + tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX); + } + + /* Tail call. */ + tcg_out_jmpl_const(s, helper, true, true); + /* delay slot -- set the env argument */ + tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); + } +} #endif /* Generate global QEMU prologue and epilogue code */ @@ -1067,9 +1100,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) /* delay slot */ tcg_out_movi_imm13(s, TCG_REG_O0, 0); -#ifdef CONFIG_SOFTMMU build_trampolines(s); -#endif } static void tcg_out_nop_fill(tcg_insn_unit *p, int count) @@ -1154,18 +1185,22 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, static const int qemu_ld_opc[(MO_SSIZE | MO_BSWAP) + 1] = { [MO_UB] = LDUB, [MO_SB] = LDSB, + [MO_UB | MO_LE] = LDUB, + [MO_SB | MO_LE] = LDSB, [MO_BEUW] = LDUH, [MO_BESW] = LDSH, [MO_BEUL] = LDUW, [MO_BESL] = LDSW, [MO_BEUQ] = LDX, + [MO_BESQ] = LDX, [MO_LEUW] = LDUH_LE, [MO_LESW] = LDSH_LE, [MO_LEUL] = LDUW_LE, [MO_LESL] = LDSW_LE, [MO_LEUQ] = LDX_LE, + [MO_LESQ] = LDX_LE, }; static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1] = { @@ -1184,11 +1219,12 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, MemOpIdx oi, bool is_64) { MemOp memop = get_memop(oi); + tcg_insn_unit *label_ptr; + #ifdef CONFIG_SOFTMMU unsigned memi = get_mmuidx(oi); TCGReg addrz, param; const tcg_insn_unit *func; - tcg_insn_unit *label_ptr; addrz = tcg_out_tlb_load(s, addr, memi, memop, offsetof(CPUTLBEntry, addr_read)); @@ -1252,13 +1288,99 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #else + TCGReg index = (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0); + unsigned a_bits = get_alignment_bits(memop); + unsigned s_bits = memop & MO_SIZE; + unsigned t_bits; + if (SPARC64 && TARGET_LONG_BITS == 32) { tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); addr = TCG_REG_T1; } - tcg_out_ldst_rr(s, data, addr, - (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0), + + /* + * Normal case: alignment equal to access size. + */ + if (a_bits == s_bits) { + tcg_out_ldst_rr(s, data, addr, index, + qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); + return; + } + + /* + * Test for at least natural alignment, and assume most accesses + * will be aligned -- perform a straight load in the delay slot. + * This is required to preserve atomicity for aligned accesses. + */ + t_bits = MAX(a_bits, s_bits); + tcg_debug_assert(t_bits < 13); + tcg_out_arithi(s, TCG_REG_G0, addr, (1u << t_bits) - 1, ARITH_ANDCC); + + /* beq,a,pt %icc, label */ + label_ptr = s->code_ptr; + tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT | BPCC_ICC, 0); + /* delay slot */ + tcg_out_ldst_rr(s, data, addr, index, qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); + + if (a_bits >= s_bits) { + /* + * Overalignment: A successful alignment test will perform the memory + * operation in the delay slot, and failure need only invoke the + * handler for SIGBUS. + */ + TCGReg arg_low = TCG_REG_O1 + (!SPARC64 && TARGET_LONG_BITS == 64); + tcg_out_call_nodelay(s, qemu_unalign_ld_trampoline, false); + /* delay slot -- move to low part of argument reg */ + tcg_out_mov_delay(s, arg_low, addr); + } else { + /* Underalignment: load by pieces of minimum alignment. */ + int ld_opc, a_size, s_size, i; + + /* + * Force full address into T1 early; avoids problems with + * overlap between @addr and @data. + */ + tcg_out_arith(s, TCG_REG_T1, addr, index, ARITH_ADD); + + a_size = 1 << a_bits; + s_size = 1 << s_bits; + if ((memop & MO_BSWAP) == MO_BE) { + ld_opc = qemu_ld_opc[a_bits | MO_BE | (memop & MO_SIGN)]; + tcg_out_ldst(s, data, TCG_REG_T1, 0, ld_opc); + ld_opc = qemu_ld_opc[a_bits | MO_BE]; + for (i = a_size; i < s_size; i += a_size) { + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, i, ld_opc); + tcg_out_arithi(s, data, data, a_size, SHIFT_SLLX); + tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR); + } + } else if (a_bits == 0) { + ld_opc = LDUB; + tcg_out_ldst(s, data, TCG_REG_T1, 0, ld_opc); + for (i = a_size; i < s_size; i += a_size) { + if ((memop & MO_SIGN) && i == s_size - a_size) { + ld_opc = LDSB; + } + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, i, ld_opc); + tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, i * 8, SHIFT_SLLX); + tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR); + } + } else { + ld_opc = qemu_ld_opc[a_bits | MO_LE]; + tcg_out_ldst_rr(s, data, TCG_REG_T1, TCG_REG_G0, ld_opc); + for (i = a_size; i < s_size; i += a_size) { + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, a_size, ARITH_ADD); + if ((memop & MO_SIGN) && i == s_size - a_size) { + ld_opc = qemu_ld_opc[a_bits | MO_LE | MO_SIGN]; + } + tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, ld_opc); + tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, i * 8, SHIFT_SLLX); + tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR); + } + } + } + + *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #endif /* CONFIG_SOFTMMU */ } @@ -1266,11 +1388,12 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, MemOpIdx oi) { MemOp memop = get_memop(oi); + tcg_insn_unit *label_ptr; + #ifdef CONFIG_SOFTMMU unsigned memi = get_mmuidx(oi); TCGReg addrz, param; const tcg_insn_unit *func; - tcg_insn_unit *label_ptr; addrz = tcg_out_tlb_load(s, addr, memi, memop, offsetof(CPUTLBEntry, addr_write)); @@ -1307,13 +1430,93 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #else + TCGReg index = (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0); + unsigned a_bits = get_alignment_bits(memop); + unsigned s_bits = memop & MO_SIZE; + unsigned t_bits; + if (SPARC64 && TARGET_LONG_BITS == 32) { tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); addr = TCG_REG_T1; } - tcg_out_ldst_rr(s, data, addr, - (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0), + + /* + * Normal case: alignment equal to access size. + */ + if (a_bits == s_bits) { + tcg_out_ldst_rr(s, data, addr, index, + qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); + return; + } + + /* + * Test for at least natural alignment, and assume most accesses + * will be aligned -- perform a straight store in the delay slot. + * This is required to preserve atomicity for aligned accesses. + */ + t_bits = MAX(a_bits, s_bits); + tcg_debug_assert(t_bits < 13); + tcg_out_arithi(s, TCG_REG_G0, addr, (1u << t_bits) - 1, ARITH_ANDCC); + + /* beq,a,pt %icc, label */ + label_ptr = s->code_ptr; + tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT | BPCC_ICC, 0); + /* delay slot */ + tcg_out_ldst_rr(s, data, addr, index, qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); + + if (a_bits >= s_bits) { + /* + * Overalignment: A successful alignment test will perform the memory + * operation in the delay slot, and failure need only invoke the + * handler for SIGBUS. + */ + TCGReg arg_low = TCG_REG_O1 + (!SPARC64 && TARGET_LONG_BITS == 64); + tcg_out_call_nodelay(s, qemu_unalign_st_trampoline, false); + /* delay slot -- move to low part of argument reg */ + tcg_out_mov_delay(s, arg_low, addr); + } else { + /* Underalignment: store by pieces of minimum alignment. */ + int st_opc, a_size, s_size, i; + + /* + * Force full address into T1 early; avoids problems with + * overlap between @addr and @data. + */ + tcg_out_arith(s, TCG_REG_T1, addr, index, ARITH_ADD); + + a_size = 1 << a_bits; + s_size = 1 << s_bits; + if ((memop & MO_BSWAP) == MO_BE) { + st_opc = qemu_st_opc[a_bits | MO_BE]; + for (i = 0; i < s_size; i += a_size) { + TCGReg d = data; + int shift = (s_size - a_size - i) * 8; + if (shift) { + d = TCG_REG_T2; + tcg_out_arithi(s, d, data, shift, SHIFT_SRLX); + } + tcg_out_ldst(s, d, TCG_REG_T1, i, st_opc); + } + } else if (a_bits == 0) { + tcg_out_ldst(s, data, TCG_REG_T1, 0, STB); + for (i = 1; i < s_size; i++) { + tcg_out_arithi(s, TCG_REG_T2, data, i * 8, SHIFT_SRLX); + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, i, STB); + } + } else { + /* Note that ST*A with immediate asi must use indexed address. */ + st_opc = qemu_st_opc[a_bits + MO_LE]; + tcg_out_ldst_rr(s, data, TCG_REG_T1, TCG_REG_G0, st_opc); + for (i = a_size; i < s_size; i += a_size) { + tcg_out_arithi(s, TCG_REG_T2, data, i * 8, SHIFT_SRLX); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, a_size, ARITH_ADD); + tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, st_opc); + } + } + } + + *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #endif /* CONFIG_SOFTMMU */ }