From patchwork Fri Feb 4 07:00:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 539862 Delivered-To: patch@linaro.org Received: by 2002:ac0:f7d2:0:0:0:0:0 with SMTP id i18csp3039035imr; Thu, 3 Feb 2022 23:39:37 -0800 (PST) X-Google-Smtp-Source: ABdhPJwXAZwYfzMJPp9N7AETyOmWi0QbXxz+X6whO8Ol9kApDpLrWJkXEqTdd9O1+GkQnsMSwYjc X-Received: by 2002:ac8:5905:: with SMTP id 5mr1185984qty.28.1643960376932; Thu, 03 Feb 2022 23:39:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1643960376; cv=none; d=google.com; s=arc-20160816; b=ZWVcMUwCCIwqx+hHXJafh/Zdl8P9vsJ2Prr/y3LBeNpyLjqI2AZv+bsSqgmPMCH2QK 1Z2uUjnVHzv0WXj1TAjvYRUTO8qeYNGYlLd2/7UksNTznYmVW24p37JEbcOD0Irax7zs KhhWrw4+02FkpzX+zRz+OjhYu+AgNPSOFT1r58zz6kUPNo7c4EOBkHg6HInGIllqjxsq 3jqXGA/Ak1GnFw3NPYWK4GMgBbSvDcNC+Xb+8YktAGNoBGm/pnmYEFHU6Qxa4k6p6vgE anwyYpzN64TM8A84CtoGRRVP+51savrmPvkTk7EmmwsKqRqUTYG2fTvt/cNMP5EUQS3/ qVfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uCnxeYPhfwcQZtAYiLYKNj7YwZATR9Ya833+hqWqAR4=; b=yF+Jn9riCbhDsMR8uGlVIsrA/7C0+QscH3qQzGU6i5nuSqUVMk7osok+IL0zODc5j9 sU/n3JErRqI6XvgwWJ7x1oM0sPLsN3osI30pOXBKNOJVZZ7JToaUKN9FOVUvz3fwAvP9 fxYCg779kwistraGWVL8tWyZUBmDGkrHWEYUf/xCTTrFr/QrdADeGGfiTFfJkZOY2B37 nmwvu6yeoBbSTp4b0sERJ708o6FmpNBgHQTgQxTSOHx60DxHhfKYwmTCe6rfrcp2r7I9 Ba06vyqwAqndDVT6FBvnOppKecs1gRghHPZ2dgH/1FDS2rNYEk78s9TSYRjdlpGD84Qr LOzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wBHIBcYM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u15si209168qtx.248.2022.02.03.23.39.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Feb 2022 23:39:36 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wBHIBcYM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nFtBw-0005xO-Fv for patch@linaro.org; Fri, 04 Feb 2022 02:39:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nFsa2-0006ak-H5 for qemu-devel@nongnu.org; Fri, 04 Feb 2022 02:00:26 -0500 Received: from [2607:f8b0:4864:20::42d] (port=37712 helo=mail-pf1-x42d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nFsZy-0006Sw-8o for qemu-devel@nongnu.org; Fri, 04 Feb 2022 02:00:25 -0500 Received: by mail-pf1-x42d.google.com with SMTP id y5so3403544pfe.4 for ; Thu, 03 Feb 2022 23:00:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uCnxeYPhfwcQZtAYiLYKNj7YwZATR9Ya833+hqWqAR4=; b=wBHIBcYMrwzrGPaUHorxI6LoQeOhECUFBmMRfcaTa7ccw/izbR+lCc9Ax+SOeqWn8c TlhzR6ZYHjRCwMWULD5s4HMdipcE4YNJk5P0CvUD1s8YqQBywVRof3x23dh0IYOUjg6D DnHHaia8P0phyDNXuWkjF87or4ps+fhy7CM2nOY5tdPSXGt8h+M6BjxsdBa3gmzL7VGH IbjoxJb8UOBos+ly3vbIF25MRQN5a12rtmGpLf1ADgSTztw79y/ddPVfI3JkfAit7QRV XU69xEFp1iE+jAxtb9Rqtfa71uTWqDEgftW1yyfigg7gO3fmqV3zv62qvdr1GqqyOp0T g9UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uCnxeYPhfwcQZtAYiLYKNj7YwZATR9Ya833+hqWqAR4=; b=3j7bzP6hIOGO0h54Tx/W9MVeAoySmQOcfRO5BJBI92rmzKaRJ2dvFfjAP8qoZ7z8Gk qVseu1/pgr3o3gydqiz8qsbZVnc7IC3BUM9uDYKFi4dlcnrveHS3r583miBgUIpM04s5 neagsFH7LmNbVVpPsBf09DyQMMU6EaJHD1rbzvZlb5+CjHjp2rvuaO2MQiDG9NFe+De9 Rs0ooeJ+VNeOLoZjVCZ9m8ED3jt+5T7KCaZuld+HN3tx0jpDaDj4twdCDWdcpdAfGhtk V7GYf+1nIbLp8CrmAw7J4ALGDl0Dnlmszn/Svfv/teHAnqnAM1rwHTKXz0vKU4nj/xw/ pTow== X-Gm-Message-State: AOAM532Fcdiq5V3QoVeCmLvPDAvwyvy47p03SS9fBBHkmBpevU9iHabC rP1Cv2QLmfsFrWji95Evs0nGC8ZtylAp856p X-Received: by 2002:a63:6983:: with SMTP id e125mr1337224pgc.574.1643958019969; Thu, 03 Feb 2022 23:00:19 -0800 (PST) Received: from stoup.modem ([2001:8003:3a49:fd00:ed23:b22a:8415:8857]) by smtp.gmail.com with ESMTPSA id 9sm11808619pjg.50.2022.02.03.23.00.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Feb 2022 23:00:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 1/5] tcg/sparc: Add scratch argument to tcg_out_movi_int Date: Fri, 4 Feb 2022 18:00:07 +1100 Message-Id: <20220204070011.573941-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220204070011.573941-1-richard.henderson@linaro.org> References: <20220204070011.573941-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will allow us to control exactly what scratch register is used for loading the constant. Also, fix a theoretical problem in recursing through tcg_out_movi, which may provide a different value for in_prologue. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 0c062c60eb..7e3758b798 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -414,7 +414,8 @@ static void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg) } static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long arg, bool in_prologue) + tcg_target_long arg, bool in_prologue, + TCGReg scratch) { tcg_target_long hi, lo = (int32_t)arg; tcg_target_long test, lsb; @@ -471,22 +472,24 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, /* A 64-bit constant decomposed into 2 32-bit pieces. */ if (check_fit_i32(lo, 13)) { hi = (arg - lo) >> 32; - tcg_out_movi(s, TCG_TYPE_I32, ret, hi); + tcg_out_movi_int(s, TCG_TYPE_I32, ret, hi, in_prologue, scratch); tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); } else { + tcg_debug_assert(scratch != TCG_REG_G0); hi = arg >> 32; - tcg_out_movi(s, TCG_TYPE_I32, ret, hi); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T2, lo); + tcg_out_movi_int(s, TCG_TYPE_I32, ret, hi, in_prologue, scratch); + tcg_out_movi_int(s, TCG_TYPE_I32, scratch, lo, in_prologue, TCG_REG_G0); tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); - tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR); + tcg_out_arith(s, ret, ret, scratch, ARITH_OR); } } static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { - tcg_out_movi_int(s, type, ret, arg, false); + tcg_debug_assert(ret != TCG_REG_T2); + tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T2); } static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, @@ -837,7 +840,7 @@ static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, } else { uintptr_t desti = (uintptr_t)dest; tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, - desti & ~0xfff, in_prologue); + desti & ~0xfff, in_prologue, TCG_REG_O7); tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL); } } @@ -1013,7 +1016,8 @@ static void tcg_target_qemu_prologue(TCGContext *s) #ifndef CONFIG_SOFTMMU if (guest_base != 0) { - tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, + true, TCG_REG_T1); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif From patchwork Fri Feb 4 07:00:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 539859 Delivered-To: patch@linaro.org Received: by 2002:ac0:f7d2:0:0:0:0:0 with SMTP id i18csp3029858imr; Thu, 3 Feb 2022 23:19:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJyeVyXj7gtCKVL8VcP/EwpJ5tuYixMDE6V/RAeLt8dTFMNfjWvPH7gsjU6qrsz7BOzRhDmI X-Received: by 2002:a25:4d41:: with SMTP id a62mr1691072ybb.560.1643959147390; Thu, 03 Feb 2022 23:19:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1643959147; cv=none; d=google.com; s=arc-20160816; b=0YKJOFt+hwBZVO9pcN9VZ7qYnJ7Z830IQWVh0dQ2Ccq/QKMOuy9nFUYn2MGFy/zAF2 KQK+zBvbHNafI41G9Etpon4QwmmGhH9CO7oBTfXSNLbFlp6nVRjSby+dqgjvm+i7faRG Bi2UyXJJ5fPBRZYQ8XUkJUzI/gjhOKwKFkBAaVAO2y3QD5seixbbYZAVGgYbZTqnUvPx BD4GzRwGFbPSQtCcZu6louQLoJ9iIf4Kj/9KkaAFNanDg6nJtVlFP7IESC/2NjnJeK+c mt1YXd0sd9xTWUVlo5NMTJIwjrCOWkGENbHWnFlVqssvyR3KhI/C9xHuShr5DVU5Ys++ tEZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xOfHTCwqJCAxGgD5mi+OdXnrE9oa2hucTy+9kx4K81s=; b=LBCSqdkkfOZv9IhgFRQ8ejFbxpO7QAKdLOtEKLjEicNP1N73JQ1dQuP86ryqFlIowh K7H/S9tORENvf5ioA0UstEqyQhSIxUxKR59vBPizCZGv4p0l3KG1lY723RkOviIFWpHI ZluMR6oTxOEzSBysOGGV89NqzNIdzwPJEsrHedxwAEE//8Vakcy1y+v55YCyY+vhTjOL fxcxzOMZDXyRKIF9qak4bDor6cMVmVpRpU1lk4/i0FLVyPeSP25QSK6DpngKWGNLc25Q pGgidPPmf8fmfLeGgPSF3cksMMv3Op18sWoMGs1+psDl+1yF83E2TrOYVQR3EYeqZ2dm FbeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cNcVKYYs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 8si653373ybw.222.2022.02.03.23.19.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Feb 2022 23:19:07 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cNcVKYYs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nFss5-0008Rl-Ex for patch@linaro.org; Fri, 04 Feb 2022 02:19:05 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35420) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nFsa2-0006ag-Bm for qemu-devel@nongnu.org; Fri, 04 Feb 2022 02:00:26 -0500 Received: from [2607:f8b0:4864:20::430] (port=33722 helo=mail-pf1-x430.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nFsa0-0006T4-5Q for qemu-devel@nongnu.org; Fri, 04 Feb 2022 02:00:25 -0500 Received: by mail-pf1-x430.google.com with SMTP id i186so4386042pfe.0 for ; Thu, 03 Feb 2022 23:00:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xOfHTCwqJCAxGgD5mi+OdXnrE9oa2hucTy+9kx4K81s=; b=cNcVKYYsC717X9pcvAio49fInKkmyOSZ6jLrewcUi0mJ/eS82oT0xuRqV3q9cJ5tM9 nJLzusWICXtm4JC9QlP98TqG8tsK++s0XZx0O9ABmzh1Uf3RbWU9r897U3jCdwE9UvMg rtUyZAkCOa2lteGG/M6Z8mmaJwwqD6fhTNrp76t/KXK1nHZ5peAcvwYCVEK4oOvqwPfk OUdVuRm4BrMyRZTFhicPIZsoMsR7ydewAblpvRXncxfP+xzoMWUO5RcAkSfmUty66FK/ HzEtDzM+wrsCEB5Ugp7UAVMWFiXC7gGq37+SzSlbVlU8NTytb10TlR9+f7xcRsBzbrg9 A2vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xOfHTCwqJCAxGgD5mi+OdXnrE9oa2hucTy+9kx4K81s=; b=NQAb0Zh6+5msDOntdgRh8riWpWSrcMSDIDvm7OHYFBqLB+8/QjuaU9flvqRVwR1kCf ubzJ4jg29ait+fge/bnS4Z6W4qXwEn0yYPMiCuuKqzikNLGxzB+nv37YTgCfpJA/JYL+ HZy0fDqUYqtfem9KBVV2Nl81nDNzNmnHb/G861POxiJG+FaWzz+0XuY/dfaTTy+/wc0e idQjmpADEdjQHO+chyvePu4ZN59s2VwYc1JMxuHRcamdSbHrndwiHPbWP1G7SQhBfxxg 5Aw5/zD2WgMWwJuXngpNRCtTwFGOeg/OKm1+QnD0OTkqs3K0D9GM2gjQLv8M9tOo76fQ huNw== X-Gm-Message-State: AOAM531GWj+aElHqD4+HkT7xGkzB4d4ztxkREYViEgy3Eahc/Gv/1Wpn J/ybc5xOz7iObE0RrImr139oiQfHRK3gU1hF X-Received: by 2002:a63:5f48:: with SMTP id t69mr1345295pgb.98.1643958022254; Thu, 03 Feb 2022 23:00:22 -0800 (PST) Received: from stoup.modem ([2001:8003:3a49:fd00:ed23:b22a:8415:8857]) by smtp.gmail.com with ESMTPSA id 9sm11808619pjg.50.2022.02.03.23.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Feb 2022 23:00:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 2/5] tcg/sparc: Improve code gen for shifted 32-bit constants Date: Fri, 4 Feb 2022 18:00:08 +1100 Message-Id: <20220204070011.573941-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220204070011.573941-1-richard.henderson@linaro.org> References: <20220204070011.573941-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::430 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We had code for checking for 13 and 21-bit shifted constants, but we can do better and allow 32-bit shifted constants. This is still 2 insns shorter than the full 64-bit sequence. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- tcg/sparc/tcg-target.c.inc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 7e3758b798..6349f750cc 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -456,17 +456,17 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, return; } - /* A 21-bit constant, shifted. */ + /* A 32-bit constant, shifted. */ lsb = ctz64(arg); test = (tcg_target_long)arg >> lsb; - if (check_fit_tl(test, 13)) { - tcg_out_movi_imm13(s, ret, test); - tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); - return; - } else if (lsb > 10 && test == extract64(test, 0, 21)) { + if (lsb > 10 && test == extract64(test, 0, 21)) { tcg_out_sethi(s, ret, test << 10); tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); return; + } else if (test == (uint32_t)test || test == (int32_t)test) { + tcg_out_movi_int(s, TCG_TYPE_I64, ret, test, in_prologue, scratch); + tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); + return; } /* A 64-bit constant decomposed into 2 32-bit pieces. */ From patchwork Fri Feb 4 07:00:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 539863 Delivered-To: patch@linaro.org Received: by 2002:ac0:f7d2:0:0:0:0:0 with SMTP id i18csp3039055imr; Thu, 3 Feb 2022 23:39:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJxCIiaMPYoyHNxwFlxBKuGLJ8jZ0+RaWXuROc600SF2IXcunnfKsCF2ctBAIow/dBU53y49 X-Received: by 2002:ac8:4e48:: with SMTP id e8mr1190661qtw.64.1643960380074; Thu, 03 Feb 2022 23:39:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1643960380; cv=none; d=google.com; s=arc-20160816; b=K4gMhcay+yrsYkmqth9ZZBG6q3FLfCldca3l5ctynRDGRcvzwEUYqG57RqrdIT2ZZC STtD63+ERhNfAJX0zUfxT2f8ed3q7Oe0EEeKjgDLkqNb7Zr3k8hcku8TIfMxdec/MkOq Flm4wag1KXfStbMLaFSFObNV2n/rLfXzGeyRUeM6B/L+mg9u1EZFRqcexZuwvvu6mJzd rUF7FPdY72oZro0Zo/dz8ckleqNGnrPBEMPsUDbvrYU7QpkuCSQ0tVflpy1xbSOCM+c+ pZ3XhaLFtqZ/TlOnkEKAKSm9w/kRk6dAxxd7JW7YSPKgugqKxdk4Qj/10Lr8myULd5H1 bojA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=l5/xMg5JmnQhX3P7JdxIT0db5qBXvDtWPFnoD+IGj8I=; b=muKga/otFuLw13/Q6DVy5eK/vwDg7pFBsVN7dgjtY9if/e+vOOnq+4Rc3FWb84OiY5 IY6CecQRSrcdJfWhq5LOV3n//j3jW2brUxOBkYeUwbXhWv94XhsAEMa0p+375Hdqi2o2 CScDp0bfUgw/eRGkduf/PloHohP5+hTnDzkyYj/6BZGMmJOhi4+IMjOnrAdkvR37tDfc KxAGF6xovwzqUfWLNybtwl2tVBT95UfR8sIsiqq2cCockP2nHwHFew/TWwOfEx0RLjPh cezItEty0KOXCgboi54Z9ugyJCPOmNCSjP98+b7dKbBAC8WK6aKfJeZLM4xhUfyTW0Mn 0x3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="bXJQ/8IB"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Thu, 03 Feb 2022 23:00:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 3/5] tcg/sparc: Use the constant pool for 64-bit constants Date: Fri, 4 Feb 2022 18:00:09 +1100 Message-Id: <20220204070011.573941-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220204070011.573941-1-richard.henderson@linaro.org> References: <20220204070011.573941-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/sparc/tcg-target.c.inc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 6349f750cc..47bdf314a0 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -332,6 +332,13 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type, insn &= ~INSN_OFF19(-1); insn |= INSN_OFF19(pcrel); break; + case R_SPARC_13: + if (!check_fit_ptr(value, 13)) { + return false; + } + insn &= ~INSN_IMM13(-1); + insn |= INSN_IMM13(value); + break; default: g_assert_not_reached(); } @@ -469,6 +476,14 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, return; } + /* Use the constant pool, if possible. */ + if (!in_prologue && USE_REG_TB) { + new_pool_label(s, arg, R_SPARC_13, s->code_ptr, + tcg_tbrel_diff(s, NULL)); + tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(TCG_REG_TB)); + return; + } + /* A 64-bit constant decomposed into 2 32-bit pieces. */ if (check_fit_i32(lo, 13)) { hi = (arg - lo) >> 32; From patchwork Fri Feb 4 07:00:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 539864 Delivered-To: patch@linaro.org Received: by 2002:ac0:f7d2:0:0:0:0:0 with SMTP id i18csp3039583imr; Thu, 3 Feb 2022 23:41:01 -0800 (PST) X-Google-Smtp-Source: ABdhPJwsN5iMbsUJlV5PnZeFanvWKcvtKW01mkZcu+WUrtAV9pbQaT82Il7aONHCEfsBCSxiG2dQ X-Received: by 2002:a05:622a:13cb:: with SMTP id p11mr1158836qtk.210.1643960461709; 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[209.51.188.17]) by mx.google.com with ESMTPS id z9si221789qtj.402.2022.02.03.23.41.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Feb 2022 23:41:01 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J4CjSjDr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34142 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nFtDD-0006xf-Q3 for patch@linaro.org; Fri, 04 Feb 2022 02:40:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35560) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nFsaM-0006gv-CN for qemu-devel@nongnu.org; Fri, 04 Feb 2022 02:00:51 -0500 Received: from [2607:f8b0:4864:20::f2e] (port=42694 helo=mail-qv1-xf2e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nFsaH-0006UJ-OO for qemu-devel@nongnu.org; Fri, 04 Feb 2022 02:00:45 -0500 Received: by mail-qv1-xf2e.google.com with SMTP id k9so4637869qvv.9 for ; Thu, 03 Feb 2022 23:00:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M0ZkQ1X6XeXxAobJERi5w3sTXAysUl6elMTzRVCZxPk=; b=J4CjSjDrJ1yHaOHhu4o07+uQV9aRHBd19us2cPXqAC2n7F/Xu69tH7j5BfPfm7ndV9 IV0O2mswJYpRlIQcuPkqcBKZa+3Vq9Xc2L2mYpBa/jSPSQClBgS5AWxY7/VEK3JLUrI9 /NV53H0s9OMku7qN6ef1UaVr5wV48TaStWN862GoFLr9kYJKk1hvZAr1c+Yq35JzfreK yc7+I8UTjU2ipSmrsq9InMe7Fyd4ewNRIkYbVPgDx/lFejcFuu6Wa/phWu+dsOSiILqU ks+uumGnym54wAQOYrA5rIC8tWk0hzu0bCoBzbyeOpKw5JubnwbY1Lx+2ki7OCJwQFLO UXFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M0ZkQ1X6XeXxAobJERi5w3sTXAysUl6elMTzRVCZxPk=; b=XW5nXTwxgSxJ9J4lfXR6kCMHOYzQxHxVGsv1K4D9NuSUsnKuddwOyLBl1fueOfyBmS XYFmw6fsbBfDQ+wi6JsuXF17mPrXd67T2dR08Zf2Y15jHqL36lHkrFrUU9dUwWBXcMpJ ZfKRsBKQ/Ry9emBFx7/a3elIwXSfZcSSj1oZNPNIGqdW6H5vRgfG7/K1uQNzTZIjS681 /+f0SpvlLyxlSmM8AuKAp/x5Zl4ccGkFV/yF+gNym2GAt5UniYeYRqdbBN8DWYtrRNhq 1bXfBnJRsUmCRx2Id3zLPMyG04+5u1YC3VDn7dAOxd3CLa2eeXGmZicTT/gW16qgSmTu TBEQ== X-Gm-Message-State: AOAM533ZFsrpf/pAz046foi4E7xIZO7gS1LxjC/9ciwdjJrSDzEsJuZO TLOFt4bECq3qrpyKxslsIMOWTAqXjy3wUivO X-Received: by 2002:aa7:96c1:: with SMTP id h1mr1784274pfq.17.1643958026807; Thu, 03 Feb 2022 23:00:26 -0800 (PST) Received: from stoup.modem ([2001:8003:3a49:fd00:ed23:b22a:8415:8857]) by smtp.gmail.com with ESMTPSA id 9sm11808619pjg.50.2022.02.03.23.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Feb 2022 23:00:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 4/5] tcg/sparc: Add tcg_out_jmpl_const for better tail calls Date: Fri, 4 Feb 2022 18:00:10 +1100 Message-Id: <20220204070011.573941-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220204070011.573941-1-richard.henderson@linaro.org> References: <20220204070011.573941-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::f2e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Due to mapping changes, we now rarely place the code_gen_buffer near the main executable. Which means that direct calls will now rarely be in range. So, always use indirect calls for tail calls, which allows us to avoid clobbering %o7, and therefore we need not save and restore it. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/sparc/tcg-target.c.inc | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 47bdf314a0..82a9d88816 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -845,6 +845,19 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); } +static void tcg_out_jmpl_const(TCGContext *s, const tcg_insn_unit *dest, + bool in_prologue, bool tail_call) +{ + uintptr_t desti = (uintptr_t)dest; + + /* Be careful not to clobber %o7 for a tail call. */ + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, + desti & ~0xfff, in_prologue, + tail_call ? TCG_REG_G2 : TCG_REG_O7); + tcg_out_arithi(s, tail_call ? TCG_REG_G0 : TCG_REG_O7, + TCG_REG_T1, desti & 0xfff, JMPL); +} + static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, bool in_prologue) { @@ -853,10 +866,7 @@ static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, if (disp == (int32_t)disp) { tcg_out32(s, CALL | (uint32_t)disp >> 2); } else { - uintptr_t desti = (uintptr_t)dest; - tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, - desti & ~0xfff, in_prologue, TCG_REG_O7); - tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL); + tcg_out_jmpl_const(s, dest, in_prologue, false); } } @@ -947,11 +957,10 @@ static void build_trampolines(TCGContext *s) /* Set the retaddr operand. */ tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); - /* Set the env operand. */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); /* Tail call. */ - tcg_out_call_nodelay(s, qemu_ld_helpers[i], true); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); + tcg_out_jmpl_const(s, qemu_ld_helpers[i], true, true); + /* delay slot -- set the env argument */ + tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); } for (i = 0; i < ARRAY_SIZE(qemu_st_helpers); ++i) { @@ -993,14 +1002,14 @@ static void build_trampolines(TCGContext *s) if (ra >= TCG_REG_O6) { tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK, TCG_TARGET_CALL_STACK_OFFSET); - ra = TCG_REG_G1; + } else { + tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); } - tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); - /* Set the env operand. */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); + /* Tail call. */ - tcg_out_call_nodelay(s, qemu_st_helpers[i], true); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); + tcg_out_jmpl_const(s, qemu_st_helpers[i], true, true); + /* delay slot -- set the env argument */ + tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); } } #endif From patchwork Fri Feb 4 07:00:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 539865 Delivered-To: patch@linaro.org Received: by 2002:ac0:f7d2:0:0:0:0:0 with SMTP id i18csp3048118imr; Fri, 4 Feb 2022 00:00:47 -0800 (PST) X-Google-Smtp-Source: ABdhPJz7M+V/lrg4foQkdXMbOzn5WZM8GmBh/t/empvr/EXx8a1419bygkllOVLjCvWWuY+YLEFX X-Received: by 2002:a05:622a:202:: with SMTP id b2mr1196959qtx.598.1643961647809; Fri, 04 Feb 2022 00:00:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1643961647; cv=none; d=google.com; s=arc-20160816; b=0oJEM66Q9xpL/yP7naNrMsA7zwkOoVsZxDdne8k3zK05oUf/hhvFQX/E5zhfpy8QF3 LPPebepehBcghbr1bcu3p8Onk298XhqpaUu6QofIPMr+U5UjlTDTdgvFTcVKkHvZ4nFo GTiUxuXrsrvBu6QcZsQPCKJ0rdExVxhQ0cNZD4DulNcqIzBuvfOgGFC3wQHGlsIGl7Ti npBp7QW00dplFxiDi4TO1ApGMBu9qq99krdWTSv3sPoK14ynkuls3z4o9pitMl7Vp2AG E5omP3sTTx9A+lK67uyVkp+eU1jKONxp94V93LMeQ9sML9hmUCOoYNDAPoWTMoW4fEuv Gy3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BTnTx+Np38oy93j629WdJsemD99NdxvV9Qe8c0rOlbY=; b=ZynRVoehuMYgGky0kyAn/7lOvDQxywHxXKdzpgeX7NRDZgm3r3Q6rWA2m40xhFjYsG YcyJrAIWKRpxA855irtiVYWZMkuF0h/BV/ecIN6RUyoOxv+Zf3YPiq3N9fQlFf+mlm+W 1Z37QSaFuO/DmN1OpVKulZBYuE6GpaMenvDO6dnl+ffNoPeBmd/uOfRrtJn45ohXdpzb oYHaDrF+/QxMojYlXt6LF/yPVJOIysmTWGWaY08OWH4Slx5rjC1wAjBxIyjmAOdd+vaZ ZvCUE6/a36k96zQQFXK4tWLf+Y7Ypoj5C95aZ9Nw9peNW+SWKXxPbvwCKiO6nMmZI9g/ RzXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ijlWdgQh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This inline code expansion is somewhat large, but it takes quite a few instructions to make a function call to a helper anyway. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 308 +++++++++++++++++++++++++++++++++++-- 1 file changed, 299 insertions(+), 9 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 82a9d88816..a0d206380c 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -211,6 +211,7 @@ static const int tcg_target_call_oarg_regs[] = { #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) +#define ARITH_ANDCC (INSN_OP(2) | INSN_OP3(0x11)) #define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) @@ -997,7 +998,7 @@ static void build_trampolines(TCGContext *s) /* Skip the oi argument. */ ra += 1; } - + /* Set the retaddr operand. */ if (ra >= TCG_REG_O6) { tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK, @@ -1012,6 +1013,38 @@ static void build_trampolines(TCGContext *s) tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); } } +#else +static const tcg_insn_unit *qemu_unalign_ld_trampoline; +static const tcg_insn_unit *qemu_unalign_st_trampoline; + +static void build_trampolines(TCGContext *s) +{ + for (int ld = 0; ld < 2; ++ld) { + void *helper; + + while ((uintptr_t)s->code_ptr & 15) { + tcg_out_nop(s); + } + + if (ld) { + helper = helper_unaligned_ld; + qemu_unalign_ld_trampoline = tcg_splitwx_to_rx(s->code_ptr); + } else { + helper = helper_unaligned_st; + qemu_unalign_st_trampoline = tcg_splitwx_to_rx(s->code_ptr); + } + + if (!SPARC64 && TARGET_LONG_BITS == 64) { + /* Install the high part of the address. */ + tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX); + } + + /* Tail call. */ + tcg_out_jmpl_const(s, helper, true, true); + /* delay slot -- set the env argument */ + tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); + } +} #endif /* Generate global QEMU prologue and epilogue code */ @@ -1062,9 +1095,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) /* delay slot */ tcg_out_movi_imm13(s, TCG_REG_O0, 0); -#ifdef CONFIG_SOFTMMU build_trampolines(s); -#endif } static void tcg_out_nop_fill(tcg_insn_unit *p, int count) @@ -1149,18 +1180,22 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, static const int qemu_ld_opc[(MO_SSIZE | MO_BSWAP) + 1] = { [MO_UB] = LDUB, [MO_SB] = LDSB, + [MO_UB | MO_LE] = LDUB, + [MO_SB | MO_LE] = LDSB, [MO_BEUW] = LDUH, [MO_BESW] = LDSH, [MO_BEUL] = LDUW, [MO_BESL] = LDSW, [MO_BEUQ] = LDX, + [MO_BESQ] = LDX, [MO_LEUW] = LDUH_LE, [MO_LESW] = LDSH_LE, [MO_LEUL] = LDUW_LE, [MO_LESL] = LDSW_LE, [MO_LEUQ] = LDX_LE, + [MO_LESQ] = LDX_LE, }; static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1] = { @@ -1179,11 +1214,12 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, MemOpIdx oi, bool is_64) { MemOp memop = get_memop(oi); + tcg_insn_unit *label_ptr; + #ifdef CONFIG_SOFTMMU unsigned memi = get_mmuidx(oi); TCGReg addrz, param; const tcg_insn_unit *func; - tcg_insn_unit *label_ptr; addrz = tcg_out_tlb_load(s, addr, memi, memop, offsetof(CPUTLBEntry, addr_read)); @@ -1247,13 +1283,190 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #else + TCGReg index = (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0); + unsigned a_bits = get_alignment_bits(memop); + unsigned s_bits = memop & MO_SIZE; + unsigned t_bits; + TCGReg orig_addr = addr; + if (SPARC64 && TARGET_LONG_BITS == 32) { tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); addr = TCG_REG_T1; } - tcg_out_ldst_rr(s, data, addr, - (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0), + + /* + * Normal case: alignment equal to access size. + */ + if (a_bits == s_bits) { + tcg_out_ldst_rr(s, data, addr, index, + qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); + return; + } + + /* + * Test for at least natural alignment, and assume most accesses + * will be aligned -- perform a straight load in the delay slot. + * This is required to preserve atomicity for aligned accesses. + */ + t_bits = MAX(a_bits, s_bits); + tcg_debug_assert(t_bits < 13); + tcg_out_arithi(s, TCG_REG_G0, addr, (1u << t_bits) - 1, ARITH_ANDCC); + + /* beq,a,pt %icc, label */ + label_ptr = s->code_ptr; + tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT | BPCC_ICC, 0); + /* delay slot */ + tcg_out_ldst_rr(s, data, addr, index, qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); + + /* + * Overalignment: When we're asking for really large alignment, + * the actual access is always done above and all we need to do + * here is invoke the handler for SIGBUS. + */ + if (a_bits >= s_bits) { + TCGReg arg_low = TCG_REG_O1 + (!SPARC64 && TARGET_LONG_BITS == 64); + tcg_out_call_nodelay(s, qemu_unalign_ld_trampoline, false); + /* delay slot -- move to low part of argument reg */ + tcg_out_mov_delay(s, arg_low, addr); + goto done; + } + + /* + * Underalignment: use multiple loads to perform the operation. + * + * Force full address into T1 early; avoids problems with + * overlap between @addr and @data. + * + * Note that the little-endian instructions use the immediate + * asi form, and must use tcg_out_ldst_rr. + */ + tcg_out_arith(s, TCG_REG_T1, addr, index, ARITH_ADD); + + switch ((unsigned)memop) { + case MO_BEUW | MO_UNALN: + case MO_BESW | MO_UNALN: + case MO_BEUL | MO_ALIGN_2: + case MO_BESL | MO_ALIGN_2: + case MO_BEUQ | MO_ALIGN_4: + /* Two loads: shift and combine. */ + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, 0, + qemu_ld_opc[a_bits | MO_BE | (memop & MO_SIGN)]); + tcg_out_ldst(s, data, TCG_REG_T1, 1 << a_bits, + qemu_ld_opc[a_bits | MO_BE]); + tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, 8 << a_bits, SHIFT_SLLX); + tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR); + break; + + case MO_LEUW | MO_UNALN: + case MO_LESW | MO_UNALN: + case MO_LEUL | MO_ALIGN_2: + case MO_LESL | MO_ALIGN_2: + case MO_LEUQ | MO_ALIGN_4: + /* Similarly, with shifts adjusted for little-endian. */ + tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, + qemu_ld_opc[a_bits | MO_LE]); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 1 << a_bits, ARITH_ADD); + tcg_out_ldst_rr(s, data, TCG_REG_T1, TCG_REG_G0, + qemu_ld_opc[a_bits | MO_LE | (memop & MO_SIGN)]); + tcg_out_arithi(s, data, data, 8 << a_bits, SHIFT_SLLX); + tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR); + break; + + case MO_BEUL | MO_UNALN: + case MO_BESL | MO_UNALN: + /* + * Naively, this would require 4 loads, 3 shifts, 3 ors. + * Use two 32-bit aligned loads, combine, and extract. + */ + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 3, ARITH_ANDN); + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, 0, LDUW); + tcg_out_ldst(s, TCG_REG_T1, TCG_REG_T1, 4, LDUW); + tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, 32, SHIFT_SLLX); + tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T2, ARITH_OR); + tcg_out_arithi(s, TCG_REG_T2, orig_addr, 3, ARITH_AND); + tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, 3, SHIFT_SLL); + tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T2, SHIFT_SLLX); + tcg_out_arithi(s, data, TCG_REG_T1, 32, + memop & MO_SIGN ? SHIFT_SRAX : SHIFT_SRLX); + break; + + case MO_LEUL | MO_UNALN: + case MO_LESL | MO_UNALN: + /* Similarly, with shifts adjusted for little-endian. */ + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 3, ARITH_ANDN); + tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, LDUW_LE); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 4, ARITH_ADD); + tcg_out_ldst_rr(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_G0, LDUW_LE); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 32, SHIFT_SLLX); + tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T2, ARITH_OR); + tcg_out_arithi(s, TCG_REG_T2, orig_addr, 3, ARITH_AND); + tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, 3, SHIFT_SLL); + tcg_out_arith(s, data, TCG_REG_T1, TCG_REG_T2, SHIFT_SRLX); + if (is_64) { + tcg_out_arithi(s, data, data, 0, + memop & MO_SIGN ? SHIFT_SRA : SHIFT_SRL); + } + break; + + case MO_BEUQ | MO_UNALN: + /* Similarly for 64-bit. */ + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 7, ARITH_ANDN); + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, 0, LDX); + tcg_out_ldst(s, TCG_REG_T1, TCG_REG_T1, 8, LDX); + tcg_out_arithi(s, data, orig_addr, 7, ARITH_AND); + tcg_out_arithi(s, data, data, 3, SHIFT_SLL); + tcg_out_arith(s, TCG_REG_T2, TCG_REG_T2, data, SHIFT_SLLX); + tcg_out_arithi(s, data, data, 64, ARITH_SUB); + tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, data, SHIFT_SRLX); + tcg_out_arith(s, data, TCG_REG_T1, TCG_REG_T2, ARITH_OR); + break; + + case MO_LEUQ | MO_UNALN: + /* Similarly for little-endian. */ + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 7, ARITH_ANDN); + tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, LDX_LE); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 8, ARITH_ADD); + tcg_out_ldst_rr(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_G0, LDX_LE); + tcg_out_arithi(s, data, orig_addr, 7, ARITH_AND); + tcg_out_arithi(s, data, data, 3, SHIFT_SLL); + tcg_out_arith(s, TCG_REG_T2, TCG_REG_T2, data, SHIFT_SRLX); + tcg_out_arithi(s, data, data, 64, ARITH_SUB); + tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, data, SHIFT_SLLX); + tcg_out_arith(s, data, TCG_REG_T1, TCG_REG_T2, ARITH_OR); + break; + + case MO_BEUQ | MO_ALIGN_2: + /* + * An extra test to verify alignment 2 is 5 insns, which + * is more than we would save by using the slightly smaller + * unaligned sequence above. + */ + tcg_out_ldst(s, data, TCG_REG_T1, 0, LDUH); + for (int i = 2; i < 8; i += 2) { + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, i, LDUW); + tcg_out_arithi(s, data, data, 16, SHIFT_SLLX); + tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR); + } + break; + + case MO_LEUQ | MO_ALIGN_2: + /* Similarly for little-endian. */ + tcg_out_ldst_rr(s, data, TCG_REG_T1, TCG_REG_G0, LDUH_LE); + for (int i = 2; i < 8; i += 2) { + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 2, ARITH_ADD); + tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, LDUW_LE); + tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, i * 8, SHIFT_SLLX); + tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR); + } + break; + + default: + g_assert_not_reached(); + } + + done: + *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #endif /* CONFIG_SOFTMMU */ } @@ -1261,11 +1474,12 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, MemOpIdx oi) { MemOp memop = get_memop(oi); + tcg_insn_unit *label_ptr; + #ifdef CONFIG_SOFTMMU unsigned memi = get_mmuidx(oi); TCGReg addrz, param; const tcg_insn_unit *func; - tcg_insn_unit *label_ptr; addrz = tcg_out_tlb_load(s, addr, memi, memop, offsetof(CPUTLBEntry, addr_write)); @@ -1302,13 +1516,89 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #else + TCGReg index = (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0); + unsigned a_bits = get_alignment_bits(memop); + unsigned s_bits = memop & MO_SIZE; + unsigned t_bits; + if (SPARC64 && TARGET_LONG_BITS == 32) { tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); addr = TCG_REG_T1; } - tcg_out_ldst_rr(s, data, addr, - (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0), + + /* + * Normal case: alignment equal to access size. + */ + if (a_bits == s_bits) { + tcg_out_ldst_rr(s, data, addr, index, + qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); + return; + } + + /* + * Test for at least natural alignment, and assume most accesses + * will be aligned -- perform a straight store in the delay slot. + * This is required to preserve atomicity for aligned accesses. + */ + t_bits = MAX(a_bits, s_bits); + tcg_debug_assert(t_bits < 13); + tcg_out_arithi(s, TCG_REG_G0, addr, (1u << t_bits) - 1, ARITH_ANDCC); + + /* beq,a,pt %icc, label */ + label_ptr = s->code_ptr; + tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT | BPCC_ICC, 0); + /* delay slot */ + tcg_out_ldst_rr(s, data, addr, index, qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); + + if (a_bits >= s_bits) { + TCGReg arg_low = TCG_REG_O1 + (!SPARC64 && TARGET_LONG_BITS == 64); + /* Overalignment: only need to call helper for SIGBUS. */ + tcg_out_call_nodelay(s, qemu_unalign_st_trampoline, false); + /* delay slot -- move to low part of argument reg */ + tcg_out_mov_delay(s, arg_low, addr); + } else { + /* Underalignment: store by pieces of minimum alignment. */ + int st_opc, a_size, s_size, i; + + /* + * Force full address into T1 early; avoids problems with + * overlap between @addr and @data. + */ + tcg_out_arith(s, TCG_REG_T1, addr, index, ARITH_ADD); + + a_size = 1 << a_bits; + s_size = 1 << (memop & MO_SIZE); + if ((memop & MO_BSWAP) == MO_BE) { + st_opc = qemu_st_opc[a_bits + MO_BE]; + for (i = 0; i < s_size; i += a_size) { + TCGReg d = data; + int shift = (s_size - a_size - i) * 8; + if (shift) { + d = TCG_REG_T2; + tcg_out_arithi(s, d, data, shift, SHIFT_SRLX); + } + tcg_out_ldst(s, d, TCG_REG_T1, i, st_opc); + } + } else if (a_bits == 0) { + tcg_out_ldst(s, data, TCG_REG_T1, 0, STB); + for (i = 1; i < s_size; i++) { + tcg_out_arithi(s, TCG_REG_T2, data, i * 8, SHIFT_SRLX); + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, i, STB); + } + } else { + /* Note that ST*A with immediate asi must use indexed address. */ + st_opc = qemu_st_opc[a_bits + MO_LE]; + tcg_out_ldst_rr(s, data, TCG_REG_T1, TCG_REG_G0, st_opc); + for (i = a_size; i < s_size; i += a_size) { + tcg_out_arithi(s, TCG_REG_T2, data, i * 8, SHIFT_SRLX); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, a_size, ARITH_ADD); + tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, st_opc); + } + } + } + + *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #endif /* CONFIG_SOFTMMU */ }