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Miller" , Tony Lindgren , Kishon Vijay Abraham I , Rob Herring CC: , Sekhar Nori , , , Andrew Lunn , , , Grygorii Strashko Subject: [PATCH linux-next 02/10] phy: ti: introduce phy-gmii-sel driver Date: Sun, 25 Nov 2018 18:15:23 -0600 Message-ID: <20181126001531.12974-3-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181126001531.12974-1-grygorii.strashko@ti.com> References: <20181126001531.12974-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces. The interface mode is selected by configuring the MII mode selection register(s) (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and bit fields placement in SCM are different between SoCs while fields meaning is the same. Historically CPSW external Port's interface mode selection configuration was introduced using custom API and driver cpsw-phy-sel.c. This leads to unnecessary driver, DT binding and custom API support effort. This patch introduces CPSW Port's PHY Interface Mode selection Driver (phy-gmii-sel) which implements standard Linux PHY interface and used as a replacement for TI's specific driver cpsw-phy-sel.c and corresponding custom API. Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Signed-off-by: Grygorii Strashko --- drivers/phy/ti/Kconfig | 10 ++ drivers/phy/ti/Makefile | 1 + drivers/phy/ti/phy-gmii-sel.c | 349 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 360 insertions(+) create mode 100644 drivers/phy/ti/phy-gmii-sel.c -- 2.10.5 diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig index 2050356..f137e01 100644 --- a/drivers/phy/ti/Kconfig +++ b/drivers/phy/ti/Kconfig @@ -76,3 +76,13 @@ config TWL4030_USB family chips (including the TWL5030 and TPS659x0 devices). This transceiver supports high and full speed devices plus, in host mode, low speed. + +config PHY_TI_GMII_SEL + tristate + default y if TI_CPSW=y + depends on TI_CPSW || COMPILE_TEST + select GENERIC_PHY + default m + help + This driver supports configuring of the TI CPSW Port mode depending on + the Ethernet PHY connected to the CPSW Port. diff --git a/drivers/phy/ti/Makefile b/drivers/phy/ti/Makefile index 9f36175..bea8f25 100644 --- a/drivers/phy/ti/Makefile +++ b/drivers/phy/ti/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_TI_GMII_SEL) += phy-gmii-sel.o diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c new file mode 100644 index 0000000..04ebf53 --- /dev/null +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Texas Instruments CPSW Port's PHY Interface Mode selection Driver + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on cpsw-phy-sel.c driver created by Mugunthan V N + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* AM33xx SoC specific definitions for the CONTROL port */ +#define AM33XX_GMII_SEL_MODE_MII 0 +#define AM33XX_GMII_SEL_MODE_RMII 1 +#define AM33XX_GMII_SEL_MODE_RGMII 2 + +enum { + PHY_GMII_SEL_PORT_MODE, + PHY_GMII_SEL_RGMII_ID_MODE, + PHY_GMII_SEL_RMII_IO_CLK_EN, + PHY_GMII_SEL_LAST, +}; + +struct phy_gmii_sel_phy_priv { + struct phy_gmii_sel_priv *priv; + u32 id; + struct phy *if_phy; + int rmii_clock_external; + int phy_if_mode; + struct regmap_field *fields[PHY_GMII_SEL_LAST]; +}; + +struct phy_gmii_sel_soc_data { + u32 num_ports; + u32 features; + const struct reg_field (*regfields)[PHY_GMII_SEL_LAST]; +}; + +struct phy_gmii_sel_priv { + struct device *dev; + const struct phy_gmii_sel_soc_data *soc_data; + struct regmap *regmap; + struct phy_provider *phy_provider; + struct phy_gmii_sel_phy_priv *if_phys; +}; + +static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct phy_gmii_sel_phy_priv *if_phy = phy_get_drvdata(phy); + const struct phy_gmii_sel_soc_data *soc_data = if_phy->priv->soc_data; + struct device *dev = if_phy->priv->dev; + struct regmap_field *regfield; + int ret, rgmii_id = 0; + u32 gmii_sel_mode = 0; + + if (mode != PHY_MODE_ETHERNET) + return -EINVAL; + + switch (submode) { + case PHY_INTERFACE_MODE_RMII: + gmii_sel_mode = AM33XX_GMII_SEL_MODE_RMII; + break; + + case PHY_INTERFACE_MODE_RGMII: + gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII; + break; + + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII; + rgmii_id = 1; + break; + + case PHY_INTERFACE_MODE_MII: + mode = AM33XX_GMII_SEL_MODE_MII; + break; + + default: + dev_warn(dev, + "port%u: unsupported mode: \"%s\". Defaulting to MII.\n", + if_phy->id, phy_modes(rgmii_id)); + return -EINVAL; + }; + + if_phy->phy_if_mode = submode; + + dev_dbg(dev, "%s id:%u mode:%u rgmii_id:%d rmii_clk_ext:%d\n", + __func__, if_phy->id, mode, rgmii_id, + if_phy->rmii_clock_external); + + regfield = if_phy->fields[PHY_GMII_SEL_PORT_MODE]; + ret = regmap_field_write(regfield, gmii_sel_mode); + if (ret) { + dev_err(dev, "port%u: set mode fail %d", if_phy->id, ret); + return ret; + } + + if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE) && + if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE]) { + regfield = if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE]; + ret = regmap_field_write(regfield, rgmii_id); + if (ret) + return ret; + } + + if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) && + if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN]) { + regfield = if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN]; + ret = regmap_field_write(regfield, + if_phy->rmii_clock_external); + } + + return 0; +} + +static const +struct reg_field phy_gmii_sel_fields_am33xx[][PHY_GMII_SEL_LAST] = { + { + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 0, 1), + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 4, 4), + [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 6, 6), + }, + { + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 2, 3), + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 5, 5), + [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 7, 7), + }, +}; + +static const +struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am33xx = { + .num_ports = 2, + .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) | + BIT(PHY_GMII_SEL_RMII_IO_CLK_EN), + .regfields = phy_gmii_sel_fields_am33xx, +}; + +static const +struct reg_field phy_gmii_sel_fields_dra7[][PHY_GMII_SEL_LAST] = { + { + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 0, 1), + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD((~0), 0, 0), + [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD((~0), 0, 0), + }, + { + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 4, 5), + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD((~0), 0, 0), + [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD((~0), 0, 0), + }, +}; + +static const +struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dra7 = { + .num_ports = 2, + .regfields = phy_gmii_sel_fields_dra7, +}; + +static const +struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dm814 = { + .num_ports = 2, + .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE), + .regfields = phy_gmii_sel_fields_am33xx, +}; + +static const struct of_device_id phy_gmii_sel_id_table[] = { + { + .compatible = "ti,am3352-phy-gmii-sel", + .data = &phy_gmii_sel_soc_am33xx, + }, + { + .compatible = "ti,dra7xx-phy-gmii-sel", + .data = &phy_gmii_sel_soc_dra7, + }, + { + .compatible = "ti,am43xx-phy-gmii-sel", + .data = &phy_gmii_sel_soc_am33xx, + }, + { + .compatible = "ti,dm814-phy-gmii-sel", + .data = &phy_gmii_sel_soc_dm814, + }, + {} +}; +MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table); + +static const struct phy_ops phy_gmii_sel_ops = { + .set_mode = phy_gmii_sel_mode, + .owner = THIS_MODULE, +}; + +static struct phy *phy_gmii_sel_of_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct phy_gmii_sel_priv *priv = dev_get_drvdata(dev); + int phy_id = args->args[0]; + + if (args->args_count < 1) + return ERR_PTR(-EINVAL); + if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) && + args->args_count < 2) + return ERR_PTR(-EINVAL); + if (!priv || !priv->if_phys) + return ERR_PTR(-ENODEV); + if (phy_id > priv->soc_data->num_ports) + return ERR_PTR(-EINVAL); + if (phy_id != priv->if_phys[phy_id - 1].id) + return ERR_PTR(-EINVAL); + + phy_id--; + if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN)) + priv->if_phys[phy_id].rmii_clock_external = args->args[1]; + dev_dbg(dev, "%s id:%u ext:%d\n", __func__, + priv->if_phys[phy_id].id, args->args[1]); + + return priv->if_phys[phy_id].if_phy; +} + +static int phy_gmii_sel_init_ports(struct phy_gmii_sel_priv *priv) +{ + const struct phy_gmii_sel_soc_data *soc_data = priv->soc_data; + struct device *dev = priv->dev; + struct phy_gmii_sel_phy_priv *if_phys; + int i, num_ports, ret; + + num_ports = priv->soc_data->num_ports; + + if_phys = devm_kcalloc(priv->dev, num_ports, + sizeof(*if_phys), GFP_KERNEL); + if (!if_phys) + return -ENOMEM; + dev_dbg(dev, "%s %d\n", __func__, num_ports); + + for (i = 0; i < num_ports; i++) { + const struct reg_field *field; + struct regmap_field *regfield; + + if_phys[i].id = i + 1; + if_phys[i].priv = priv; + + field = &soc_data->regfields[i][PHY_GMII_SEL_PORT_MODE]; + dev_dbg(dev, "%s field %x %d %d\n", __func__, + field->reg, field->msb, field->lsb); + + regfield = devm_regmap_field_alloc(dev, priv->regmap, *field); + if (IS_ERR(regfield)) + return PTR_ERR(regfield); + if_phys[i].fields[PHY_GMII_SEL_PORT_MODE] = regfield; + + field = &soc_data->regfields[i][PHY_GMII_SEL_RGMII_ID_MODE]; + if (field->reg != (~0)) { + regfield = devm_regmap_field_alloc(dev, + priv->regmap, + *field); + if (IS_ERR(regfield)) + return PTR_ERR(regfield); + if_phys[i].fields[PHY_GMII_SEL_RGMII_ID_MODE] = + regfield; + } + + field = &soc_data->regfields[i][PHY_GMII_SEL_RMII_IO_CLK_EN]; + if (field->reg != (~0)) { + regfield = devm_regmap_field_alloc(dev, + priv->regmap, + *field); + if (IS_ERR(regfield)) + return PTR_ERR(regfield); + if_phys[i].fields[PHY_GMII_SEL_RMII_IO_CLK_EN] = + regfield; + } + + if_phys[i].if_phy = devm_phy_create(dev, + priv->dev->of_node, + &phy_gmii_sel_ops); + if (IS_ERR(if_phys[i].if_phy)) { + ret = PTR_ERR(if_phys[i].if_phy); + dev_err(dev, "Failed to create phy%d %d\n", i, ret); + return ret; + } + phy_set_drvdata(if_phys[i].if_phy, &if_phys[i]); + } + + priv->if_phys = if_phys; + return 0; +} + +static int phy_gmii_sel_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + const struct of_device_id *of_id; + struct phy_gmii_sel_priv *priv; + int ret; + + of_id = of_match_node(phy_gmii_sel_id_table, pdev->dev.of_node); + if (!of_id) + return -EINVAL; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + priv->soc_data = of_id->data; + + priv->regmap = syscon_node_to_regmap(node->parent); + if (IS_ERR(priv->regmap)) { + ret = PTR_ERR(priv->regmap); + dev_err(dev, "Failed to get syscon %d\n", ret); + return ret; + } + + ret = phy_gmii_sel_init_ports(priv); + if (ret) + return ret; + + dev_set_drvdata(&pdev->dev, priv); + + priv->phy_provider = + devm_of_phy_provider_register(dev, + phy_gmii_sel_of_xlate); + if (IS_ERR(priv->phy_provider)) { + ret = PTR_ERR(priv->phy_provider); + dev_err(dev, "Failed to create phy provider %d\n", ret); + return ret; + } + + return 0; +} + +static struct platform_driver phy_gmii_sel_driver = { + .probe = phy_gmii_sel_probe, + .driver = { + .name = "phy-gmii-sel", + .of_match_table = phy_gmii_sel_id_table, + }, +}; +module_platform_driver(phy_gmii_sel_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Grygorii Strashko "); +MODULE_DESCRIPTION("TI CPSW Port's PHY Interface Mode selection Driver"); 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Miller" , Tony Lindgren , Kishon Vijay Abraham I , Rob Herring CC: , Sekhar Nori , , , Andrew Lunn , , , Grygorii Strashko Subject: [PATCH linux-next 03/10] dt-bindings: net: ti: cpsw: switch to use phy-gmii-sel phy Date: Sun, 25 Nov 2018 18:15:24 -0600 Message-ID: <20181126001531.12974-4-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181126001531.12974-1-grygorii.strashko@ti.com> References: <20181126001531.12974-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The cpsw-phy-sel driver was replaced with new PHY driver phy-gmii-sel, so deprecate cpsw-phy-sel bindings and update CPSW binding to use phy-gmii-sel PHY bindings. Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Signed-off-by: Grygorii Strashko --- Documentation/devicetree/bindings/net/cpsw.txt | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.10.5 diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt index b3acebe..3264e19 100644 --- a/Documentation/devicetree/bindings/net/cpsw.txt +++ b/Documentation/devicetree/bindings/net/cpsw.txt @@ -22,7 +22,8 @@ Required properties: - cpsw-phy-sel : Specifies the phandle to the CPSW phy mode selection device. See also cpsw-phy-sel.txt for it's binding. Note that in legacy cases cpsw-phy-sel may be - a child device instead of a phandle. + a child device instead of a phandle + (DEPRECATED, use phys property instead). Optional properties: - ti,hwmods : Must be "cpgmac0" @@ -44,6 +45,7 @@ Optional properties: Slave Properties: Required properties: - phy-mode : See ethernet.txt file in the same directory +- phys : phandle on phy-gmii-sel PHY (see phy/ti-phy-gmii-sel.txt) Optional properties: - dual_emac_res_vlan : Specifies VID to be used to segregate the ports @@ -85,12 +87,14 @@ Examples: phy-mode = "rgmii-txid"; /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 0>; }; cpsw_emac1: slave@1 { phy_id = <&davinci_mdio>, <1>; phy-mode = "rgmii-txid"; /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 0>; }; }; @@ -114,11 +118,13 @@ Examples: phy-mode = "rgmii-txid"; /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 0>; }; cpsw_emac1: slave@1 { phy_id = <&davinci_mdio>, <1>; phy-mode = "rgmii-txid"; /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 0>; }; }; From patchwork Mon Nov 26 00:15:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 151966 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4971570ljp; Sun, 25 Nov 2018 16:17:14 -0800 (PST) X-Google-Smtp-Source: AFSGD/UScC1LUNPfTAdMfTt/A+TP54Ud4kEE1x+dofka125qMcyqRJX4N87SCjAzOo5l7X3AKQnr X-Received: by 2002:a17:902:6909:: with SMTP id j9mr24514117plk.196.1543191434550; Sun, 25 Nov 2018 16:17:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543191434; cv=none; d=google.com; s=arc-20160816; b=eo6U0R2DpVQfvDrtdZ9aLx+SuW0k/7KqQUDZzV3jMpw0A1VtJA61Pnb2VL1PshXWUi TQjQXLDYybdpsb4Hbdlfz+de6wTJ7mmm/TF/9S0Gpmwy/9cmXOVDAimzdGUppaYxgBg5 Iufwy7DOh3q+I6crmvit+j84dZKBCeYxDgeU5/8AiJ0OG7JcBxFwctGtksGNxOE9YKL+ AUHLzdfUcpvFb9tQdF/J65DqigEjq6AGWmg4kWFMtyeEaRkzRIuncrlnk/Ks3RDuG1hb BASjBsmwnkuzJPrn3s8ACohwdrneNgQVb5eBerNbbVqc7pMXMnhSaH79V+KdyMvH+Qrm +6bA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=2Vit5RiZHib93dEny9PteOYqGtzGPo28jGCpaIBnV+s=; b=THc9wVwkDcVlTDjpDjqgwL2XJcYyDZkfCWgkZZ6PWlmtV94C/9VZRZ3eHbb2VbVLVY ndLCG2e1/FVTjQLAls826w9G8ArC9bkhNe6DksY0QwypUUtoenCiP4CUrcY+dMcJwwyH 68b1xWqYMs6UBl/X/OM1JFwLX0qNmX/zhJ+e/uN6foSUMkMLRyujPa7ove/Q7A1ZLsJv ACD/6p1MtzgrpRReDoaPXDK7XW2ltw2uF52QYX4Y0RXZbYf5FmK73HPitxdbYYf9zTCj b38pEeWUjmOR4jPvTGgYQt2PUgCCwBlrhsUo2cjWWZNzwCWmgdehkHajl0GzW5tNe4Ww e37w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eQVq07mc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Tony Lindgren , Kishon Vijay Abraham I , Rob Herring CC: , Sekhar Nori , , , Andrew Lunn , , , Grygorii Strashko Subject: [PATCH linux-next 06/10] ARM: dts: dm814x: switch to use phy-gmii-sel Date: Sun, 25 Nov 2018 18:15:27 -0600 Message-ID: <20181126001531.12974-7-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181126001531.12974-1-grygorii.strashko@ti.com> References: <20181126001531.12974-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel. Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Signed-off-by: Grygorii Strashko --- arch/arm/boot/dts/dm814x.dtsi | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) -- 2.10.5 diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 601c57a..413ae19 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -343,6 +343,12 @@ #size-cells = <1>; ranges = <0 0 0x800>; + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,dm814-phy-gmii-sel"; + reg = <0x650 0x4>; + #phy-cells = <1>; + }; + scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; @@ -549,17 +555,14 @@ cpsw_emac0: slave@4a100200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1>; + }; cpsw_emac1: slave@4a100300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; - }; - - phy_sel: cpsw-phy-sel@48140650 { - compatible = "ti,am3352-cpsw-phy-sel"; - reg= <0x48140650 0x4>; - reg-names = "gmii-sel"; + phys = <&phy_gmii_sel 2>; }; }; From patchwork Mon Nov 26 00:15:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 151965 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4971402ljp; Sun, 25 Nov 2018 16:17:01 -0800 (PST) X-Google-Smtp-Source: AFSGD/XFgOGWq1oQ1ka/e66UHI9AkKwxbhhEVqvtCLZNSxWhW4He3UwpWN3dG0Xxsjvr3px8lqY5 X-Received: by 2002:a63:78cd:: with SMTP id t196mr22679242pgc.62.1543191421537; Sun, 25 Nov 2018 16:17:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543191421; cv=none; d=google.com; s=arc-20160816; b=VzFIOz+Bvw/AWnyrbDljBqLlyj+4KIBFvOM7Pyn+nketkFR2i4rTkbWh17Wi1X1rOM S9gQP70llekOyp3WbxFUxZWTQRroL/j4ewQ1O/EeAlhgB757hdYHvLm8zW44uHajqGIl I85UCQR53cZWlCHco7VqYVit8TMmmvBKQVnHJbN6OGtPhfjbByOdsGmHCNb642KFH8sS vRfFV+DKPGIHj3DOJDtDS66wy5izBl1eCUuhrpIN52yVk1lmC1GoPQ/iOlFU4PgMRDz9 ORgiyl/sv/kDjOrTfZdU6BMwPo+fOHmrjpAsruqH5Iz66IKnEipB47bP/jAiGTnkMX9g RTDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=tO2aluYNB+YKg1lDnRoQJAWJh5Gddubs7Ch/wbkCKQY=; b=KIYWE0kpvDWayILBUTR8hXnueY2Hc9hi6a4gnGgQggmdKNu9J4YuRBvtiUGflDNr9Q qd+h0iirREi3z61emEmKaHgxLDXK67v174k+ekE3aq9CbCaoJMaZ+i6ezqspxgRM7gIV a6c8RXy2ZAjO7aomreIQTdMCCEadMYRz4H2oUryceWNT7RkT+elKmbKh+/mZcRR4aqfU WzIEHLFr0gv5UqEAEvzzCj2ROmAsl4ZxjWmWkL/EEKNOC5cey5ezpGylH1uf0Ezo607X XsXDqAQLdRw6MX5UCZrIZYH+ajJjWhEHSsy9iPGpmd6GwM2YaSV/gpBjTkK9MKW6Zmb4 b5mA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=YppOuXDG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Tony Lindgren , Kishon Vijay Abraham I , Rob Herring CC: , Sekhar Nori , , , Andrew Lunn , , , Grygorii Strashko Subject: [PATCH linux-next 07/10] ARM: dts: am4372: switch to use phy-gmii-sel Date: Sun, 25 Nov 2018 18:15:28 -0600 Message-ID: <20181126001531.12974-8-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181126001531.12974-1-grygorii.strashko@ti.com> References: <20181126001531.12974-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel. Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Signed-off-by: Grygorii Strashko --- arch/arm/boot/dts/am437x-l4.dtsi | 17 +++++++++-------- arch/arm/boot/dts/am43x-epos-evm.dts | 5 +---- 2 files changed, 10 insertions(+), 12 deletions(-) -- 2.10.5 diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index ff2c11e..121a71d 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -280,12 +280,6 @@ #size-cells = <1>; ranges = <0 0 0x4000>; - phy_sel: cpsw-phy-sel@650 { - compatible = "ti,am43xx-cpsw-phy-sel"; - reg= <0x650 0x4>; - reg-names = "gmii-sel"; - }; - am43xx_pinmux: pinmux@800 { compatible = "ti,am437-padconf", "pinctrl-single"; @@ -300,11 +294,17 @@ }; scm_conf: scm_conf@0 { - compatible = "syscon"; + compatible = "syscon", "simple-bus"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,am43xx-phy-gmii-sel"; + reg = <0x650 0x4>; + #phy-cells = <2>; + }; + scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; @@ -555,7 +555,6 @@ cpts_clock_shift = <29>; ranges = <0 0 0x8000>; syscon = <&scm_conf>; - cpsw-phy-sel = <&phy_sel>; davinci_mdio: mdio@1000 { compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio"; @@ -572,11 +571,13 @@ cpsw_emac0: slave@200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 0>; }; cpsw_emac1: slave@300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 0>; }; }; }; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 4ea753b..9dfd80e 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -584,10 +584,7 @@ &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rmii"; -}; - -&phy_sel { - rmii-clock-ext; + phys = <&phy_gmii_sel 1 1>; }; &i2c0 { From patchwork Mon Nov 26 00:15:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 151963 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4971172ljp; Sun, 25 Nov 2018 16:16:43 -0800 (PST) X-Google-Smtp-Source: AFSGD/VHQxaE0L6KEL6YZlR9sLEqc8iAMRjKvpyoD6D3bydx9pGKHereBh9pR4nrf+VFcWAQXj8w X-Received: by 2002:a63:d34a:: with SMTP id u10mr22911551pgi.301.1543191403421; Sun, 25 Nov 2018 16:16:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543191403; cv=none; d=google.com; s=arc-20160816; b=ttINjwgCdIDdapR6SU5/FsiPGR3HVUC9AP5YM7ywkgMTH6M6eBC/VmPKZyiM9yhdey 421IQPk6dpVPu7ch3Wf8ryeJv51hIWC49nkLPQyqrGC4IYPYRN9dSkNOy0+spAGX6Z+X XhLCbYNv+OFnbzC3JKbHACqI6+xTkuFHAbf502NZHhX8hIt3qYl/VjQ1M/Nh7+R1Krki 5CTdq5NglPPWgvI5Xxv52ef6eR0rv1DlLdIcJlJLThTt0bkJeSYy6/OU55ZOBw77Z5+7 ym96+sxWFM8pbISZafcrZQVV3koImafuy1rEl2vFp1LC0SBgsr/EK7OnD/AycfUs+srQ WxeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=wibd5CRYV6Uj19ty14uDoJlKqN1IRqXWZd8ylDb1+V4=; b=Hz6McD8abNantwjdVHyoho1mczhF4b7PQ1muHXs0LeEYogFp+tSJV1jsZXTrkaCc+F C/hjMrNN1eFtIsO9NVRS2IOYh8jIFhuyOaLsv/REVDyh9DJjeR+ixLTRjZnrzjoMxMEZ jfubnxyOLb8BB2UutoMPBw8t9Irc5u4jddYL5Zu2DDr3l5V+0NpWs8eip0nz2bp4SQCi izaRvRdxyIFtDQeOwiwfI82yY89Zj2n3pdY9LxOQRlhmaFO5prknz0JAIior6EJMywfC 0qbza1rZJsX/64oJWNZbjr4Y+nJeQmXlztPOFRfYsuo3PpRHt0ktQt+aCNVPiD3kICDe 3VpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RCEIAfgF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Tony Lindgren , Kishon Vijay Abraham I , Rob Herring CC: , Sekhar Nori , , , Andrew Lunn , , , Grygorii Strashko Subject: [PATCH linux-next 09/10] dt-bindings: net: ti: deprecate cpsw-phy-sel bindings Date: Sun, 25 Nov 2018 18:15:30 -0600 Message-ID: <20181126001531.12974-10-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181126001531.12974-1-grygorii.strashko@ti.com> References: <20181126001531.12974-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The cpsw-phy-sel driver was replaced with new PHY driver phy-gmii-sel, so deprecate cpsw-phy-sel bindings. Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Signed-off-by: Grygorii Strashko --- Documentation/devicetree/bindings/net/cpsw-phy-sel.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.10.5 diff --git a/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt b/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt index 764c0c7..5d76f99 100644 --- a/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt +++ b/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt @@ -1,4 +1,4 @@ -TI CPSW Phy mode Selection Device Tree Bindings +TI CPSW Phy mode Selection Device Tree Bindings (DEPRECATED) ----------------------------------------------- Required properties: From patchwork Mon Nov 26 00:15:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 151959 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4970712ljp; Sun, 25 Nov 2018 16:16:09 -0800 (PST) X-Google-Smtp-Source: AFSGD/W/bZAoSuL6EV6MWzPP/a4u698Mah21UtHQAq5FymQCs2bDDOq1I7Bgzk+dhNZJuL685CxD X-Received: by 2002:a63:6445:: with SMTP id y66mr23181142pgb.250.1543191369087; Sun, 25 Nov 2018 16:16:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543191369; cv=none; d=google.com; s=arc-20160816; b=Pq5PgRAg/JNoYiaN+blk+6wbY6k7j965pfcrYebW+81J81PqxdU5IEwG7ciLI0P82R w26bp5uRxRk61g1z1NsGDjp/JRJ8S7KugfTYEIbKwpfK9AZVBdMRypOKdwfFCy8kOJwH pN0ER9EaHEWa8QvDvembftdLKMj7hRs5GxmT0qM87P3GRzTscFkXNoqr3er9RIprolm5 qHlIDpZ7CalnvlfG/iRRjoIgtO7zAUhsmNM7DrLsVNk3ALia+y36iDPPnQZaBq4/E52l WAdHNwbvvpoh1NYVIBLnMN2+dmFZF9fFHiox+vX2D1BSFO2GRxUHMFr1Nw5Sc0wDLO2+ vP1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=85hfGuh+Ks3roiNMaMUxBKOuiJrYoqG3YSSqK90z+B4=; b=j2yEVgiHnVRztC2D6RszmDHCBMO0390mhoDkmvo68W87S9sI7zJFnjb6SZTeE7+QiY DUsNTD0SzSm8x8kyKc+xedo0FTZsHZjM8xfJ9WFW313vTYnCeR4mj8CxNxiqZC9WDJ+I uLPonk8htfqYQrkeAOAJssibBsNzb+bmFV952hPIqO/aiJ6fZSu8+OEx/yyXREp/6nsc KyfxLN1i5brEh+AHMPzFY+MXI57Uu+lZKpBxVFjKe9wRLVxrXmGF+GhZkoT6aroO3Ye3 1W2ohErR38ObzKBDpPZc0vrcwmncwKpuUZ3yKni5YUEJ15XALdc/YdDW+ZOxYD6h5dbl R7WQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Tony Lindgren , Kishon Vijay Abraham I , Rob Herring CC: , Sekhar Nori , , , Andrew Lunn , , , Grygorii Strashko Subject: [PATCH linux-next 10/10] net: ethernet: ti: cpsw: deprecate cpsw-phy-sel driver Date: Sun, 25 Nov 2018 18:15:31 -0600 Message-ID: <20181126001531.12974-11-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181126001531.12974-1-grygorii.strashko@ti.com> References: <20181126001531.12974-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Deprecate cpsw-phy-sel driver as it's been replaced with new TI phy-gmii-sel PHY driver. Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/Kconfig | 6 +++--- drivers/net/ethernet/ti/cpsw.h | 6 ++++++ 2 files changed, 9 insertions(+), 3 deletions(-) -- 2.10.5 diff --git a/drivers/net/ethernet/ti/Kconfig b/drivers/net/ethernet/ti/Kconfig index f932923..96415da 100644 --- a/drivers/net/ethernet/ti/Kconfig +++ b/drivers/net/ethernet/ti/Kconfig @@ -49,10 +49,11 @@ config TI_DAVINCI_CPDMA will be called davinci_cpdma. This is recommended. config TI_CPSW_PHY_SEL - bool + bool "TI CPSW Phy mode Selection (DEPRECATED)" + default n ---help--- This driver supports configuring of the phy mode connected to - the CPSW. + the CPSW. DEPRECATED: use PHY_TI_GMII_SEL. config TI_CPSW_ALE tristate "TI CPSW ALE Support" @@ -64,7 +65,6 @@ config TI_CPSW depends on ARCH_DAVINCI || ARCH_OMAP2PLUS || COMPILE_TEST select TI_DAVINCI_CPDMA select TI_DAVINCI_MDIO - select TI_CPSW_PHY_SEL select TI_CPSW_ALE select MFD_SYSCON select REGMAP diff --git a/drivers/net/ethernet/ti/cpsw.h b/drivers/net/ethernet/ti/cpsw.h index cf111db..907e05fc 100644 --- a/drivers/net/ethernet/ti/cpsw.h +++ b/drivers/net/ethernet/ti/cpsw.h @@ -21,7 +21,13 @@ ((mac)[2] << 16) | ((mac)[3] << 24)) #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) +#if IS_ENABLED(CONFIG_TI_CPSW_PHY_SEL) void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave); +#else +static inline +void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave) +{} +#endif int ti_cm_get_macid(struct device *dev, int slave, u8 *mac_addr); #endif /* __CPSW_H__ */