From patchwork Thu Feb 3 07:25:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 539701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4CF8C433EF for ; Thu, 3 Feb 2022 07:25:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242560AbiBCHZV (ORCPT ); Thu, 3 Feb 2022 02:25:21 -0500 Received: from mail-40140.protonmail.ch ([185.70.40.140]:50129 "EHLO mail-40140.protonmail.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232662AbiBCHZV (ORCPT ); Thu, 3 Feb 2022 02:25:21 -0500 Date: Thu, 03 Feb 2022 07:25:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail2; t=1643873119; bh=rroVZy+8mm+y9NJmmSBWrLbl8QRoHIsd7+BkHgYOTVg=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:In-Reply-To: References:From:To:Cc; b=DBYP77jMHRsBppbN6FldyHmlwGym/e9QVtnf8/aiLs2zukGlqbAUVeTDAyBAf3L8k qQj0yyaZ/lueegbKIw3ybl4xaZFTTqpL+gHU0mcptYF+RrNIGtreBTdMDl2i1XY3+Z uIaou8p9z+Ry2dxRF4q6wmHudPlzg/ORZFLhw4SneLjZN+5ZTvF3pUOPUIzI6tW5+D h7prvM0R2Lm5mVmj/NEbIPNwNtcIpSvQ0HVvPKmn4GH0/7rv4JV5rRnQr4mwxpWe4O YmxQzRLLTYSPgCsQc3xOt5gEC+OPk/vnMgd0VaAm/NRw9gIfVifaPWbBP6uNRZOOgz ZnLiEn4eRFtzw== To: Rob Herring , Bjorn Andersson , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org From: Yassine Oudjana Cc: Yassine Oudjana , linux-kernel@vger.kernel.org Reply-To: Yassine Oudjana Subject: [PATCH RESEND v3 1/7] dt-bindings: arm: qcom: Add msm8996 and apq8096 compatibles Message-ID: <20220203072226.51482-2-y.oudjana@protonmail.com> In-Reply-To: <20220203072226.51482-1-y.oudjana@protonmail.com> References: <20220203072226.51482-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add compatibles for MSM8996 and APQ8096 and all supported devices that have them. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/qcom.yaml | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 04ff0b55bb85..da6b2608f10b 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -172,7 +172,21 @@ properties: - const: qcom,apq8094 - items: - - const: qcom,msm8996-mtp + - enum: + - arrow,apq8096-db820c + - inforce,ifc6640 + - const: qcom,apq8096-sbc + - const: qcom,apq8096 + + - items: + - enum: + - qcom,msm8996-mtp + - sony,dora-row + - sony,kagura-row + - sony,keyaki-row + - xiaomi,gemini + - xiaomi,scorpio + - const: qcom,msm8996 - items: - enum: From patchwork Thu Feb 3 07:25:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 539700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF9E8C433F5 for ; Thu, 3 Feb 2022 07:25:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349368AbiBCHZ6 (ORCPT ); Thu, 3 Feb 2022 02:25:58 -0500 Received: from mail-4318.protonmail.ch ([185.70.43.18]:49219 "EHLO mail-4318.protonmail.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232662AbiBCHZ5 (ORCPT ); Thu, 3 Feb 2022 02:25:57 -0500 Date: Thu, 03 Feb 2022 07:25:49 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail2; t=1643873155; bh=BhVx/8CmQNBoQ1I8GQ67bJRSFTz/jB4S/vmeDj83nEc=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:In-Reply-To: References:From:To:Cc; b=Vx/7CuhMzffvYYDyfyUjOkAhUyHS94eZrv3g0ACbpR4DlJo7D5eRaM7arMBkUzDZE hAjPplJrBMf4A7Fpd9FXTfU3ZxALjRvml5yu4/QOqsK886Wy3FAqUDCQyWkInaGwas Um9TSTdw4CGPb7FwItjVyWsXwx6cEfBqOlHSDbd1r82fJ1AgdkBQn0CEIFs3jpaVQN PsdY3JDrIjA/LhwzC9W2RzdIb82rILxN7I2tCl9zO5DCJc8CimIRu3S0cIe6QwKjAs Fy6CBIUCljFFKgdoPFh3MJM7jh3nek+7WhxN11Kn6hjkSWZ2BrZkTE+ZXKJp+j1ata +JYKFzqaE3dCA== To: Rob Herring , Bjorn Andersson , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org From: Yassine Oudjana Cc: Yassine Oudjana , linux-kernel@vger.kernel.org Reply-To: Yassine Oudjana Subject: [PATCH RESEND v3 3/7] dt-bindings: opp: qcom-opp: Convert to DT schema Message-ID: <20220203072226.51482-4-y.oudjana@protonmail.com> In-Reply-To: <20220203072226.51482-1-y.oudjana@protonmail.com> References: <20220203072226.51482-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert qcom-opp.txt to DT schema format. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring --- .../bindings/opp/opp-v2-qcom-level.yaml | 60 +++++++++++++++++++ .../devicetree/bindings/opp/qcom-opp.txt | 19 ------ 2 files changed, 60 insertions(+), 19 deletions(-) create mode 100644 Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml delete mode 100644 Documentation/devicetree/bindings/opp/qcom-opp.txt diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml new file mode 100644 index 000000000000..14a7a689ad6d --- /dev/null +++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm OPP bindings to describe OPP nodes. + +maintainers: + - Niklas Cassel + +allOf: + - $ref: opp-v2-base.yaml# + +properties: + compatible: + const: operating-points-v2-qcom-level + +patternProperties: + '^opp-?[0-9]+$': + type: object + + properties: + opp-level: true + + qcom,opp-fuse-level: + description: | + A positive value representing the fuse corner/level associated with + this OPP node. Sometimes several corners/levels shares a certain fuse + corner/level. A fuse corner/level contains e.g. ref uV, min uV, + and max uV. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - opp-level + - qcom,opp-fuse-level + +required: + - compatible + +additionalProperties: false + +examples: + - | + cpr_opp_table: opp-table-cpr { + compatible = "operating-points-v2-qcom-level"; + + cpr_opp1: opp1 { + opp-level = <1>; + qcom,opp-fuse-level = <1>; + }; + cpr_opp2: opp2 { + opp-level = <2>; + qcom,opp-fuse-level = <2>; + }; + cpr_opp3: opp3 { + opp-level = <3>; + qcom,opp-fuse-level = <3>; + }; + }; diff --git a/Documentation/devicetree/bindings/opp/qcom-opp.txt b/Documentation/devicetree/bindings/opp/qcom-opp.txt deleted file mode 100644 index 41d3e4ff2dc3..000000000000 --- a/Documentation/devicetree/bindings/opp/qcom-opp.txt +++ /dev/null @@ -1,19 +0,0 @@ -Qualcomm OPP bindings to describe OPP nodes - -The bindings are based on top of the operating-points-v2 bindings -described in Documentation/devicetree/bindings/opp/opp-v2-base.yaml -Additional properties are described below. - -* OPP Table Node - -Required properties: -- compatible: Allow OPPs to express their compatibility. It should be: - "operating-points-v2-qcom-level" - -* OPP Node - -Required properties: -- qcom,opp-fuse-level: A positive value representing the fuse corner/level - associated with this OPP node. Sometimes several corners/levels shares - a certain fuse corner/level. A fuse corner/level contains e.g. ref uV, - min uV, and max uV. From patchwork Thu Feb 3 07:26:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 539699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7958C433EF for ; Thu, 3 Feb 2022 07:26:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349387AbiBCH0l (ORCPT ); Thu, 3 Feb 2022 02:26:41 -0500 Received: from mail-4027.protonmail.ch ([185.70.40.27]:30561 "EHLO mail-4027.protonmail.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239780AbiBCH0k (ORCPT ); Thu, 3 Feb 2022 02:26:40 -0500 Date: Thu, 03 Feb 2022 07:26:24 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail2; t=1643873199; bh=sR/YQB+9UhT4OEEpJHtDhmgJhmBoOU3G+c+isEuYc2M=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:In-Reply-To: References:From:To:Cc; b=L7I8i48AEjkvaGzpqm67XPHRxmYUv74nDisBs2akkn/5Bt+FYV8WzT9LTonnzNiYc p+G4RY0/s22DToWqP12Ftb4eFSZB/FGOEns4BSYqHqBUC/WNhBJr2syvMFTIf2wwzv yfs7puyGNP3UajyIMGRmThrY0JupX3Nx9T92o2fIKgthYYfDgorgxN4zNV7KP5xIu5 T+BMHcXhZqGJOZZPA96h+xz5ZNnq96d1JktgpuhBrOPXgONkD8oqUGmg4PLIvYzUxx N778Q3Kmn6cZ6pHJSvECWXgivUQDXCjNN1u0BPbEegVTKX/xEGNEHm4gJ+giUo85qL NCEmOrhmg8hag== To: Rob Herring , Bjorn Andersson , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org From: Yassine Oudjana Cc: Yassine Oudjana , linux-kernel@vger.kernel.org Reply-To: Yassine Oudjana Subject: [PATCH RESEND v3 5/7] arm64: dts: qcom: msm8996: Rename cluster OPP tables Message-ID: <20220203072226.51482-6-y.oudjana@protonmail.com> In-Reply-To: <20220203072226.51482-1-y.oudjana@protonmail.com> References: <20220203072226.51482-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rename cluster OPP table node names to match the nodename pattern defined in the opp-v2-base DT schema. Signed-off-by: Yassine Oudjana --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 91bc974aeb0a..036de52c54f1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -134,7 +134,7 @@ CPU_SLEEP_0: cpu-sleep-0 { }; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-cluster0 { compatible = "operating-points-v2-kryo-cpu"; nvmem-cells = <&speedbin_efuse>; opp-shared; @@ -222,7 +222,7 @@ opp-1593600000 { }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-cluster1 { compatible = "operating-points-v2-kryo-cpu"; nvmem-cells = <&speedbin_efuse>; opp-shared; From patchwork Thu Feb 3 07:26:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 539698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3991C433F5 for ; Thu, 3 Feb 2022 07:27:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349394AbiBCH1I (ORCPT ); Thu, 3 Feb 2022 02:27:08 -0500 Received: from mail-40137.protonmail.ch ([185.70.40.137]:33692 "EHLO mail-40137.protonmail.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239028AbiBCH1H (ORCPT ); Thu, 3 Feb 2022 02:27:07 -0500 Date: Thu, 03 Feb 2022 07:26:58 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail2; t=1643873225; bh=rjXtv8DjIMsE13KIuztdA6i3i1h+3p2yBsgPSWpIkBY=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:In-Reply-To: References:From:To:Cc; b=fdx50OH7O+EHnMXixx5811cAZUJ0AvsFBcxY3fVDup3oKxgAfOIYB+dnWyxFaSqKM zI5IR+p5Uir/ujU1I8X5YrEfAfVUE+2aBcoF4g19gEAoGJBDBsKPR/5G+3AE96h2+Z /0EZdfZwVDEOWNyjNYW6epbtoMPHsUr/LJEPCMuB0nVmlnVdr4/xNGHDjpmTR1Q1rQ bz+aUqih5CwbXV7skLoNHygXWzYdpK/g/gl86Y4gmTzX4zwcnpA4GVT3JOUnzRBy5H YEzD56ezVzKOqBurO/32ipIshlXPDuYlGNdHUH9EVTYipK+9WnYle59h0v5mSN7Ewo v/WIQqYQEtQTA== To: Rob Herring , Bjorn Andersson , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org From: Yassine Oudjana Cc: Yassine Oudjana , linux-kernel@vger.kernel.org Reply-To: Yassine Oudjana Subject: [PATCH RESEND v3 7/7] dt-bindings: power: avs: qcom,cpr: Convert to DT schema Message-ID: <20220203072226.51482-8-y.oudjana@protonmail.com> In-Reply-To: <20220203072226.51482-1-y.oudjana@protonmail.com> References: <20220203072226.51482-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert qcom,cpr.txt to DT schema format. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring --- Changes since v1: - Remove allOf from compatible. .../bindings/power/avs/qcom,cpr.txt | 130 -------------- .../bindings/power/avs/qcom,cpr.yaml | 160 ++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 161 insertions(+), 131 deletions(-) delete mode 100644 Documentation/devicetree/bindings/power/avs/qcom,cpr.txt create mode 100644 Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml diff --git a/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt deleted file mode 100644 index ab0d5ebbad4e..000000000000 --- a/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt +++ /dev/null @@ -1,130 +0,0 @@ -QCOM CPR (Core Power Reduction) - -CPR (Core Power Reduction) is a technology to reduce core power on a CPU -or other device. Each OPP of a device corresponds to a "corner" that has -a range of valid voltages for a particular frequency. While the device is -running at a particular frequency, CPR monitors dynamic factors such as -temperature, etc. and suggests adjustments to the voltage to save power -and meet silicon characteristic requirements. - -- compatible: - Usage: required - Value type: - Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404 - -- reg: - Usage: required - Value type: - Definition: base address and size of the rbcpr register region - -- interrupts: - Usage: required - Value type: - Definition: should specify the CPR interrupt - -- clocks: - Usage: required - Value type: - Definition: phandle to the reference clock - -- clock-names: - Usage: required - Value type: - Definition: must be "ref" - -- vdd-apc-supply: - Usage: required - Value type: - Definition: phandle to the vdd-apc-supply regulator - -- #power-domain-cells: - Usage: required - Value type: - Definition: should be 0 - -- operating-points-v2: - Usage: required - Value type: - Definition: A phandle to the OPP table containing the - performance states supported by the CPR - power domain - -- acc-syscon: - Usage: optional - Value type: - Definition: phandle to syscon for writing ACC settings - -- nvmem-cells: - Usage: required - Value type: - Definition: phandle to nvmem cells containing the data - that makes up a fuse corner, for each fuse corner. - As well as the CPR fuse revision. - -- nvmem-cell-names: - Usage: required - Value type: - Definition: should be "cpr_quotient_offset1", "cpr_quotient_offset2", - "cpr_quotient_offset3", "cpr_init_voltage1", - "cpr_init_voltage2", "cpr_init_voltage3", "cpr_quotient1", - "cpr_quotient2", "cpr_quotient3", "cpr_ring_osc1", - "cpr_ring_osc2", "cpr_ring_osc3", "cpr_fuse_revision" - for qcs404. - -Example: - - cpr_opp_table: cpr-opp-table { - compatible = "operating-points-v2-qcom-level"; - - cpr_opp1: opp1 { - opp-level = <1>; - qcom,opp-fuse-level = <1>; - }; - cpr_opp2: opp2 { - opp-level = <2>; - qcom,opp-fuse-level = <2>; - }; - cpr_opp3: opp3 { - opp-level = <3>; - qcom,opp-fuse-level = <3>; - }; - }; - - power-controller@b018000 { - compatible = "qcom,qcs404-cpr", "qcom,cpr"; - reg = <0x0b018000 0x1000>; - interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; - clocks = <&xo_board>; - clock-names = "ref"; - vdd-apc-supply = <&pms405_s3>; - #power-domain-cells = <0>; - operating-points-v2 = <&cpr_opp_table>; - acc-syscon = <&tcsr>; - - nvmem-cells = <&cpr_efuse_quot_offset1>, - <&cpr_efuse_quot_offset2>, - <&cpr_efuse_quot_offset3>, - <&cpr_efuse_init_voltage1>, - <&cpr_efuse_init_voltage2>, - <&cpr_efuse_init_voltage3>, - <&cpr_efuse_quot1>, - <&cpr_efuse_quot2>, - <&cpr_efuse_quot3>, - <&cpr_efuse_ring1>, - <&cpr_efuse_ring2>, - <&cpr_efuse_ring3>, - <&cpr_efuse_revision>; - nvmem-cell-names = "cpr_quotient_offset1", - "cpr_quotient_offset2", - "cpr_quotient_offset3", - "cpr_init_voltage1", - "cpr_init_voltage2", - "cpr_init_voltage3", - "cpr_quotient1", - "cpr_quotient2", - "cpr_quotient3", - "cpr_ring_osc1", - "cpr_ring_osc2", - "cpr_ring_osc3", - "cpr_fuse_revision"; - }; diff --git a/Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml b/Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml new file mode 100644 index 000000000000..3301fa0c2653 --- /dev/null +++ b/Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/avs/qcom,cpr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Core Power Reduction (CPR) bindings + +maintainers: + - Niklas Cassel + +description: | + CPR (Core Power Reduction) is a technology to reduce core power on a CPU + or other device. Each OPP of a device corresponds to a "corner" that has + a range of valid voltages for a particular frequency. While the device is + running at a particular frequency, CPR monitors dynamic factors such as + temperature, etc. and suggests adjustments to the voltage to save power + and meet silicon characteristic requirements. + +properties: + compatible: + items: + - enum: + - qcom,qcs404-cpr + - const: qcom,cpr + + reg: + description: Base address and size of the RBCPR register region. + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Reference clock. + + clock-names: + items: + - const: ref + + vdd-apc-supply: + description: APC regulator supply. + + '#power-domain-cells': + const: 0 + + operating-points-v2: + description: | + A phandle to the OPP table containing the performance states + supported by the CPR power domain. + + acc-syscon: + description: A phandle to the syscon used for writing ACC settings. + + nvmem-cells: + items: + - description: Corner 1 quotient offset + - description: Corner 2 quotient offset + - description: Corner 3 quotient offset + - description: Corner 1 initial voltage + - description: Corner 2 initial voltage + - description: Corner 3 initial voltage + - description: Corner 1 quotient + - description: Corner 2 quotient + - description: Corner 3 quotient + - description: Corner 1 ring oscillator + - description: Corner 2 ring oscillator + - description: Corner 3 ring oscillator + - description: Fuse revision + + nvmem-cell-names: + items: + - const: cpr_quotient_offset1 + - const: cpr_quotient_offset2 + - const: cpr_quotient_offset3 + - const: cpr_init_voltage1 + - const: cpr_init_voltage2 + - const: cpr_init_voltage3 + - const: cpr_quotient1 + - const: cpr_quotient2 + - const: cpr_quotient3 + - const: cpr_ring_osc1 + - const: cpr_ring_osc2 + - const: cpr_ring_osc3 + - const: cpr_fuse_revision + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - vdd-apc-supply + - '#power-domain-cells' + - operating-points-v2 + - nvmem-cells + - nvmem-cell-names + +additionalProperties: false + +examples: + - | + #include + + cpr_opp_table: opp-table-cpr { + compatible = "operating-points-v2-qcom-level"; + + cpr_opp1: opp1 { + opp-level = <1>; + qcom,opp-fuse-level = <1>; + }; + cpr_opp2: opp2 { + opp-level = <2>; + qcom,opp-fuse-level = <2>; + }; + cpr_opp3: opp3 { + opp-level = <3>; + qcom,opp-fuse-level = <3>; + }; + }; + + power-controller@b018000 { + compatible = "qcom,qcs404-cpr", "qcom,cpr"; + reg = <0x0b018000 0x1000>; + interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; + clocks = <&xo_board>; + clock-names = "ref"; + vdd-apc-supply = <&pms405_s3>; + #power-domain-cells = <0>; + operating-points-v2 = <&cpr_opp_table>; + acc-syscon = <&tcsr>; + + nvmem-cells = <&cpr_efuse_quot_offset1>, + <&cpr_efuse_quot_offset2>, + <&cpr_efuse_quot_offset3>, + <&cpr_efuse_init_voltage1>, + <&cpr_efuse_init_voltage2>, + <&cpr_efuse_init_voltage3>, + <&cpr_efuse_quot1>, + <&cpr_efuse_quot2>, + <&cpr_efuse_quot3>, + <&cpr_efuse_ring1>, + <&cpr_efuse_ring2>, + <&cpr_efuse_ring3>, + <&cpr_efuse_revision>; + nvmem-cell-names = "cpr_quotient_offset1", + "cpr_quotient_offset2", + "cpr_quotient_offset3", + "cpr_init_voltage1", + "cpr_init_voltage2", + "cpr_init_voltage3", + "cpr_quotient1", + "cpr_quotient2", + "cpr_quotient3", + "cpr_ring_osc1", + "cpr_ring_osc2", + "cpr_ring_osc3", + "cpr_fuse_revision"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 8a024490a1f8..e365a6903787 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15889,7 +15889,7 @@ M: Niklas Cassel L: linux-pm@vger.kernel.org L: linux-arm-msm@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/power/avs/qcom,cpr.txt +F: Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml F: drivers/soc/qcom/cpr.c QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096