From patchwork Thu Feb 3 17:06:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 539679 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63C85C43217 for ; Thu, 3 Feb 2022 17:06:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352491AbiBCRGu (ORCPT ); Thu, 3 Feb 2022 12:06:50 -0500 Received: from relmlor1.renesas.com ([210.160.252.171]:19627 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1352493AbiBCRGs (ORCPT ); Thu, 3 Feb 2022 12:06:48 -0500 X-IronPort-AV: E=Sophos;i="5.88,340,1635174000"; d="scan'208";a="108564570" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 04 Feb 2022 02:06:48 +0900 Received: from localhost.localdomain (unknown [10.226.92.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1A03440B184E; Fri, 4 Feb 2022 02:06:45 +0900 (JST) From: Biju Das To: Rob Herring Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH v3 2/4] arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings Date: Thu, 3 Feb 2022 17:06:34 +0000 Message-Id: <20220203170636.7747-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220203170636.7747-1-biju.das.jz@bp.renesas.com> References: <20220203170636.7747-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org RZ/G2LC SoM uses DIP-SWitch SW1 for various pin multiplexing functions. This patch describes DIP-SWitch SW1 settings on SoM and adds the corresponding macros for enabling pinmux functionality on RZ/G2LC SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- v2->v3: No change v1->v2: No change --- .../boot/dts/renesas/r9a07g044c2-smarc.dts | 4 +-- arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 36 +++++++++++++++++++ 2 files changed, 37 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index af84fd6c8a81..50abdabc374a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -7,9 +7,7 @@ /dts-v1/; #include "r9a07g044c2.dtsi" -#include "rzg2lc-smarc-som.dtsi" -#include "rzg2lc-smarc-pinfunction.dtsi" -#include "rz-smarc-common.dtsi" +#include "rzg2lc-smarc.dtsi" / { model = "Renesas SMARC EVK based on r9a07g044c2"; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi new file mode 100644 index 000000000000..ca5ca7ce6692 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC SMARC EVK parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +/* + * DIP-Switch SW1 setting on SoM + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD) + * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1) + * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1) + * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0) + * Please change below macros according to SW1 setting + */ + +#define SW_SCIF_CAN 0 +#if (SW_SCIF_CAN) +/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */ +#define SW_RSPI_CAN 0 +#else +/* Please set SW_RSPI_CAN. Default value is 1 */ +#define SW_RSPI_CAN 1 +#endif + +#if (SW_SCIF_CAN & SW_RSPI_CAN) +#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" +#endif + +#include "rzg2lc-smarc-som.dtsi" +#include "rzg2lc-smarc-pinfunction.dtsi" +#include "rz-smarc-common.dtsi" From patchwork Thu Feb 3 17:06:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 539678 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D12DAC4332F for ; Thu, 3 Feb 2022 17:06:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229671AbiBCRG4 (ORCPT ); Thu, 3 Feb 2022 12:06:56 -0500 Received: from relmlor2.renesas.com ([210.160.252.172]:40671 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1352501AbiBCRGx (ORCPT ); Thu, 3 Feb 2022 12:06:53 -0500 X-IronPort-AV: E=Sophos;i="5.88,340,1635174000"; d="scan'208";a="109262256" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 04 Feb 2022 02:06:53 +0900 Received: from localhost.localdomain (unknown [10.226.92.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 2E4B940B184E; Fri, 4 Feb 2022 02:06:50 +0900 (JST) From: Biju Das To: Rob Herring Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH v3 4/4] arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1 Date: Thu, 3 Feb 2022 17:06:36 +0000 Message-Id: <20220203170636.7747-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220203170636.7747-1-biju.das.jz@bp.renesas.com> References: <20220203170636.7747-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On RZ/G2LC SMARC EVK, CAN0 is not populated. CAN1 is multiplexed with SCIF1 using SW1[3] or RSPI using SW1[4]. This patch adds support for the CAN1 interface on RZ/G2LC SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- v2->v3: No change v1->v2: No change --- .../boot/dts/renesas/r9a07g044c2-smarc.dts | 6 ----- .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 23 +++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 13 +++++++++++ 3 files changed, 36 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 50abdabc374a..5a5cea82a5d9 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -14,12 +14,6 @@ compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; }; -&canfd { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &ehci0 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index ec9e08ec0822..bff56d696936 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -17,6 +17,14 @@ ; /* RxD */ }; +#if SW_SCIF_CAN + /* SW8 should be at position 2->1 */ + can1_pins: can1 { + pinmux = , /* TxD */ + ; /* RxD */ + }; +#endif + scif1_pins: scif1 { pinmux = , /* TxD */ , /* RxD */ @@ -24,6 +32,21 @@ ; /* RTS# */ }; +#if SW_RSPI_CAN + /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ + can1-stb { + gpio-hog; + gpios = ; + output-low; + line-name = "can1_stb"; + }; + + can1_pins: can1 { + pinmux = , /* TxD */ + ; /* RxD */ + }; +#endif + sd1-pwr-en-hog { gpio-hog; gpios = ; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 1b59ef376296..28f21c287ba3 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -44,6 +44,19 @@ }; }; +#if (SW_SCIF_CAN || SW_RSPI_CAN) +&canfd { + pinctrl-0 = <&can1_pins>; + /delete-node/ channel@0; +}; +#else +&canfd { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; +#endif + /* * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board * SW1 should be at position 2->3 so that SER0_CTS# line is activated