From patchwork Wed Feb 2 17:25:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 539428 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD5C9C433F5 for ; Wed, 2 Feb 2022 17:25:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244839AbiBBRZ5 (ORCPT ); Wed, 2 Feb 2022 12:25:57 -0500 Received: from so254-9.mailgun.net ([198.61.254.9]:33487 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237656AbiBBRZ4 (ORCPT ); Wed, 2 Feb 2022 12:25:56 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1643822756; h=Message-Id: Date: Subject: Cc: To: From: Sender; bh=CNruI/g+gBVAdYPEy22ABVFeKz4l119XLs0dajq3y/Y=; b=AsjW6C6Ji2E9m4fa9uUykhTpuzjGWezJADzBJGKALqoowpWdRECWy9RywjpDIhUKYjCKPoiq EeXfyJ81CLdfu8flj7USFDt/ELvfXxn56Pa4mmqdFmkTLfC9fuIyJseGAuTNNHRViedx/qpx DjIVTNu4O85LHJhkYSv6VL2KuzU= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n07.prod.us-east-1.postgun.com with SMTP id 61fabea242b0db82d29c865f (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 02 Feb 2022 17:25:54 GMT Sender: tdas=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 97D72C4360C; Wed, 2 Feb 2022 17:25:53 +0000 (UTC) Received: from hu-tdas-hyd.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: tdas) by smtp.codeaurora.org (Postfix) with ESMTPSA id 636AEC4338F; Wed, 2 Feb 2022 17:25:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.codeaurora.org 636AEC4338F Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=codeaurora.org From: Taniya Das To: Stephen Boyd , =?utf-8?q?Michael_Turquette_=C2=A0?= Cc: Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh@kernel.org, robh+dt@kernel.org, Taniya Das Subject: [PATCH v2 1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG Date: Wed, 2 Feb 2022 22:55:39 +0530 Message-Id: <20220202172540.2458-1-tdas@codeaurora.org> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The current implementation does not check for D value is within the accepted range for a given M & N value. Update the logic to calculate the final D value based on the range. Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks") Signed-off-by: Taniya Das Reviewed-by: Stephen Boyd --- * Split the patch and update the Fixes tag. drivers/clk/qcom/clk-rcg2.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation. diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index e1b1b426fae4..34251ec98def 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -264,7 +264,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw, static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) { - u32 cfg, mask; + u32 cfg, mask, d_val, not2d_val; struct clk_hw *hw = &rcg->clkr.hw; int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); @@ -283,8 +283,18 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) if (ret) return ret; + /* Calculate 2d value */ + d_val = f->n; + + if (d_val > ((f->n - f->m) * 2)) + d_val = (f->n - f->m) * 2; + else if (d_val < f->m) + d_val = f->m; + + not2d_val = ~d_val & mask; + ret = regmap_update_bits(rcg->clkr.regmap, - RCG_D_OFFSET(rcg), mask, ~f->n); + RCG_D_OFFSET(rcg), mask, not2d_val); if (ret) return ret; } From patchwork Wed Feb 2 17:42:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 539427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A250C43219 for ; Wed, 2 Feb 2022 17:42:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346323AbiBBRmb (ORCPT ); Wed, 2 Feb 2022 12:42:31 -0500 Received: from so254-9.mailgun.net ([198.61.254.9]:32579 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229816AbiBBRmb (ORCPT ); Wed, 2 Feb 2022 12:42:31 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1643823751; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=XXGHacUGDA8T2oMG/LGqkka2QKznuATpVP6h9ySIS9s=; b=QTqMCp4dfyg/CeAHqucHP7pDRRfFnqA1Wg4fGn/JtO7pnX2opTGN7LTtmp95VNCEwxSVAQA8 lwLav6Cz+8BluHZmCvj1nRD7J7K1LOn0CSMGy/VwDs+UaOgzX+ROoiRjWMnjye4QKoPq9B9e 4aVw+FlKOqEh1U8OMc/uLaha0To= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n07.prod.us-west-2.postgun.com with SMTP id 61fac286d9f69c72767482c4 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 02 Feb 2022 17:42:30 GMT Sender: tdas=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 66835C43616; Wed, 2 Feb 2022 17:42:30 +0000 (UTC) Received: from hu-tdas-hyd.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: tdas) by smtp.codeaurora.org (Postfix) with ESMTPSA id 26728C4338F; Wed, 2 Feb 2022 17:42:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.codeaurora.org 26728C4338F Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=codeaurora.org From: Taniya Das To: Stephen Boyd , =?utf-8?q?Michael_Turquette_=C2=A0?= Cc: Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das Subject: [PATCH v2 2/2] clk: qcom: clk-alpha-pll: Update to use determine rate ops for PLL Date: Wed, 2 Feb 2022 23:12:13 +0530 Message-Id: <20220202174213.21259-2-tdas@codeaurora.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220202174213.21259-1-tdas@codeaurora.org> References: <20220202174213.21259-1-tdas@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 32 bit devices, where the PLL requires to support the frequency beyond the range of the `long int` the round rate ops cannot support. Thus update the clk_ops to use determine rate instead. Fixes: 134b55b7e19f8 ("clk: qcom: support Huayra type Alpha PLL") Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation. diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 4406cf609aae..4e2e93cd8c8b 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -812,12 +812,25 @@ static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } -static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int alpha_pll_huayra_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { + struct clk_hw *parent_hw; + unsigned long rrate, prate; u32 l, a; - return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); + parent_hw = clk_hw_get_parent(hw); + if (!parent_hw) + return -EINVAL; + + prate = clk_hw_get_rate(parent_hw); + rrate = alpha_huayra_pll_round_rate(req->rate, prate, &l, &a); + + req->best_parent_hw = parent_hw; + req->best_parent_rate = prate; + req->rate = rrate; + + return 0; } static int trion_pll_is_enabled(struct clk_alpha_pll *pll, @@ -946,7 +959,7 @@ const struct clk_ops clk_alpha_pll_huayra_ops = { .disable = clk_alpha_pll_disable, .is_enabled = clk_alpha_pll_is_enabled, .recalc_rate = alpha_pll_huayra_recalc_rate, - .round_rate = alpha_pll_huayra_round_rate, + .determine_rate = alpha_pll_huayra_determine_rate, .set_rate = alpha_pll_huayra_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);