From patchwork Tue Feb 1 11:47:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 539232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 978EAC433EF for ; Tue, 1 Feb 2022 11:48:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237445AbiBALsf (ORCPT ); Tue, 1 Feb 2022 06:48:35 -0500 Received: from smtp-relay-internal-1.canonical.com ([185.125.188.123]:56534 "EHLO smtp-relay-internal-1.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237435AbiBALse (ORCPT ); Tue, 1 Feb 2022 06:48:34 -0500 Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id 898363F07D for ; Tue, 1 Feb 2022 11:48:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1643716107; bh=nPtCkUJvHAiFdwR1aBTRoo7Q3YDQ+MsjF9AD3ZrXCWg=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=D0bczYAuWAw1+eGM69EHL8c2ne/EucAg1YT6+HoQ0bHbTUJ7w1c1Yc0lnjiFqgrhJ jOR9ieokpCME/+Y9xS2F/NYg7rbbPbYR1/MSNgV415xtjmJ4vQK+29L/Pr2g23IEcd YOVKmY7cF3phywJjAsQobcPwD4pwO9JJaifF37Lx1qRl9fjr97mG9Eic8sYEF6tIHy c8qWgoeSf9ZKapzaoew9zZtB4LYIEt+6O6s9s+bWEZn4rRPHJUKLol104+P5RcA4IR te1qH5je0kQKLzzXAJg+9cNfP9c7rA82p9ShBxRQNybdez6jnekrOTKZdNzc/kwabu MIrOHqyoYiSSQ== Received: by mail-ed1-f70.google.com with SMTP id l16-20020aa7c3d0000000b004070ea10e7fso8496744edr.3 for ; Tue, 01 Feb 2022 03:48:27 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=nPtCkUJvHAiFdwR1aBTRoo7Q3YDQ+MsjF9AD3ZrXCWg=; b=E6ML5Wct5pp/LizwGx84fJGQJ+mQubnHZ0LLIKrHtdalYxfili7qX71LGoU8gI+jua Zl4EttaoPIm3ydQVJN3YhSG20n0XUzUt/f8ojV9Z0IK8/W4H0IiZF/0KjQt1DhKxY15M /ex/MdSlMlKxYMDP0rrtBo0F0vvfRr3kzF5bOhNOhM664YRe1/I3UewbgY+3wAJnp280 zkMaABiSWht6lrRWh/1vZN6y+R4xeiY4c8wR+65g5huXQHUaGjCsfEF6GoI7LNsxAmuG F48c6E5qR8+UEzlPhZs+TtACi5nfZxOHWcOmp/D1Kavy2r6pdBm+ptFn5KRU5vFjwp0R YQBA== X-Gm-Message-State: AOAM532itQBKwBTa5IQ7CaYc4l4eP08DCJ9ya4Gk+C3eh9ujyvv2H+wX 8RXnZqSSjWMKSCFopcXUrjAWBjnAIG116iwqVush944dpIx41JEghHCi+9xW7pkMWGVv/AymXzl jtojpa6aygwM/bFzX2RQvvnZZFSOkiUpd6SvWu3sF9C5mqJXf X-Received: by 2002:a17:907:8a24:: with SMTP id sc36mr20350990ejc.318.1643716107287; Tue, 01 Feb 2022 03:48:27 -0800 (PST) X-Google-Smtp-Source: ABdhPJzSB+mTN/eqKVxteQU8ZJe5VpQaVxci/PoYo5bHi9rsjmr1K5CgtZb6C+DyJSPH0xcLZmI3cQ== X-Received: by 2002:a17:907:8a24:: with SMTP id sc36mr20350984ejc.318.1643716107068; Tue, 01 Feb 2022 03:48:27 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id bo19sm17954484edb.56.2022.02.01.03.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 03:48:26 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 1/6] arm64: dts: exynos: use generic node name for LPDDR3 timings Date: Tue, 1 Feb 2022 12:47:44 +0100 Message-Id: <20220201114749.88500-1-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The node names should have generic name, so use "timings" for LPDDR3 timings. This will also be required by dtschema. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 24c428b84192..2f65dcf6ba73 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -358,7 +358,7 @@ samsung_K3QF2F20DB: lpddr3 { tCKESR-min-tck = <2>; tMRD-min-tck = <5>; - timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + timings_samsung_K3QF2F20DB_800mhz: timings@800000000 { compatible = "jedec,lpddr3-timings"; /* workaround: 'reg' shows max-freq */ reg = <800000000>; From patchwork Tue Feb 1 11:47:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 539231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4B7BC43217 for ; Tue, 1 Feb 2022 11:48:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237468AbiBALsf (ORCPT ); Tue, 1 Feb 2022 06:48:35 -0500 Received: from smtp-relay-internal-0.canonical.com ([185.125.188.122]:38432 "EHLO smtp-relay-internal-0.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237427AbiBALse (ORCPT ); Tue, 1 Feb 2022 06:48:34 -0500 Received: from mail-ej1-f70.google.com (mail-ej1-f70.google.com [209.85.218.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id 3D2E53F4B4 for ; Tue, 1 Feb 2022 11:48:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1643716112; bh=wQ7LXiPof6IMw8aL2q+JYN7M9eGDaZpG8RUm/afPGLI=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sgcRv88GQ+UHY/hpCCEmyqNgzzR2Vwnd/BPQh81Xa9GT7jx1XjDAR5L126VBaQaK6 gwXc04+tUKEatcfJS7JU9+1jlMUJzdEPvCg7hHDZn37Ewaaj1mArzVJoScYDRNDQXK O5KIyZ25y1jgRe+6A0mw9PZwedgrwVM7kiwS6by+ZClS5HqtEarZji+1tcoiH0RF5s EBiNc20FSmd3FX88Tu3f8OwkFFUAsj0es0A243+lz9rXTTfhra6bwvKHcDdn14w+lN v1IgqVZvUmipbN0rmAxyLeDdTbbPVgy+GRZ8CFjQUGHC48OpMbJc053kH+75ie4cz/ egTGrbb+rU6zQ== Received: by mail-ej1-f70.google.com with SMTP id x16-20020a170906135000b006b5b4787023so6452785ejb.12 for ; Tue, 01 Feb 2022 03:48:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wQ7LXiPof6IMw8aL2q+JYN7M9eGDaZpG8RUm/afPGLI=; b=dfYaVOC6bfav92Eu5/WMFAH+HvbSKFfQ42xpfEz+M+1abvYs2oger5Dq6EogDrr9Ev USRVq9O3TXdE9V0SDCD94BhX5Vw1cd0qnw/GQIUyaY8Gajy7VUYsRw2LLDF25LkDTSLO +hglMv0v8Gl5cSFK00mw0HuLr2Ndq67eA67fJs1wLNG3dwGG4OG/rO9V8mYpOG413mqq evMUIsDD9dfgnHuKXH1L4iOL24aYIaZOr/X1dz7gxyDynjzuwav22Kvm7CjmHTSCpH25 QPYguFtW0rzCfylgVJWzH8d3JsWBCpqd0eQ06gQ+CjDrMqpNURnb4sVYcsEHEcbqsmkQ iQxQ== X-Gm-Message-State: AOAM532X1fJ7qO0THW/2oRu2bujt+K2svVDlP354VZ4fQW+GFXdaLtTU a25ve7WvkQf1JO2uj34BRq5U28uc0lGHu7OZLy7FiRGsWddL7VTN1Ccr4JSi/b1VfZxpixrmbRp XeVVKBYGrifKwloUfBBwCNd20P3/gYrBav1u4tft5ZfScvmMS X-Received: by 2002:aa7:d1d4:: with SMTP id g20mr24934224edp.296.1643716108456; Tue, 01 Feb 2022 03:48:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJz3KvejSRP8XZF4mm33Vo+og/yd0Iu/L/N3KWBXvK3ZpTdVbOdRwR97tU2Yb/X7gw3TbKUbHw== X-Received: by 2002:aa7:d1d4:: with SMTP id g20mr24934210edp.296.1643716108233; Tue, 01 Feb 2022 03:48:28 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id bo19sm17954484edb.56.2022.02.01.03.48.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 03:48:27 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 2/6] dt-bindings: memory: lpddr3: convert to dtschema Date: Tue, 1 Feb 2022 12:47:45 +0100 Message-Id: <20220201114749.88500-2-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220201114749.88500-1-krzysztof.kozlowski@canonical.com> References: <20220201114749.88500-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Convert the LPDDR3 memory bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski --- .../memory-controllers/ddr/jedec,lpddr3.yaml | 266 ++++++++++++++++++ .../memory-controllers/ddr/lpddr3.txt | 107 ------- 2 files changed, 266 insertions(+), 107 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml new file mode 100644 index 000000000000..c8577186324a --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -0,0 +1,266 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR3 SDRAM compliant to JEDEC JESD209-3 + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + items: + - enum: + - samsung,K3QF2F20DB + - const: jedec,lpddr3 + + '#address-cells': + const: 1 + + density: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Density in megabits of SDRAM chip. + enum: + - 4096 + - 8192 + - 16384 + - 32768 + + io-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + IO bus width in bits of SDRAM chip. + enum: + - 64 + - 32 + - 16 + - 8 + + manufacturer-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Manufacturer ID value read from Mode Register 5. + + revision-id: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + items: + maximum: 255 + description: | + Revision value of SDRAM chip read from Mode Registers 6 and 7. + + '#size-cells': + const: 0 + + tCKE-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + CKE minimum pulse width (HIGH and LOW pulse width) in terms of number + of clock cycles. + + tCKESR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in terms of number of clock cycles. + + tDQSCK-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + DQS output data access time from CK_t/CK_c in terms of number of clock + cycles. + + tFAW-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 63 + description: | + Four-bank activate window in terms of number of clock cycles. + + tMRD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Mode register set command delay in terms of number of clock cycles. + + tR2R-C2C-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + Additional READ-to-READ delay in chip-to-chip cases in terms of number + of clock cycles. + + tRAS-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 63 + description: | + Row active time in terms of number of clock cycles. + + tRC-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 63 + description: | + ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles. + + tRCD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + RAS-to-CAS delay in terms of number of clock cycles. + + tRFC-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 255 + description: | + Refresh Cycle time in terms of number of clock cycles. + + tRL-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + READ data latency in terms of number of clock cycles. + + tRPab-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Row precharge time (all banks) in terms of number of clock cycles. + + tRPpb-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Row precharge time (single banks) in terms of number of clock cycles. + + tRRD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Active bank A to active bank B in terms of number of clock cycles. + + tRTP-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Internal READ to PRECHARGE command delay in terms of number of clock + cycles. + + tW2W-C2C-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number + of clock cycles. + + tWL-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + WRITE data latency in terms of number of clock cycles. + + tWR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + WRITE recovery time in terms of number of clock cycles. + + tWTR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Internal WRITE-to-READ command delay in terms of number of clock cycles. + + tXP-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 255 + description: | + Exit power-down to next valid command delay in terms of number of clock + cycles. + + tXSR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 1023 + description: | + SELF REFRESH exit to next valid command delay in terms of number of clock + cycles. + +patternProperties: + "^timings@[0-9a-f]+$": + type: object + description: | + The lpddr3 node may have one or more child nodes with timings. + Each timing node provides AC timing parameters of the device for a given + speed-bin. The user may provide the timings for as many speed-bins as is + required. For more information please see:: + Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt + +required: + - compatible + - '#address-cells' + - density + - io-width + - '#size-cells' + +additionalProperties: false + +examples: + - | + lpddr3 { + compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tDQSCK-min-tck = <5>; + tFAW-min-tck = <5>; + tMRD-min-tck = <5>; + tR2R-C2C-min-tck = <0>; + tRAS-min-tck = <5>; + tRC-min-tck = <6>; + tRCD-min-tck = <3>; + tRFC-min-tck = <17>; + tRL-min-tck = <14>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRRD-min-tck = <2>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tWR-min-tck = <7>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tXSR-min-tck = <12>; + + timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; + min-freq = <100000000>; + tCKE = <3750>; + tCKESR = <3750>; + tFAW = <25000>; + tMRD = <7000>; + tR2R-C2C = <0>; + tRAS = <23000>; + tRC = <33750>; + tRCD = <10000>; + tRFC = <65000>; + tRPab = <12000>; + tRPpb = <12000>; + tRRD = <6000>; + tRTP = <3750>; + tW2W-C2C = <0>; + tWR = <7500>; + tWTR = <3750>; + tXP = <3750>; + tXSR = <70000>; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt deleted file mode 100644 index 031af5fb0379..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt +++ /dev/null @@ -1,107 +0,0 @@ -* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C - -Required properties: -- compatible : Should be ",", and generic value "jedec,lpddr3". - Example "," values: - "samsung,K3QF2F20DB" - -- density : representing density in Mb (Mega bits) -- io-width : representing bus width. Possible values are 8, 16, 32, 64 -- #address-cells: Must be set to 1 -- #size-cells: Must be set to 0 - -Optional properties: - -- manufacturer-id : Manufacturer ID value read from Mode Register 5 -- revision-id : Revision IDs read from Mode Registers 6 and 7 - -The following optional properties represent the minimum value of some AC -timing parameters of the DDR device in terms of number of clock cycles. -These values shall be obtained from the device data-sheet. -- tRFC-min-tck -- tRRD-min-tck -- tRPab-min-tck -- tRPpb-min-tck -- tRCD-min-tck -- tRC-min-tck -- tRAS-min-tck -- tWTR-min-tck -- tWR-min-tck -- tRTP-min-tck -- tW2W-C2C-min-tck -- tR2R-C2C-min-tck -- tWL-min-tck -- tDQSCK-min-tck -- tRL-min-tck -- tFAW-min-tck -- tXSR-min-tck -- tXP-min-tck -- tCKE-min-tck -- tCKESR-min-tck -- tMRD-min-tck - -Child nodes: -- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". - "lpddr3-timings" provides AC timing parameters of the device for - a given speed-bin. Please see - Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt - for more information on "lpddr3-timings" - -Example: - -samsung_K3QF2F20DB: lpddr3 { - compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; - density = <16384>; - io-width = <32>; - manufacturer-id = <1>; - revision-id = <123 234>; - #address-cells = <1>; - #size-cells = <0>; - - tRFC-min-tck = <17>; - tRRD-min-tck = <2>; - tRPab-min-tck = <2>; - tRPpb-min-tck = <2>; - tRCD-min-tck = <3>; - tRC-min-tck = <6>; - tRAS-min-tck = <5>; - tWTR-min-tck = <2>; - tWR-min-tck = <7>; - tRTP-min-tck = <2>; - tW2W-C2C-min-tck = <0>; - tR2R-C2C-min-tck = <0>; - tWL-min-tck = <8>; - tDQSCK-min-tck = <5>; - tRL-min-tck = <14>; - tFAW-min-tck = <5>; - tXSR-min-tck = <12>; - tXP-min-tck = <2>; - tCKE-min-tck = <2>; - tCKESR-min-tck = <2>; - tMRD-min-tck = <5>; - - timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { - compatible = "jedec,lpddr3-timings"; - /* workaround: 'reg' shows max-freq */ - reg = <800000000>; - min-freq = <100000000>; - tRFC = <65000>; - tRRD = <6000>; - tRPab = <12000>; - tRPpb = <12000>; - tRCD = <10000>; - tRC = <33750>; - tRAS = <23000>; - tWTR = <3750>; - tWR = <7500>; - tRTP = <3750>; - tW2W-C2C = <0>; - tR2R-C2C = <0>; - tFAW = <25000>; - tXSR = <70000>; - tXP = <3750>; - tCKE = <3750>; - tCKESR = <3750>; - tMRD = <7000>; - }; -} From patchwork Tue Feb 1 11:47:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 539525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5815C433F5 for ; Tue, 1 Feb 2022 11:48:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237452AbiBALsf (ORCPT ); Tue, 1 Feb 2022 06:48:35 -0500 Received: from smtp-relay-internal-0.canonical.com ([185.125.188.122]:38438 "EHLO smtp-relay-internal-0.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237444AbiBALse (ORCPT ); Tue, 1 Feb 2022 06:48:34 -0500 Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id AE67C3FFDA for ; Tue, 1 Feb 2022 11:48:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1643716112; bh=o1EGYrWsRqx/bd/p11jiwzAPNZIWt1CcXa2YB+SDcqU=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SWSrXVTQq0L6ixpRvgggDNLQXCpJvj0wMDBjexJAF1yGWDPMCxPAa8EZ0EjczDRy5 d07Y9d794sbqTCo2xpDGbx883TUyzY7Uji7ur3MykbmsUz5il5L0vhSHBLA/dSe3Ud 3eFpjLI/xAC2L36NF3qFlkUcg7vM8fxKXeCBjkanK4U7HChR8n9LJLvfanBP3zQb1R /IgM+2A88dVkO58KTMI7CRhE8ZwrRUjj+L7pE8izUfrH5HibUsgVI6+JQTwjh29cNj mEUZ5NQXKjsBV0LcrprAN2sFSprAw33N9Oh+5lyhJV2XN3v9FN/ZQ6tWi42Lz8OqzV YakTx4ToEN1KQ== Received: by mail-ed1-f69.google.com with SMTP id w23-20020a50d797000000b00406d33c039dso8550145edi.11 for ; Tue, 01 Feb 2022 03:48:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o1EGYrWsRqx/bd/p11jiwzAPNZIWt1CcXa2YB+SDcqU=; b=jZxWdJUlQ505a2LrvCvFbMZ22P9IHMjDbIEtybh+tMrOcOn3VH6E/087D1XXJ4cg7m KOM6o/jII5+xdtXLG5Hqsstb70oq11snvXhV1WW7+1D9V6kUc2hP28r38XUkx/SHLEI2 fkL1ufizI2b4/ichJ5/LSlSbLbM/WxEUeU55qEywmz+Zzw0nLpoRJktOdoyIuBBc8WuP Ux4op58b3EhKjX3ssNweR9hyXh/l8Qrlxo8ESMdlgdzN7nJRtLPwtnHAkMe7K6q7ABsY B7lFfIrw5taFaFTnhN6mB4iOvH3sVkJTUZ5ureZk76iC5X2v0uVbqqvhDM+r9HFv1+Rl Mucg== X-Gm-Message-State: AOAM531sD2XQ7TD1qqy2BOq0vUQyeAuqoalHSPqUZu6pEpOiCLL70eno QtT7ptbKhnR5oUE1Gg1ehEsaguyMhEWo12k6SX6haU5q1UwoHuvcmJ4XosfHYNQVQDzc4LLU3Nt KBSnRHIzZgACQdGarw2KfahwV094DFwNwAWKT++oKWPhaCjs/ X-Received: by 2002:a05:6402:c8f:: with SMTP id cm15mr11990023edb.142.1643716109126; Tue, 01 Feb 2022 03:48:29 -0800 (PST) X-Google-Smtp-Source: ABdhPJwraRAjhC9I6DY9xAnWWXt1339RlIYhSluQ5JrwhO0g6NxEHo1NIp7ivDOtxHqLqCBE3vpCHQ== X-Received: by 2002:a05:6402:c8f:: with SMTP id cm15mr11990002edb.142.1643716108971; Tue, 01 Feb 2022 03:48:28 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id bo19sm17954484edb.56.2022.02.01.03.48.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 03:48:28 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 3/6] dt-bindings: memory: lpddr3: adjust IO width to spec Date: Tue, 1 Feb 2022 12:47:46 +0100 Message-Id: <20220201114749.88500-3-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220201114749.88500-1-krzysztof.kozlowski@canonical.com> References: <20220201114749.88500-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org According to JEDEC Standard No. 209-3 (table 3.4.1 "Mode Register Assignment and Definition in LPDDR3 SDRAM"), the LPDDR3 supports only 16- and 32-bit IO width. Drop the unsupported others. Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/ddr/jedec,lpddr3.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml index c8577186324a..0c8353c11767 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -34,10 +34,8 @@ properties: description: | IO bus width in bits of SDRAM chip. enum: - - 64 - 32 - 16 - - 8 manufacturer-id: $ref: /schemas/types.yaml#/definitions/uint32 From patchwork Tue Feb 1 11:47:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 539524 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60065C433FE for ; Tue, 1 Feb 2022 11:48:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237471AbiBALsg (ORCPT ); Tue, 1 Feb 2022 06:48:36 -0500 Received: from smtp-relay-internal-0.canonical.com ([185.125.188.122]:38462 "EHLO smtp-relay-internal-0.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237440AbiBALsf (ORCPT ); Tue, 1 Feb 2022 06:48:35 -0500 Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id 9D3793FFE6 for ; Tue, 1 Feb 2022 11:48:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1643716113; bh=OuVWT+OxqE323DEVUlu5DyHs7hHuGTLMdHDm6pwqNSI=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nzVHKUorVmzrzrOWORGOGRsP13Hq6vhGLEUpnmMW4vC6mjOvKsf+jSP3UPITkE7Xp QvHd1IGyMazWoMjxNmwNoJSo/hLN9AiYY0GworzslCi6zDbkrXomGZ+rk4TJIooB5T U5lRkhO9RoFrHo3wkUFS5ZNUVZ0DI1IvV5m20a3Z6Jf7iiTlMyd8o88QPIQvmK6K1F nuAFEDJKa5WRqzWr7y8E8WpAP8GH1gERk28hPHiWyzDlP7+0193tYOr7wlg7cuYDCx /+JprZueX4IRQsXU/KDgFukiZzFvCHmCPawouuyTssuytwF7ujrGKUC4SHeWfF2lhM T38Vua+aDyBJA== Received: by mail-ed1-f69.google.com with SMTP id o25-20020a056402039900b0040631c2a67dso8469428edv.19 for ; Tue, 01 Feb 2022 03:48:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OuVWT+OxqE323DEVUlu5DyHs7hHuGTLMdHDm6pwqNSI=; b=abcqHQTmohVEeq5Kl2uzyaLDiBoKTiH0/Eh/q3/X/bhClrjpZYH/GOBemql1aydDfb UnES/31l/ZuGOcT5tkr9IEBAxqzwCLaxsBKKTLScGQnIXexboVcWCuOBP2iU5HS86YYV KHVopZ69WIlwjr9+d19DL9E5Qx1EjCaYaN6Uu9UwZSwlfdFIa1Qjtc4VvvZwgjciZKOx NYxE4peToXrn2DM5paVxWXUTbrXU+YUNB35522deKmVKM5XTNuReaZiaGHbLqfGcooBJ bVONfpovPHnrC/eYWpTz9nOH6pqOFGKGbJ/vB5x433msjWMXZW3zQ4kSWu7CDc2+WQUv 7xmA== X-Gm-Message-State: AOAM530eQkNJpB1U3c94YGIxT5ACo/isIGX1vlnK+dXNCvbgpK7gTDER SIh5dS9ZnOXo4c15GGjaR/FDJJtWddA7xIJ3z/5VGgyFyAh8CgMJmP2FmUckc7RQbvJH/hPYP/S MUumLoWSqiRBcJLNoCrWfO9N60SnRmaGzaTbO83WQ1GPEiOfI X-Received: by 2002:a17:907:d9f:: with SMTP id go31mr21604851ejc.282.1643716111079; Tue, 01 Feb 2022 03:48:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJz4hxffkdEDnSRNHd8A4Uy3TqYuAKbZF4KOrK7b4i45cPu6GWoai3jbLk/RRWS+LN17FX6K9Q== X-Received: by 2002:a17:907:d9f:: with SMTP id go31mr21604841ejc.282.1643716110925; Tue, 01 Feb 2022 03:48:30 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id bo19sm17954484edb.56.2022.02.01.03.48.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 03:48:30 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 4/6] dt-bindings: memory: lpddr3: deprecated manufacturer ID Date: Tue, 1 Feb 2022 12:47:47 +0100 Message-Id: <20220201114749.88500-4-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220201114749.88500-1-krzysztof.kozlowski@canonical.com> References: <20220201114749.88500-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The memory manufacturer should be described in vendor part of compatible, so there is no need to duplicate it in separate property. Similarly is done in LPDDR2 bindings. Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/ddr/jedec,lpddr3.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml index 0c8353c11767..138c57d8a375 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -40,7 +40,9 @@ properties: manufacturer-id: $ref: /schemas/types.yaml#/definitions/uint32 description: | - Manufacturer ID value read from Mode Register 5. + Manufacturer ID value read from Mode Register 5. The property is + deprecated, manufacturer should be derived from the compatible. + deprecated: true revision-id: $ref: /schemas/types.yaml#/definitions/uint32-array From patchwork Tue Feb 1 11:47:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 539230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F409EC4167D for ; Tue, 1 Feb 2022 11:48:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237483AbiBALsh (ORCPT ); Tue, 1 Feb 2022 06:48:37 -0500 Received: from smtp-relay-internal-1.canonical.com ([185.125.188.123]:56568 "EHLO smtp-relay-internal-1.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237442AbiBALsg (ORCPT ); Tue, 1 Feb 2022 06:48:36 -0500 Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id B3A4F3F1BE for ; Tue, 1 Feb 2022 11:48:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1643716115; bh=WADk9zGuYiMHMUgeqEWKXcx1LnePmBdOwPQaJwQS8DQ=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BXGAEKKZky1gvaZ2uUab9T9F+Uvi6gdSHiJBzMgvznK4mkFl/kx9YwIL1p5g1JO3u J+vmwug73mOFk4glAEwv2m31EM1pxzf/cC8loJLrl9TbhTv2JowPOHwV9MpWz8oCFK N9BvpJySDS/CO7Xx8B7E/QDo0ii8QvUCbYETGBQ7FrC3uxuBiPAtD9beoNGOkxjPAy detQK9IubDgnrvuv6lZA6d6LOzMfjk34Q9eXKOwcm9zPSzHlwwMvYyZxBtss0wpXSa 1YKFaHacW2hrmR9/7eUicvmXXO0LCYW+5n3zV+9PnIZB9PDtz7tSC8dxSn84XzCGa8 x3V0cdcsDHDsA== Received: by mail-ed1-f72.google.com with SMTP id n7-20020a05640205c700b0040b7be76147so4044963edx.10 for ; Tue, 01 Feb 2022 03:48:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WADk9zGuYiMHMUgeqEWKXcx1LnePmBdOwPQaJwQS8DQ=; b=ysP6qMMR6JHyuAHXAGu87LEjKcD0DODKO6l113PgeWv9IUxgtWXQz7PNCFyeNmHcZ5 wpCYNuitz1gLYEdkrNfNNR0df6u7Nx2PdSm2p1UVd9GRuMuF8CcMWs2fbcax8/dkQbQr pJ8365FXTGuXMtDN/DwggyIftuUP5KKLzjhOkVUuRDAn04cYLvQHgTaYr4TqtZJYs6cm c1PJKnD0KkRAn9ZCB5TPFPuxQd50Gjc93lcmFgfr7r8aR95pc4UKMYijESfUIovo+JFe NfWqm1hw86Sm+k1PxSWG0dYemoFWLfAbTkVcoyS91VtZvJo5VI4lTNfh5084bve8gYeK hAKw== X-Gm-Message-State: AOAM531XZ085wLGx3HPbxWnsOMYlJwl01nIjLNv+X7jUajtGTgzXp13X 2Xrc/Msd2yKAkidI2ZBO6bCYzHVcMF4QoAN7B8T+JN+7MdDkgmAJBAIiLG9z0NxPG3Wd7A2D17i Q11dHvsfI/3w3nY5lXkHrU1jwa/STLTbg64bdiFSpVq5z50D1 X-Received: by 2002:a17:906:31cc:: with SMTP id f12mr20180711ejf.115.1643716113277; Tue, 01 Feb 2022 03:48:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJzritvK1s6ruWejqqATTfAiWNIFOFiUVuabJlDk6yiD80KSJT2X8p45M7wsQIgsuFwujL1ONQ== X-Received: by 2002:a17:906:31cc:: with SMTP id f12mr20180702ejf.115.1643716113054; Tue, 01 Feb 2022 03:48:33 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id bo19sm17954484edb.56.2022.02.01.03.48.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 03:48:32 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 5/6] dt-bindings: memory: lpddr3-timings: convert to dtschema Date: Tue, 1 Feb 2022 12:47:48 +0100 Message-Id: <20220201114749.88500-5-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220201114749.88500-1-krzysztof.kozlowski@canonical.com> References: <20220201114749.88500-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Convert the LPDDR3 memory timings bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski --- .../ddr/jedec,lpddr3-timings.yaml | 153 ++++++++++++++++++ .../memory-controllers/ddr/jedec,lpddr3.yaml | 5 +- .../memory-controllers/ddr/lpddr3-timings.txt | 58 ------- 3 files changed, 155 insertions(+), 61 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml new file mode 100644 index 000000000000..98bc219e8a25 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR3 SDRAM AC timing parameters for a given speed-bin + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + const: jedec,lpddr3-timings + + reg: + maxItems: 1 + description: | + Maximum DDR clock frequency for the speed-bin, in Hz. + + min-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Minimum DDR clock frequency for the speed-bin, in Hz. + + tCKE: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds. + + tCKESR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in pico seconds. + + tFAW: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Four-bank activate window in pico seconds. + + tMRD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Mode register set command delay in pico seconds. + + tR2R-C2C: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Additional READ-to-READ delay in chip-to-chip cases in pico seconds. + + tRAS: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row active time in pico seconds. + + tRC: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + ACTIVATE-to-ACTIVATE command period in pico seconds. + + tRCD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + RAS-to-CAS delay in pico seconds. + + tRFC: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Refresh Cycle time in pico seconds. + + tRPab: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row precharge time (all banks) in pico seconds. + + tRPpb: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row precharge time (single banks) in pico seconds. + + tRRD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Active bank A to active bank B in pico seconds. + + tRTP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal READ to PRECHARGE command delay in pico seconds. + + tW2W-C2C: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds. + + tWR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WRITE recovery time in pico seconds. + + tWTR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal WRITE-to-READ command delay in pico seconds. + + tXP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Exit power-down to next valid command delay in pico seconds. + + tXSR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SELF REFRESH exit to next valid command delay in pico seconds. + +required: + - compatible + - min-freq + - reg + +additionalProperties: false + +examples: + - | + lpddr3 { + #address-cells = <1>; + #size-cells = <0>; + + timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; + min-freq = <100000000>; + tCKE = <3750>; + tCKESR = <3750>; + tFAW = <25000>; + tMRD = <7000>; + tR2R-C2C = <0>; + tRAS = <23000>; + tRC = <33750>; + tRCD = <10000>; + tRFC = <65000>; + tRPab = <12000>; + tRPpb = <12000>; + tRRD = <6000>; + tRTP = <3750>; + tW2W-C2C = <0>; + tWR = <7500>; + tWTR = <3750>; + tXP = <3750>; + tXSR = <70000>; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml index 138c57d8a375..3bcba15098ea 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -192,13 +192,12 @@ properties: patternProperties: "^timings@[0-9a-f]+$": - type: object + $ref: jedec,lpddr3-timings.yaml description: | The lpddr3 node may have one or more child nodes with timings. Each timing node provides AC timing parameters of the device for a given speed-bin. The user may provide the timings for as many speed-bins as is - required. For more information please see:: - Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt + required. required: - compatible diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt deleted file mode 100644 index 84705e50a3fd..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt +++ /dev/null @@ -1,58 +0,0 @@ -* AC timing parameters of LPDDR3 memories for a given speed-bin. - -The structures are based on LPDDR2 and extended where needed. - -Required properties: -- compatible : Should be "jedec,lpddr3-timings" -- min-freq : minimum DDR clock frequency for the speed-bin. Type is -- reg : maximum DDR clock frequency for the speed-bin. Type is - -Optional properties: - -The following properties represent AC timing parameters from the memory -data-sheet of the device for a given speed-bin. All these properties are -of type and the default unit is ps (pico seconds). -- tRFC -- tRRD -- tRPab -- tRPpb -- tRCD -- tRC -- tRAS -- tWTR -- tWR -- tRTP -- tW2W-C2C -- tR2R-C2C -- tFAW -- tXSR -- tXP -- tCKE -- tCKESR -- tMRD - -Example: - -timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { - compatible = "jedec,lpddr3-timings"; - reg = <800000000>; /* workaround: it shows max-freq */ - min-freq = <100000000>; - tRFC = <65000>; - tRRD = <6000>; - tRPab = <12000>; - tRPpb = <12000>; - tRCD = <10000>; - tRC = <33750>; - tRAS = <23000>; - tWTR = <3750>; - tWR = <7500>; - tRTP = <3750>; - tW2W-C2C = <0>; - tR2R-C2C = <0>; - tFAW = <25000>; - tXSR = <70000>; - tXP = <3750>; - tCKE = <3750>; - tCKESR = <3750>; - tMRD = <7000>; -}; From patchwork Tue Feb 1 11:47:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 539523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83569C433EF for ; Tue, 1 Feb 2022 11:48:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237438AbiBALsu (ORCPT ); Tue, 1 Feb 2022 06:48:50 -0500 Received: from smtp-relay-internal-1.canonical.com ([185.125.188.123]:56586 "EHLO smtp-relay-internal-1.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237501AbiBALsm (ORCPT ); Tue, 1 Feb 2022 06:48:42 -0500 Received: from mail-ej1-f70.google.com (mail-ej1-f70.google.com [209.85.218.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id 2F26E3F1FD for ; Tue, 1 Feb 2022 11:48:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1643716121; bh=T/Y7vvIm1vNgiOBuzuvlSLr7bPQM9EpmEANjJNIACK4=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Z60CuZRe3aW5oKVPq2Boh5+sHlY24lbKP+WpPvat3pplGHGTr5BMtczJKd2UBtJ0e wwby7ShWITzZM7NhKL1LWqfCWXdduIm2U3962qsabwtL1ZK83V9yh1bzBhtANf2gNo yy0F3Vt/29I/73sZaBiuSyKRnjDXp0YwtB2b/dhN1qEv9wqXMcQ0Ofgi4/e9k0Jbpu CczuVQc1yhrjbtqofduigHzYbl346/Wlfe7arJZJVNts2uuM3yT3cZ5g/B5T0arLAT U386Kh7Ar6Vw6vb/Zt9qNcNrhftphIwnqNi1Ggfg3BFTUsXooDqknSlU+aI+WFm8+S 9p6uVengS6tbQ== Received: by mail-ej1-f70.google.com with SMTP id kw5-20020a170907770500b006ba314a753eso6408061ejc.21 for ; Tue, 01 Feb 2022 03:48:41 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T/Y7vvIm1vNgiOBuzuvlSLr7bPQM9EpmEANjJNIACK4=; b=p+FLciYTPceGHfC/Zwld4CwPlQA37qSFcSWSsEXZnYM3MOQV47sR2C2Ct6Nl8n2utW prgfzNJOKjP3iRNcXC7Af6CMTYvQpT544/8kcGB5Dgp3/0gMayMjoqRzuzleIvf0lWnu XrY0QeU818rD9yFd3IVnG4rBX2wnvrOj8YZieWnspZVHtqC6pkiS1aJxjmUawLAKh4Mg 3xEBteT32D/s5tK+aXHZ3cyDu+i4JwVa5aBGQDYGU9f9D9KKuuKs4e8CtCdET7EY7+jq 58sRqqYrVU+hf0D0UL2hje3oyuyK7vuvWMW743fsHN40ekTcNTilIYRbTqjAhQSRT1ON z71w== X-Gm-Message-State: AOAM533VQvHjIVwD9yDq+sdmQMXhd44uuMK4ro7cW+amGKdm4lv90tlI hXl7ipvR5vBoYwUh7nwHygxvhwDy65pqg5/PFKTFs6xM3DvLSQQZUnAwKHgEYWbx+vuzORG7sIn Oze8qnYBc6jZZYiDMKUVS2kjQIbtaNva8kxnsH+u+K8YkSG7u X-Received: by 2002:a17:907:7ea3:: with SMTP id qb35mr20935344ejc.553.1643716114004; Tue, 01 Feb 2022 03:48:34 -0800 (PST) X-Google-Smtp-Source: ABdhPJxBVg7XQAKdtCkCWKY7svrC9N0kglErPiZRvcZ3T1qESNacpBeH/7PKHB+m0oeeHfjiu1i0cQ== X-Received: by 2002:a17:907:7ea3:: with SMTP id qb35mr20935333ejc.553.1643716113773; Tue, 01 Feb 2022 03:48:33 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id bo19sm17954484edb.56.2022.02.01.03.48.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 03:48:33 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 6/6] dt-bindings: memory: lpddr2-timings: convert to dtschema Date: Tue, 1 Feb 2022 12:47:49 +0100 Message-Id: <20220201114749.88500-6-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220201114749.88500-1-krzysztof.kozlowski@canonical.com> References: <20220201114749.88500-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Convert the LPDDR2 memory timings bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski --- .../ddr/jedec,lpddr2-timings.yaml | 135 ++++++++++++++++++ .../memory-controllers/ddr/jedec,lpddr2.yaml | 6 +- .../memory-controllers/ddr/lpddr2-timings.txt | 52 ------- 3 files changed, 137 insertions(+), 56 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml new file mode 100644 index 000000000000..7cc3021decfe --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR2 SDRAM AC timing parameters for a given speed-bin + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + const: jedec,lpddr2-timings + + max-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Maximum DDR clock frequency for the speed-bin, in Hz. + + min-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Minimum DDR clock frequency for the speed-bin, in Hz. + + tCKESR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in pico seconds. + + tDQSCK-max: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + DQS output data access time from CK_t/CK_c in pico seconds. + + tDQSCK-max-derated: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + DQS output data access time from CK_t/CK_c, temperature de-rated, in pico + seconds. + + tFAW: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Four-bank activate window in pico seconds. + + tRAS-max-ns: + description: | + Row active time in nano seconds. + + tRAS-min: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row active time in pico seconds. + + tRCD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + RAS-to-CAS delay in pico seconds. + + tRPab: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row precharge time (all banks) in pico seconds. + + tRRD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Active bank A to active bank B in pico seconds. + + tRTP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal READ to PRECHARGE command delay in pico seconds. + + tWR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WRITE recovery time in pico seconds. + + tWTR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal WRITE-to-READ command delay in pico seconds. + + tXP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Exit power-down to next valid command delay in pico seconds. + + tZQCL: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SELF REFRESH exit to next valid command delay in pico seconds. + + tZQCS: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SELF REFRESH exit to next valid command delay in pico seconds. + + tZQinit: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SELF REFRESH exit to next valid command delay in pico seconds. + +required: + - compatible + - min-freq + - max-freq + +additionalProperties: false + +examples: + - | + timings { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tRAS-max-ns = <70000>; + tRAS-min = <42000>; + tRPab = <21000>; + tRCD = <18000>; + tRRD = <10000>; + tRTP = <7500>; + tWR = <15000>; + tWTR = <7500>; + tXP = <7500>; + tZQCL = <360000>; + tZQCS = <90000>; + tZQinit = <1000000>; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml index 25ed0266f6dd..2d8a701e2a05 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml @@ -142,14 +142,12 @@ properties: patternProperties: "^lpddr2-timings": - type: object + $ref: jedec,lpddr2-timings.yaml description: | The lpddr2 node may have one or more child nodes of type "lpddr2-timings". "lpddr2-timings" provides AC timing parameters of the device for a given speed-bin. The user may provide the timings for as many - speed-bins as is required. Please see Documentation/devicetree/ - bindings/memory-controllers/ddr/lpddr2-timings.txt for more information - on "lpddr2-timings". + speed-bins as is required. required: - compatible diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt deleted file mode 100644 index 9ceb19e0c7fd..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt +++ /dev/null @@ -1,52 +0,0 @@ -* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin - -Required properties: -- compatible : Should be "jedec,lpddr2-timings" -- min-freq : minimum DDR clock frequency for the speed-bin. Type is -- max-freq : maximum DDR clock frequency for the speed-bin. Type is - -Optional properties: - -The following properties represent AC timing parameters from the memory -data-sheet of the device for a given speed-bin. All these properties are -of type and the default unit is ps (pico seconds). Parameters with -a different unit have a suffix indicating the unit such as 'tRAS-max-ns' -- tRCD -- tWR -- tRAS-min -- tRRD -- tWTR -- tXP -- tRTP -- tDQSCK-max -- tFAW -- tZQCS -- tZQinit -- tRPab -- tZQCL -- tCKESR -- tRAS-max-ns -- tDQSCK-max-derated - -Example: - -timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <400000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; -};