From patchwork Fri Jan 28 06:28:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunfeng Yun X-Patchwork-Id: 537883 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16D7EC4332F for ; Fri, 28 Jan 2022 06:29:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346493AbiA1G3Q (ORCPT ); Fri, 28 Jan 2022 01:29:16 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:43502 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237265AbiA1G3K (ORCPT ); Fri, 28 Jan 2022 01:29:10 -0500 X-UUID: aa9056f5144e44749c19611c6fac7515-20220128 X-UUID: aa9056f5144e44749c19611c6fac7515-20220128 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1596489570; Fri, 28 Jan 2022 14:29:05 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 28 Jan 2022 14:29:04 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 28 Jan 2022 14:29:04 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 28 Jan 2022 14:29:03 +0800 From: Chunfeng Yun To: Greg Kroah-Hartman , Matthias Brugger CC: Chunfeng Yun , Rob Herring , Mathias Nyman , , , , , , Tianping Fang , Eddie Hung , AngeloGioacchino Del Regno Subject: [PATCH v2 1/4] dt-bindings: usb: mtk-xhci: add support ip-sleep for mt8195 Date: Fri, 28 Jan 2022 14:28:59 +0800 Message-ID: <20220128062902.26273-1-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org There are 4 USB controllers on MT8195, each controller's wakeup control is different, add some specific versions for them. Signed-off-by: Chunfeng Yun Acked-by: AngeloGioacchino Del Regno Acked-by: Rob Herring --- v2: 1. fix typo 'specific' suggested by Rob 2. add acked-by AngeloGioacchino --- .../devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index 11f7bacd4e2b..41efb51638d1 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -146,7 +146,11 @@ properties: 2 - used by mt2712 etc, revision 2 following IPM rule; 101 - used by mt8183, specific 1.01; 102 - used by mt8192, specific 1.02; - enum: [1, 2, 101, 102] + 103 - used by mt8195, IP0, specific 1.03; + 104 - used by mt8195, IP1, specific 1.04; + 105 - used by mt8195, IP2, specific 1.05; + 106 - used by mt8195, IP3, specific 1.06; + enum: [1, 2, 101, 102, 103, 104, 105, 106] mediatek,u3p-dis-msk: $ref: /schemas/types.yaml#/definitions/uint32 From patchwork Fri Jan 28 06:29:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunfeng Yun X-Patchwork-Id: 538208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0593C43219 for ; Fri, 28 Jan 2022 06:29:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346506AbiA1G3S (ORCPT ); Fri, 28 Jan 2022 01:29:18 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:43534 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1346488AbiA1G3L (ORCPT ); Fri, 28 Jan 2022 01:29:11 -0500 X-UUID: b5d5a2e7869b468ca7c68449549ffa59-20220128 X-UUID: b5d5a2e7869b468ca7c68449549ffa59-20220128 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1531445026; Fri, 28 Jan 2022 14:29:06 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 28 Jan 2022 14:29:05 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 28 Jan 2022 14:29:05 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 28 Jan 2022 14:29:04 +0800 From: Chunfeng Yun To: Greg Kroah-Hartman , Matthias Brugger CC: Chunfeng Yun , Rob Herring , Mathias Nyman , , , , , , Tianping Fang , Eddie Hung , AngeloGioacchino Del Regno Subject: [PATCH v2 2/4] usb: xhci-mtk: add support ip-sleep wakeup for mt8195 Date: Fri, 28 Jan 2022 14:29:00 +0800 Message-ID: <20220128062902.26273-2-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128062902.26273-1-chunfeng.yun@mediatek.com> References: <20220128062902.26273-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add support ip-sleep wakeup for mt8195, it's a specific revision for each USB controller, and not following IPM rule. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Signed-off-by: Chunfeng Yun --- v2: add reviewed-by Matthias & AngeloGioacchino --- drivers/usb/host/xhci-mtk.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c index 91738af0ab14..96a0ff0bb11e 100644 --- a/drivers/usb/host/xhci-mtk.c +++ b/drivers/usb/host/xhci-mtk.c @@ -95,6 +95,19 @@ #define WC0_SSUSB0_CDEN BIT(6) #define WC0_IS_SPM_EN BIT(1) +/* mt8195 */ +#define PERI_WK_CTRL0_8195 0x04 +#define WC0_IS_P_95 BIT(30) /* polarity */ +#define WC0_IS_C_95(x) ((u32)(((x) & 0x7) << 27)) +#define WC0_IS_EN_P3_95 BIT(26) +#define WC0_IS_EN_P2_95 BIT(25) +#define WC0_IS_EN_P1_95 BIT(24) + +#define PERI_WK_CTRL1_8195 0x20 +#define WC1_IS_C_95(x) ((u32)(((x) & 0xf) << 28)) +#define WC1_IS_P_95 BIT(12) +#define WC1_IS_EN_P0_95 BIT(6) + /* mt2712 etc */ #define PERI_SSUSB_SPM_CTRL 0x0 #define SSC_IP_SLEEP_EN BIT(4) @@ -105,6 +118,10 @@ enum ssusb_uwk_vers { SSUSB_UWK_V2, SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */ SSUSB_UWK_V1_2, /* specific revision 1.2 */ + SSUSB_UWK_V1_3, /* mt8195 IP0 */ + SSUSB_UWK_V1_4, /* mt8195 IP1 */ + SSUSB_UWK_V1_5, /* mt8195 IP2 */ + SSUSB_UWK_V1_6, /* mt8195 IP3 */ }; /* @@ -308,6 +325,26 @@ static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable) msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN; val = enable ? msk : 0; break; + case SSUSB_UWK_V1_3: + reg = mtk->uwk_reg_base + PERI_WK_CTRL1_8195; + msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95; + val = enable ? (WC1_IS_EN_P0_95 | WC1_IS_C_95(0x1)) : 0; + break; + case SSUSB_UWK_V1_4: + reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195; + msk = WC0_IS_EN_P1_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95; + val = enable ? (WC0_IS_EN_P1_95 | WC0_IS_C_95(0x1)) : 0; + break; + case SSUSB_UWK_V1_5: + reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195; + msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95; + val = enable ? (WC0_IS_EN_P2_95 | WC0_IS_C_95(0x1)) : 0; + break; + case SSUSB_UWK_V1_6: + reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195; + msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95; + val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0; + break; case SSUSB_UWK_V2: reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL; msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN; From patchwork Fri Jan 28 06:29:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunfeng Yun X-Patchwork-Id: 538209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8BA5C433EF for ; Fri, 28 Jan 2022 06:29:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346499AbiA1G3O (ORCPT ); Fri, 28 Jan 2022 01:29:14 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:43470 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S242393AbiA1G3K (ORCPT ); Fri, 28 Jan 2022 01:29:10 -0500 X-UUID: b02262b5534f4d32b9529e3dc2dc5059-20220128 X-UUID: b02262b5534f4d32b9529e3dc2dc5059-20220128 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 946290845; Fri, 28 Jan 2022 14:29:07 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 28 Jan 2022 14:29:05 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 28 Jan 2022 14:29:05 +0800 From: Chunfeng Yun To: Greg Kroah-Hartman , Matthias Brugger CC: Chunfeng Yun , Rob Herring , Mathias Nyman , , , , , , Tianping Fang , Eddie Hung Subject: [PATCH v2 3/4] arm64: dts: mediatek: mt8195: add efuse node and cells Date: Fri, 28 Jan 2022 14:29:01 +0800 Message-ID: <20220128062902.26273-3-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128062902.26273-1-chunfeng.yun@mediatek.com> References: <20220128062902.26273-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add efuse node and cells used by t-phy to fix the bit shift issue Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Tested-by: Macpaul Lin --- v2: use hw auto load for u2phy which has no this issue Note: depend on the reviewing patch: [v9,3/3] arm64: dts: Add mediatek SoC mt8195 and evaluation board https://patchwork.kernel.org/patch/12711296 --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 55 ++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index a363e82f6988..240a21708806 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -695,6 +695,53 @@ status = "disabled"; }; + efuse: efuse@11c10000 { + compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; + reg = <0 0x11c10000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + u3_tx_imp_p0: usb3-tx-imp@184 { + reg = <0x184 0x1>; + bits = <0 5>; + }; + u3_rx_imp_p0: usb3-rx-imp@184 { + reg = <0x184 0x2>; + bits = <5 5>; + }; + u3_intr_p0: usb3-intr@185 { + reg = <0x185 0x1>; + bits = <2 6>; + }; + comb_tx_imp_p1: usb3-tx-imp@186 { + reg = <0x186 0x1>; + bits = <0 5>; + }; + comb_rx_imp_p1: usb3-rx-imp@186 { + reg = <0x186 0x2>; + bits = <5 5>; + }; + comb_intr_p1: usb3-intr@187 { + reg = <0x187 0x1>; + bits = <2 6>; + }; + u2_intr_p0: usb2-intr-p0@188 { + reg = <0x188 0x1>; + bits = <0 5>; + }; + u2_intr_p1: usb2-intr-p1@188 { + reg = <0x188 0x2>; + bits = <5 5>; + }; + u2_intr_p2: usb2-intr-p2@189 { + reg = <0x189 0x1>; + bits = <2 5>; + }; + u2_intr_p3: usb2-intr-p3@189 { + reg = <0x189 0x2>; + bits = <7 5>; + }; + }; + u3phy2: t-phy@11c40000 { compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; #address-cells = <1>; @@ -877,6 +924,10 @@ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; clock-names = "ref", "da_ref"; + nvmem-cells = <&comb_intr_p1>, + <&comb_rx_imp_p1>, + <&comb_tx_imp_p1>; + nvmem-cell-names = "intr", "rx_imp", "tx_imp"; #phy-cells = <1>; }; }; @@ -901,6 +952,10 @@ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, <&topckgen CLK_TOP_SSUSB_PHY_REF>; clock-names = "ref", "da_ref"; + nvmem-cells = <&u3_intr_p0>, + <&u3_rx_imp_p0>, + <&u3_tx_imp_p0>; + nvmem-cell-names = "intr", "rx_imp", "tx_imp"; #phy-cells = <1>; }; }; From patchwork Fri Jan 28 06:29:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunfeng Yun X-Patchwork-Id: 537882 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85D00C433EF for ; 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Fri, 28 Jan 2022 14:29:05 +0800 From: Chunfeng Yun To: Greg Kroah-Hartman , Matthias Brugger CC: Chunfeng Yun , Rob Herring , Mathias Nyman , , , , , , Tianping Fang , Eddie Hung Subject: [PATCH v2 4/4] arm64: dts: mediatek: mt8195: enable usb remote wakeup Date: Fri, 28 Jan 2022 14:29:02 +0800 Message-ID: <20220128062902.26273-4-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128062902.26273-1-chunfeng.yun@mediatek.com> References: <20220128062902.26273-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Enable USB remote wakeup of all four xHCI controllers Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno --- v2: based on new mt8195 base dts, no need add usb nodes Note: depend on the reviewing patch: [v9,3/3] arm64: dts: Add mediatek SoC mt8195 and evaluation board https://patchwork.kernel.org/patch/12711296 --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 240a21708806..444e5448c9b1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -573,6 +573,8 @@ <&apmixedsys CLK_APMIXED_USB1PLL>, <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; + mediatek,syscon-wakeup = <&pericfg 0x400 103>; + wakeup-source; status = "disabled"; }; @@ -636,6 +638,8 @@ <&apmixedsys CLK_APMIXED_USB1PLL>, <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck"; + mediatek,syscon-wakeup = <&pericfg 0x400 104>; + wakeup-source; status = "disabled"; }; @@ -655,6 +659,8 @@ <&topckgen CLK_TOP_SSUSB_P2_REF>, <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; clock-names = "sys_ck", "ref_ck", "xhci_ck"; + mediatek,syscon-wakeup = <&pericfg 0x400 105>; + wakeup-source; status = "disabled"; }; @@ -674,6 +680,8 @@ <&topckgen CLK_TOP_SSUSB_P3_REF>, <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; clock-names = "sys_ck", "ref_ck", "xhci_ck"; + mediatek,syscon-wakeup = <&pericfg 0x400 106>; + wakeup-source; /* This controller is connected with a BT device. * Disable usb2 lpm to prevent konwn issues. */