From patchwork Thu Nov 22 18:32:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 151813 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1084020ljp; Thu, 22 Nov 2018 10:32:18 -0800 (PST) X-Google-Smtp-Source: AFSGD/VeT+nmdarZOdrZ25283F1R1/9yQgc4B2W2GXr0MjgVk7ivqUqjWcHme3P9UHIBsltjuF4R X-Received: by 2002:a62:4714:: with SMTP id u20mr7134500pfa.144.1542911538077; Thu, 22 Nov 2018 10:32:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542911538; cv=none; d=google.com; s=arc-20160816; b=PLLPn91WzkgnjikE38dqcWiyOa8KYZiA2jl/LpBMxgtLxZELBWqIev2jxs1j8QrKX4 BP9jS0JGPbU39rv8QPlkKWx2fJ+IFVuV28rPW8ug5oogDavYfXsAf9IWGR39kIo8Zh1e LRr8lNZOimzfmAmZr4iWfir0ez3sfTUBZZW1KTiXqCHF5aUbmuprykU7i1zLL/wJ0/1w +uD3LlL6KVYNU++TDGt6/rYyQIf5SrmA5VLYOrBRHk6Kkte36VaXvrslDXZrx79xCa8f 6Wz5DFN5NtFQBz0Q+NOTBCX0/aWMbq8gzim/SUSnVXXNsxR572+cbexk32W6e680srvn nSrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=uiT7mql3LrIBSapvTsOqHQS+ZJhwkLcsbyLxK1A1yks=; b=rUtb/80usx9V+UPf2WqC+KohkrhvRjS08E/mn+oAoSOky0M1bCJTxD/0goxAXmJOCk kOsLngKTqwG3LxvUme99ouky9sGn/4zvkKZ+e5IGHix13hisG5a8imd9i+wvt/mZlh9+ fydOYILI0WmK6Bmtm7p85eqvu74/lghNdbkOxVvWsyS73qq+KQibqxcLaklhsCeLCK7L k5Ucw0FkWaNod5VP1TpSNGwMFICMh0DpKGbTa5+lsvyVgaRUjF2UPetivffv9o0N85+6 gkHMGtduCBxc7KD2BW0xotxX45SVralOOpnNyU4yrTcqBrUhiaFo24FGwBiSuJnKxA4r B1kA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VvA7xev2; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g18si49265561pgg.522.2018.11.22.10.32.16; Thu, 22 Nov 2018 10:32:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VvA7xev2; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726412AbeKWFMt (ORCPT + 15 others); Fri, 23 Nov 2018 00:12:49 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:46651 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725737AbeKWFMt (ORCPT ); Fri, 23 Nov 2018 00:12:49 -0500 Received: by mail-wr1-f66.google.com with SMTP id l9so10126248wrt.13 for ; Thu, 22 Nov 2018 10:32:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uiT7mql3LrIBSapvTsOqHQS+ZJhwkLcsbyLxK1A1yks=; b=VvA7xev20L3m+TpF2gwnYyh3BlgayVedZzAVjvWYZxBDpgNWpTIkBbZtnIaKFIZ3jS e/2mzDiU4QMqFKDqXzzCWm0Xu00JVbRJiKLvUYYC5vZh/2b+zVTm3NfZQOlAQjXIAAi4 5wsm8hbExqTe5z0Q53yNqzXJaH/W9Rg+KvJfk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uiT7mql3LrIBSapvTsOqHQS+ZJhwkLcsbyLxK1A1yks=; b=Tc0swV65ps/XeW1zuC58sWGnGvjlXuol07Q6EWdHSWxjbFnf49MmKABosHiZHr226n FHGiS9g/ep1yBrIF5KWhrqgAwyMFFasutA58tap6u+fleIKyH+VJtAsYzb96N0zFYEsi Ory0bKgS7Ij/Hf4m3aS5DUbjndOJ0le9XCU0uhUDXgbsK32ZuIWXRTsVJJ3zeKvJ83UZ pRZ6u6xacKSceY6QJokVK3YZ2jKLEpu12EA2Vc2c7soqsiANzvDVZ7ErkNkVtY+p0lSH XzIE3R/SSrtn7pbB6xKioXqOXxq0nKMKoFHsr8F305U/tj6p2tl7KSpYDeBJ26Sp3KS1 6wOA== X-Gm-Message-State: AA+aEWYULbD37j71jwl1KkCiakFAkVCx0yow9IoVAVmmGa9WVqCiI+ek THFTk2gMT8smIwakhnjI/Ci7DQ== X-Received: by 2002:adf:f984:: with SMTP id f4mr10916793wrr.234.1542911533683; Thu, 22 Nov 2018 10:32:13 -0800 (PST) Received: from localhost ([103.8.150.191]) by smtp.gmail.com with ESMTPSA id f2sm8562778wru.14.2018.11.22.10.32.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 22 Nov 2018 10:32:13 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, David Brown , Rob Herring , Mark Rutland Subject: [PATCH v1] arm64: dts: msm8998: thermal: split address space into two Date: Fri, 23 Nov 2018 00:02:04 +0530 Message-Id: <565873e4dd152df24c86d091327687f4aa3505e2.1542911304.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We added support to split the register address space for tsens into TM and SROT regions in 'Commit 5b1283984fa3 ("thermal: tsens: Add support to split up register address space into two")'. Split up the tsens address space for msm8998 since it has a similar register layout to other versions of the IP to allow for better code sharing. Signed-off-by: Amit Kucheria --- (Compile-tested only, since I don't have the hardware) arch/arm64/boot/dts/qcom/msm8998.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 78227cce16db..eb4f6f77969f 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -577,17 +577,18 @@ cell-index = <0>; }; - tsens0: thermal@10aa000 { + tsens0: thermal@10ab000 { compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; - reg = <0x10aa000 0x2000>; - + reg = <0x10ab000 0x1000>, /* TM */ + <0x10aa000 0x1000>; /* SROT */ #qcom,sensors = <12>; #thermal-sensor-cells = <1>; }; - tsens1: thermal@10ad000 { + tsens1: thermal@10ae000 { compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; - reg = <0x10ad000 0x2000>; + reg = <0x10ae000 0x1000>, /* TM */ + <0x10ad000 0x1000>; /* SROT */ #qcom,sensors = <8>; #thermal-sensor-cells = <1>;