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[90.55.193.222]) by smtp.gmail.com with ESMTPSA id w2-v6sm11821005wrr.78.2018.11.21.09.40.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Nov 2018 09:40:42 -0800 (PST) From: Loic Poulain To: andy.gross@linaro.org, david.brown@linaro.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Loic Poulain Subject: [PATCH v2] clk: qcom: msm8916: Additional clock rates for spi Date: Wed, 21 Nov 2018 18:40:41 +0100 Message-Id: <1542822041-9675-1-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add SPI friendly clock rates to the spi freq table. Today it's not possible to use SPI at lower than 960Khz. This patch adds 100/250/500/1000 kHz configs to the table. Signed-off-by: Loic Poulain --- v2: reword: s/khz/KHz drivers/clk/qcom/gcc-msm8916.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.7.4 diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index ac2b0aa..7d9647c 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -544,7 +544,11 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { }; static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { + F(100000, P_XO, 16, 2, 24), + F(250000, P_XO, 16, 5, 24), + F(500000, P_XO, 8, 5, 24), F(960000, P_XO, 10, 1, 2), + F(1000000, P_XO, 4, 5, 24), F(4800000, P_XO, 4, 0, 0), F(9600000, P_XO, 2, 0, 0), F(16000000, P_GPLL0, 10, 1, 5),