From patchwork Wed Jan 26 17:55:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 536843 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01B49C63684 for ; Wed, 26 Jan 2022 17:56:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243948AbiAZR4Q (ORCPT ); Wed, 26 Jan 2022 12:56:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230370AbiAZR4P (ORCPT ); Wed, 26 Jan 2022 12:56:15 -0500 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0097CC06173B; Wed, 26 Jan 2022 09:56:14 -0800 (PST) Received: by mail-wr1-x433.google.com with SMTP id w11so428666wra.4; Wed, 26 Jan 2022 09:56:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JQsJN7pJU0BMJyEgmIQu4kyCp2vR66DlJR8TnVMAcyQ=; b=TOQ67iGAT+7+07uNizB8BHdh7jMFRMf/l+pHtOhq2S77YS6VBRszqhcfC+kZOKGRat FDU9kMMTLJivAE7oOHzbCf3euJ2eoS9POx7iSbAzJejOKGfziBKQRm6/eN6yJtZ4JjNx vFgbZP4cgzgnYWq/BcN/VYm47yo6rxWa8EBNCagRH9Zeez4Ck3kKyQe/99aLWlPEXK7K +iBbCm9PFe18TWp3b9s5HkZCH8UCGMUa97bJMgBHMHfT5mCYlcVDpNqdlfb670pi5qHd APrtuHWtdxvmhEDMDFPhiZMxqvLc2XOVGjn53ZbCOx5hVQ1scgGYJ5JbuWeyyEKooKcB oUlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JQsJN7pJU0BMJyEgmIQu4kyCp2vR66DlJR8TnVMAcyQ=; b=CsM+qIF/+auajpwZyWLz/CZq84RgpbxUKozJyUUo7VbwRNMOPzQE+/ephM0sr99EF/ S1LOr/zMGUG0YKmeQogmQOXgq+rbnIl/NTLP1L/1z3EfXM/OQenZEA75ZjcsnVuh8hEA prgqBwt6Zawix7OJorBgY+nxV0GOCBK6gIiy0+p3GAhn2DVXwdfKtrzpW5wL6JTvluu9 WoRzVfSPP+8ArmpJuKo9TuIgMokf9uj3ATNn9zkQO3iV9lSjutkAIuTK+xgH39cjIiYX ognDTbZhG/+LdHGoIrn8hHIHsFafF4OcAVBv3biLHxgX8QJ+ESoWG7heytHvXZ4jvykS lsOw== X-Gm-Message-State: AOAM531+95j7Yj6tsxJER4TN6Yl7Od+1D9Z8o9EWpSD2jdRTKQVW+Sif mlQXUtzoegQGVwCtgYuk3Cs= X-Google-Smtp-Source: ABdhPJx2eb5nlXZaKrsfJpJ+W8WqvxfydVOT6cwaVmM5rRae+FOQ+xqg8ALAfHShxVhcl4JknstmdQ== X-Received: by 2002:a5d:610f:: with SMTP id v15mr23005925wrt.139.1643219773519; Wed, 26 Jan 2022 09:56:13 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id m2sm4072416wmq.35.2022.01.26.09.56.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:56:13 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v4 1/8] dt-bindings: clk: mstar msc313 cpupll binding description Date: Wed, 26 Jan 2022 18:55:57 +0100 Message-Id: <20220126175604.17919-2-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220126175604.17919-1-romain.perier@gmail.com> References: <20220126175604.17919-1-romain.perier@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Daniel Palmer Add a binding description for the MStar/SigmaStar CPU PLL block. Signed-off-by: Daniel Palmer Reviewed-by: Rob Herring --- .../bindings/clock/mstar,msc313-cpupll.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml diff --git a/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml b/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml new file mode 100644 index 000000000000..a9ad7ab5230c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mstar,msc313-cpupll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar/Sigmastar MSC313 CPU PLL + +maintainers: + - Daniel Palmer + +description: | + The MStar/SigmaStar MSC313 and later ARMv7 chips have a scalable + PLL that can be used as the clock source for the CPU(s). + +properties: + compatible: + const: mstar,msc313-cpupll + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clocks + - reg + +additionalProperties: false + +examples: + - | + #include + cpupll: cpupll@206400 { + compatible = "mstar,msc313-cpupll"; + reg = <0x206400 0x200>; + #clock-cells = <1>; + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; From patchwork Wed Jan 26 17:55:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 537252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13390C6369B for ; Wed, 26 Jan 2022 17:56:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243971AbiAZR4R (ORCPT ); Wed, 26 Jan 2022 12:56:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243965AbiAZR4Q (ORCPT ); Wed, 26 Jan 2022 12:56:16 -0500 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A1BAC06161C; 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Wed, 26 Jan 2022 09:56:14 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id 16sm3708753wmj.12.2022.01.26.09.56.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:56:14 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Willy Tarreau Subject: [PATCH v4 2/8] clk: mstar: msc313 cpupll clk driver Date: Wed, 26 Jan 2022 18:55:58 +0100 Message-Id: <20220126175604.17919-3-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220126175604.17919-1-romain.perier@gmail.com> References: <20220126175604.17919-1-romain.perier@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Daniel Palmer Add a driver for the CPU pll/ARM pll/MIPS pll that is present in MStar SoCs. Currently there is no documentation for this block so it's possible this driver isn't entirely correct. Only tested on the version of this IP in the MStar/SigmaStar ARMv7 SoCs. Co-authored-by: Willy Tarreau Signed-off-by: Daniel Palmer --- drivers/clk/mstar/Kconfig | 8 + drivers/clk/mstar/Makefile | 2 +- drivers/clk/mstar/clk-msc313-cpupll.c | 221 ++++++++++++++++++++++++++ 3 files changed, 230 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/mstar/clk-msc313-cpupll.c diff --git a/drivers/clk/mstar/Kconfig b/drivers/clk/mstar/Kconfig index de37e1bce2d2..146eeb637318 100644 --- a/drivers/clk/mstar/Kconfig +++ b/drivers/clk/mstar/Kconfig @@ -1,4 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-only +config MSTAR_MSC313_CPUPLL + bool "MStar CPUPLL driver" + depends on ARCH_MSTARV7 || COMPILE_TEST + default ARCH_MSTARV7 + help + Support for the CPU PLL present on MStar/Sigmastar SoCs. + config MSTAR_MSC313_MPLL bool "MStar MPLL driver" depends on ARCH_MSTARV7 || COMPILE_TEST @@ -7,3 +14,4 @@ config MSTAR_MSC313_MPLL help Support for the MPLL PLL and dividers block present on MStar/Sigmastar SoCs. + diff --git a/drivers/clk/mstar/Makefile b/drivers/clk/mstar/Makefile index f8dcd25ede1d..21296a04e65a 100644 --- a/drivers/clk/mstar/Makefile +++ b/drivers/clk/mstar/Makefile @@ -2,5 +2,5 @@ # # Makefile for mstar specific clk # - +obj-$(CONFIG_MSTAR_MSC313_CPUPLL) += clk-msc313-cpupll.o obj-$(CONFIG_MSTAR_MSC313_MPLL) += clk-msc313-mpll.o diff --git a/drivers/clk/mstar/clk-msc313-cpupll.c b/drivers/clk/mstar/clk-msc313-cpupll.c new file mode 100644 index 000000000000..c57b509e8c20 --- /dev/null +++ b/drivers/clk/mstar/clk-msc313-cpupll.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Daniel Palmer + */ + +#include +#include +#include + +/* + * This IP is not documented outside of the messy vendor driver. + * Below is what we think the registers look like based on looking at + * the vendor code and poking at the hardware: + * + * 0x140 -- LPF low. Seems to store one half of the clock transition + * 0x144 / + * 0x148 -- LPF high. Seems to store one half of the clock transition + * 0x14c / + * 0x150 -- vendor code says "toggle lpf enable" + * 0x154 -- mu? + * 0x15c -- lpf_update_count? + * 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank? + * 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to + * LPF high. + * 0x174 -- Seems to be the PLL lock status bit + * 0x180 -- Seems to be the current frequency, this might need to be populated by software? + * 0x184 / The vendor driver uses these to set the initial value of LPF low + * + * Frequency seems to be calculated like this: + * (parent clock (432mhz) / register_magic_value) * 16 * 524288 + * Only the lower 24 bits of the resulting value will be used. In addition, the + * PLL doesn't seem to be able to lock on frequencies lower than 220 MHz, as + * divisor 0xfb586f (220 MHz) works but 0xfb7fff locks up. + * + * Vendor values: + * frequency - register value + * + * 400000000 - 0x0067AE14 + * 600000000 - 0x00451EB8, + * 800000000 - 0x0033D70A, + * 1000000000 - 0x002978d4, + */ + +#define REG_LPF_LOW_L 0x140 +#define REG_LPF_LOW_H 0x144 +#define REG_LPF_HIGH_BOTTOM 0x148 +#define REG_LPF_HIGH_TOP 0x14c +#define REG_LPF_TOGGLE 0x150 +#define REG_LPF_MYSTERYTWO 0x154 +#define REG_LPF_UPDATE_COUNT 0x15c +#define REG_LPF_MYSTERYONE 0x160 +#define REG_LPF_TRANSITIONCTRL 0x164 +#define REG_LPF_LOCK 0x174 +#define REG_CURRENT 0x180 + +#define LPF_LOCK_TIMEOUT 100000000 + +#define MULTIPLIER_1 16 +#define MULTIPLIER_2 524288 +#define MULTIPLIER (MULTIPLIER_1 * MULTIPLIER_2) + +struct msc313_cpupll { + void __iomem *base; + struct clk_hw clk_hw; +}; + +#define to_cpupll(_hw) container_of(_hw, struct msc313_cpupll, clk_hw) + +static u32 msc313_cpupll_reg_read32(struct msc313_cpupll *cpupll, unsigned int reg) +{ + u32 value; + + value = ioread16(cpupll->base + reg + 4) << 16; + value |= ioread16(cpupll->base + reg); + + return value; +} + +static void msc313_cpupll_reg_write32(struct msc313_cpupll *cpupll, unsigned int reg, u32 value) +{ + u16 l = value & 0xffff, h = (value >> 16) & 0xffff; + + iowrite16(l, cpupll->base + reg); + iowrite16(h, cpupll->base + reg + 4); +} + +static void msc313_cpupll_setfreq(struct msc313_cpupll *cpupll, u32 regvalue) +{ + ktime_t timeout; + + msc313_cpupll_reg_write32(cpupll, REG_LPF_HIGH_BOTTOM, regvalue); + + iowrite16(0x1, cpupll->base + REG_LPF_MYSTERYONE); + iowrite16(0x6, cpupll->base + REG_LPF_MYSTERYTWO); + iowrite16(0x8, cpupll->base + REG_LPF_UPDATE_COUNT); + iowrite16(BIT(12), cpupll->base + REG_LPF_TRANSITIONCTRL); + + iowrite16(0, cpupll->base + REG_LPF_TOGGLE); + iowrite16(1, cpupll->base + REG_LPF_TOGGLE); + + timeout = ktime_add_ns(ktime_get(), LPF_LOCK_TIMEOUT); + while (!(ioread16(cpupll->base + REG_LPF_LOCK))) { + if (ktime_after(ktime_get(), timeout)) { + pr_err("timeout waiting for LPF_LOCK\n"); + return; + } + cpu_relax(); + } + + iowrite16(0, cpupll->base + REG_LPF_TOGGLE); + + msc313_cpupll_reg_write32(cpupll, REG_LPF_LOW_L, regvalue); +} + +static unsigned long msc313_cpupll_frequencyforreg(u32 reg, unsigned long parent_rate) +{ + unsigned long long prescaled = ((unsigned long long)parent_rate) * MULTIPLIER; + + if (prescaled == 0 || reg == 0) + return 0; + return DIV_ROUND_DOWN_ULL(prescaled, reg); +} + +static u32 msc313_cpupll_regforfrequecy(unsigned long rate, unsigned long parent_rate) +{ + unsigned long long prescaled = ((unsigned long long)parent_rate) * MULTIPLIER; + + if (prescaled == 0 || rate == 0) + return 0; + return DIV_ROUND_UP_ULL(prescaled, rate); +} + +static unsigned long msc313_cpupll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct msc313_cpupll *cpupll = to_cpupll(hw); + + return msc313_cpupll_frequencyforreg(msc313_cpupll_reg_read32(cpupll, REG_LPF_LOW_L), + parent_rate); +} + +static long msc313_cpupll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + u32 reg = msc313_cpupll_regforfrequecy(rate, *parent_rate); + long rounded = msc313_cpupll_frequencyforreg(reg, *parent_rate); + + /* + * This is my poor attempt at making sure the resulting + * rate doesn't overshoot the requested rate. + */ + for (; rounded >= rate && reg > 0; reg--) + rounded = msc313_cpupll_frequencyforreg(reg, *parent_rate); + + return rounded; +} + +static int msc313_cpupll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) +{ + struct msc313_cpupll *cpupll = to_cpupll(hw); + u32 reg = msc313_cpupll_regforfrequecy(rate, parent_rate); + + msc313_cpupll_setfreq(cpupll, reg); + + return 0; +} + +static const struct clk_ops msc313_cpupll_ops = { + .recalc_rate = msc313_cpupll_recalc_rate, + .round_rate = msc313_cpupll_round_rate, + .set_rate = msc313_cpupll_set_rate, +}; + +static const struct of_device_id msc313_cpupll_of_match[] = { + { .compatible = "mstar,msc313-cpupll" }, + {} +}; + +static const struct clk_parent_data cpupll_parent = { + .index = 0, +}; + +static int msc313_cpupll_probe(struct platform_device *pdev) +{ + struct clk_init_data clk_init = {}; + struct device *dev = &pdev->dev; + struct msc313_cpupll *cpupll; + int ret; + + cpupll = devm_kzalloc(&pdev->dev, sizeof(*cpupll), GFP_KERNEL); + if (!cpupll) + return -ENOMEM; + + cpupll->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(cpupll->base)) + return PTR_ERR(cpupll->base); + + /* LPF might not contain the current frequency so fix that up */ + msc313_cpupll_reg_write32(cpupll, REG_LPF_LOW_L, + msc313_cpupll_reg_read32(cpupll, REG_CURRENT)); + + clk_init.name = dev_name(dev); + clk_init.ops = &msc313_cpupll_ops; + clk_init.parent_data = &cpupll_parent; + clk_init.num_parents = 1; + cpupll->clk_hw.init = &clk_init; + + ret = devm_clk_hw_register(dev, &cpupll->clk_hw); + if (ret) + return ret; + + return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get, &cpupll->clk_hw); +} + +static struct platform_driver msc313_cpupll_driver = { + .driver = { + .name = "mstar-msc313-cpupll", + .of_match_table = msc313_cpupll_of_match, + }, + .probe = msc313_cpupll_probe, +}; +builtin_platform_driver(msc313_cpupll_driver); From patchwork Wed Jan 26 17:55:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 536842 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD227C636C9 for ; Wed, 26 Jan 2022 17:56:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243981AbiAZR4T (ORCPT ); Wed, 26 Jan 2022 12:56:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243984AbiAZR4S (ORCPT ); Wed, 26 Jan 2022 12:56:18 -0500 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7808C06161C; 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Signed-off-by: Daniel Palmer Reviewed-by: Romain Perier --- arch/arm/boot/dts/mstar-v7.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 89ebfe4f29da..2249faaa3aa7 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -155,6 +155,13 @@ mpll: mpll@206000 { clocks = <&xtal>; }; + cpupll: cpupll@206400 { + compatible = "mstar,msc313-cpupll"; + reg = <0x206400 0x200>; + #clock-cells = <0>; + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; + gpio: gpio@207800 { #gpio-cells = <2>; reg = <0x207800 0x200>; From patchwork Wed Jan 26 17:56:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 537251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13BFEC63697 for ; Wed, 26 Jan 2022 17:56:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244007AbiAZR4U (ORCPT ); Wed, 26 Jan 2022 12:56:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243997AbiAZR4T (ORCPT ); Wed, 26 Jan 2022 12:56:19 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5F0CC061749; Wed, 26 Jan 2022 09:56:18 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id u15so436811wrt.3; Wed, 26 Jan 2022 09:56:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rDNoKV0qv6YEK56MEl2TbFC2RsE/2jQa2ifEdZIoeX0=; b=OqGltRvbjpCNbLcabWMdamxxF4OG4xNm/NOuGRc4l7L7cJ4ZF/20KF43TO2EZGCRap RUbL50jsdvJzLubUTpxcjr7fsjh4sey/1ow5NR6+a+M0LtChHzU3DMOUnC9IQKjoMqQ4 ITznzqwB8tRvcJANRiBOVBza3fBThjqy/eaw37Ji582lyGlYfZnRwjbMo+kifsbqdYp8 3sHD8y5cRzY0RlP4NWAk05iQ6sJZdJeeT/oORHWM+y+QN4OnfRAf1uUNYLADIwic5rzs l+Zvtu0DpULVx5v2qVaK3detxxPtSGS+bifTXhtxl6Oid1BOL/xuu2BaJwJynJ+dwCjm ZroQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rDNoKV0qv6YEK56MEl2TbFC2RsE/2jQa2ifEdZIoeX0=; b=agMuH/MHHeWoPmzsrOYPOMxGBICk/vhV5Rs2O9F5HY+9DFroNmgfn5PQjEfp3p25EN 7+5exEBQdlhbqRPsZvsEopGQb4GjDKAFHw2WOgjhcQGenwqoAcZsWjbhJ3XlcUh1RXn3 MRhAdCL2dPaY9H1sOFkau+Y9JOvnPMVmz4lx0TwddJWFNORJn59Xz9/3D9vwhIkNwJtl F5pQ8YZTf84/BJrtdWIx160V6F6dHxvTcgAvrsCp/Mg6ELdJFIZRZ4XFoZzm7QnO0qbs F6lA90AxUv96NxE+P4ClypQKLEowAHuA/UujHNToLObwVumkMtmUnyaMjax/pz5SpDgL AhwA== X-Gm-Message-State: AOAM530hP5lsDdoOCuSQpA6XFY84uPzH/bTpeM9JINzFAKe4MYs2XvWn McPl4KZQgx+e30kXIGV38imS52tCAKCzLw== X-Google-Smtp-Source: ABdhPJzoRB+ISl3F2EneRHRBb/x6urgHFoQbFid3vN+X+fH/Xm/+JtJ5GvksG57uVSkwv06e9i00Zg== X-Received: by 2002:a5d:6a08:: with SMTP id m8mr23742984wru.355.1643219777015; Wed, 26 Jan 2022 09:56:17 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id s17sm20207613wrm.62.2022.01.26.09.56.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:56:16 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/8] ARM: mstar: Link cpupll to cpu Date: Wed, 26 Jan 2022 18:56:00 +0100 Message-Id: <20220126175604.17919-5-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220126175604.17919-1-romain.perier@gmail.com> References: <20220126175604.17919-1-romain.perier@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Daniel Palmer The CPU clock is sourced from the CPU PLL. Link cpupll to the cpu so that frequency scaling can happen. Signed-off-by: Daniel Palmer Reviewed-by: Romain Perier --- arch/arm/boot/dts/mstar-v7.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 2249faaa3aa7..c26ba9b7b6dd 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -21,6 +21,8 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; + clocks = <&cpupll>; + clock-names = "cpuclk"; }; }; From patchwork Wed Jan 26 17:56:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 536841 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AC33C636C8 for ; Wed, 26 Jan 2022 17:56:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243996AbiAZR4V (ORCPT ); Wed, 26 Jan 2022 12:56:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244004AbiAZR4U (ORCPT ); Wed, 26 Jan 2022 12:56:20 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7436C06173B; Wed, 26 Jan 2022 09:56:19 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id v13so369018wrv.10; Wed, 26 Jan 2022 09:56:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I0fcplD3VFrkCpKgQiNkIlnOuTzfq8ZQ6areILp5ZR4=; b=U9Z/ql/ZK5IhK6P6O4TP//zSS7SALYSv28NVpH43H2c8VeWbavUv6Yczw/oDx7jch8 m+jzH6RY74MMRnWB39XeOeKKP//Ta7fXipFxNH3dToe5KpJCsb21jTrhJINlgdTVV3Yo NXVcNR4GjqEGNoj5p5SlHth02vxqMYXVAwYDevkNIvKQWg9sXt+LsmTimoJhGuKicBcU 7kVJz8+8Te1RWjqJw6mURwfIWOFNTCCj0xR6uakv8JvW/7LH6f1IEKprfI92TlkBB0mE uMhItvJJ6vrTIOkDSJwgqzjf4i6AgbjcIyKNRgdqRFo46N/M8qb0CDS+KI75xB4KmriQ YMZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I0fcplD3VFrkCpKgQiNkIlnOuTzfq8ZQ6areILp5ZR4=; b=y39Rt98bbPFdxeVgRs3BOJio+K2wKsQRpBrrdK6K6OX16CQpLyQlmRMfh6EY5XKP0k 3vJ5doJJSv5JXYmcusxNjLNiZVKEfrmhCFAsSicRx35DcJYN/kTCAvxFXGcd4Pn/WupL vrwjjEqshk+z87dQJ1qFkNyvFTrmX9gS1qQs54t6s0Sd4vn+97auxrn3l7jkpFO7eLwn VIl7Bg3pg7GyUUiMhmnjzwpmedZQWE3J6+/lJ+dQEVDBQBBeGU+LSV68VLuv50mSkv5M pnq0MdRX98g0q4UBy+YJS3SKtJ8O5vwR0fP8neWpzQfqiujHRYa3V7fJ/+MXgFmLqjvz JJoA== X-Gm-Message-State: AOAM533F6pG5ZF38LUPg6cNRb27iOwRayRGlS/QOiG1QoLFXFtugcQxV 6X/Yw3VfDQ4x0SunwTg7bTpb9aJ+vRUyjg== X-Google-Smtp-Source: ABdhPJzllu4IdjHXcUMczo++gtjf4jceZyVT6HHXrsq0SLK7NBDrKCoKTv4YEOEn8X7kGWdEbXOzyA== X-Received: by 2002:a5d:5342:: with SMTP id t2mr23407788wrv.215.1643219777966; Wed, 26 Jan 2022 09:56:17 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id o12sm4632848wmq.41.2022.01.26.09.56.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:56:17 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 5/8] ARM: mstar: Link cpupll to second core Date: Wed, 26 Jan 2022 18:56:01 +0100 Message-Id: <20220126175604.17919-6-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220126175604.17919-1-romain.perier@gmail.com> References: <20220126175604.17919-1-romain.perier@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Daniel Palmer The second core also sources it's clock from the CPU PLL. Signed-off-by: Daniel Palmer Reviewed-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi index 6d4d1d224e96..dc339cd29778 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -11,6 +11,8 @@ cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x1>; + clocks = <&cpupll>; + clock-names = "cpuclk"; }; }; From patchwork Wed Jan 26 17:56:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 537250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43D91C2BA4C for ; Wed, 26 Jan 2022 17:56:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244012AbiAZR4V (ORCPT ); Wed, 26 Jan 2022 12:56:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243986AbiAZR4U (ORCPT ); Wed, 26 Jan 2022 12:56:20 -0500 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75339C06161C; Wed, 26 Jan 2022 09:56:20 -0800 (PST) Received: by mail-wr1-x42d.google.com with SMTP id c23so418571wrb.5; Wed, 26 Jan 2022 09:56:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=987i68G0hoSD7befa/sZSvlzgSvWjRDhljDEuS8vWhM=; b=YW2UrPWX3Gqj7NPwSuzV0pZYMXbe6mghkz4zxiAfBMsjgRWORd2wNL9Ngd0v113N6Q l/d1ujsUKh1C4a0IkFe8cWm+W55eBPI8OLU3IMuLr9EGPsdBU4rzmsosqxzuQ9Ra1r/J GbSDXVoiYDUuKwVBb77ylkN5/wMJC/3VLqFFLlURyO5RM6w4/Vje+9MOMzsxWs5tLCI0 TjCwXoXSyssc+muDW3ktraSDb8P60usz7GTOr/Id/aOa4bi2mp7gD69wquIF8u3ir2YU 8m1A4uLkadQxpmnR4K6Qjs0JcHTAEaMTH8Fxq6M3ZWndr+S0XSXb3+m5bD9pQvb0hEOe Xv2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=987i68G0hoSD7befa/sZSvlzgSvWjRDhljDEuS8vWhM=; b=TGgFJYJbfgU5d9TNRvl1Jwk71CIk3XcCnfxL6FGC4fv/N3Dz/a+FrPGUbrfF+lXi/l DoDIY31l3y87/mDhIGgYB0W1YSczi7rFipoBQr5BJUPLsaaLv2rV5jut2hjJpYG0J877 riBNPwdv3pexREzbNJms3jBclhau/A7PDPM11UTXJUEE3Cp888y/0ngAG4jyCs2qMb6U EkJaxJjE0AHrjbr0GhFbMi1eiFAjAcHZsYv8lNi7/mKAftFpvtG5kaEybYV/Rv7QzA+d jZ9ESUcHSg79AHOz4MzwvU7zU50wLYEJV43Wn/p2uaFewCKYltL+5ieCr8yKmqZ+M2wX yvhw== X-Gm-Message-State: AOAM5312L2XU5KgS0ODZ2thJuNZZhyD9K3G/wAqpoR+6iam0mhQe9+D9 1p4lplZA0WxocSRBHgQGQVc= X-Google-Smtp-Source: ABdhPJyUUeUIz50LPFJ1txfvAZ2tlqLG/uX9p2O822Wau+U7NjY7bHm99jmtJ6NwczP49HCwt50baQ== X-Received: by 2002:adf:f791:: with SMTP id q17mr23246847wrp.340.1643219779015; Wed, 26 Jan 2022 09:56:19 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id o2sm2179098wmq.21.2022.01.26.09.56.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:56:18 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Willy Tarreau Subject: [PATCH v4 6/8] ARM: mstar: Add OPP table for infinity Date: Wed, 26 Jan 2022 18:56:02 +0100 Message-Id: <20220126175604.17919-7-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220126175604.17919-1-romain.perier@gmail.com> References: <20220126175604.17919-1-romain.perier@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Daniel Palmer Add an OPP table for the inifinity chips so that cpu frequency scaling can happen. Co-authored-by: Willy Tarreau Signed-off-by: Daniel Palmer Reviewed-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity.dtsi | 34 +++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/mstar-infinity.dtsi index 0bee517797f4..441a917b88ba 100644 --- a/arch/arm/boot/dts/mstar-infinity.dtsi +++ b/arch/arm/boot/dts/mstar-infinity.dtsi @@ -8,6 +8,40 @@ #include +/ { + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; +}; + &imi { reg = <0xa0000000 0x16000>; }; From patchwork Wed Jan 26 17:56:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 536840 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A462CC28CF5 for ; Wed, 26 Jan 2022 17:56:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244017AbiAZR4X (ORCPT ); Wed, 26 Jan 2022 12:56:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244015AbiAZR4V (ORCPT ); Wed, 26 Jan 2022 12:56:21 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E5E6C06173B; Wed, 26 Jan 2022 09:56:21 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id r7so183705wmq.5; Wed, 26 Jan 2022 09:56:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YbbfYaxNXJjiNo8O6xmEfb2M0Ik6NihxDDvfwKnfopE=; b=LLbJQvi+fx8IkX14ezqcJmTTKm1B3+EKjhaD/fKavWP4YIT5w+OIlgUqgouf09gROv eTCkFvChgj2vYIN+H2LbJh1XMa3gCZT5U3VeXFwvvp8W3QEiBlAXf1uJbGwrB7IOgu2G TPDTU45uGhS8eoy2095OIN+S7KLNXNmvNdhBjqVQL1PxwBTML4SUADU//0yXRw2NHAdO DmCuRNMMxGTrD2zWP40nvf5KOkwreYz3iI7Qh2AJwSzYtefrm7h+zbAk0XoiKzOMkPwU vB/LhfmBJLHEWVEU7ZpZv2BK0uORZq897AQ1Rbxnw7L3JZG2Bavd55l237TbMvWhvyvj 39RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YbbfYaxNXJjiNo8O6xmEfb2M0Ik6NihxDDvfwKnfopE=; b=lK3QJlzto7RWaIRCNw3D3J3lgYZltnLe2DfsqLAA6uWjm1pXhs4fXlxkEvei1ATFHD ahWGc0+igwvitUGKgU8TvK6E8t5JcSsAcE7FkgiLV5wgx8HeWjGmS+hrhdm6SBiXQtNd PRLvctf1fbT+hRZlXr/JDkHApOoR2BhD/NIUtZ32/Vo7VOqkbHONTj0Vo/jbw88cBo5L na761/W7VMoKjL1Yr+bvQgm/v4WiuDE1vFnNH5jxF78w6qW0otulU52ThalfS9QtuIKO mODn41jQsWXiYc8D7L4zrvzRQG+w5ZPqEJblxKu+evH9BcRYLSG8UiNam0rPvY75kn8Q 2NJw== X-Gm-Message-State: AOAM532mbRGvxAiIln7nuRHRbotLMQH1brORvRAvVeJAwgzJi9KsPkZ+ 0A3DLI9IAjVfddfXp8147n4= X-Google-Smtp-Source: ABdhPJyBNh0xEqsTSW37ZhKBR1IOZtVGY211ApiFMYBC1fYxhO0v5UJvpml8Lc7sVcNj/31SGIzgBQ== X-Received: by 2002:a05:600c:2245:: with SMTP id a5mr8052798wmm.8.1643219780052; Wed, 26 Jan 2022 09:56:20 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id u3sm10515371wrs.55.2022.01.26.09.56.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:56:19 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Willy Tarreau Subject: [PATCH v4 7/8] ARM: mstar: Add OPP table for infinity3 Date: Wed, 26 Jan 2022 18:56:03 +0100 Message-Id: <20220126175604.17919-8-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220126175604.17919-1-romain.perier@gmail.com> References: <20220126175604.17919-1-romain.perier@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Daniel Palmer The infinity3 has a slightly higher max frequency compared to the infinity so extend the OPP table. Co-authored-by: Willy Tarreau Signed-off-by: Daniel Palmer Reviewed-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity3.dtsi | 58 ++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity3.dtsi b/arch/arm/boot/dts/mstar-infinity3.dtsi index 9857e2a9934d..a56cf29e5d82 100644 --- a/arch/arm/boot/dts/mstar-infinity3.dtsi +++ b/arch/arm/boot/dts/mstar-infinity3.dtsi @@ -6,6 +6,64 @@ #include "mstar-infinity.dtsi" +&cpu0_opp_table { + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + // overclock frequencies below, shown to work fine up to 1.3 GHz + opp-108000000 { + opp-hz = /bits/ 64 <1080000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1188000000 { + opp-hz = /bits/ 64 <1188000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1404000000 { + opp-hz = /bits/ 64 <1404000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1458000000 { + opp-hz = /bits/ 64 <1458000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; +}; + &imi { reg = <0xa0000000 0x20000>; }; From patchwork Wed Jan 26 17:56:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 537249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CE83C63682 for ; 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Wed, 26 Jan 2022 09:56:20 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 8/8] ARM: mstar: Extend opp_table for infinity2m Date: Wed, 26 Jan 2022 18:56:04 +0100 Message-Id: <20220126175604.17919-9-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220126175604.17919-1-romain.perier@gmail.com> References: <20220126175604.17919-1-romain.perier@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org infinity2m are running up to 1.2Ghz, this extends opp_table with the corresponding frequencies and enable operating-points table for cpu1 Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi index dc339cd29778..1b485efd7156 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -6,10 +6,25 @@ #include "mstar-infinity.dtsi" +&cpu0_opp_table { + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; +}; + &cpus { cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; + operating-points-v2 = <&cpu0_opp_table>; reg = <0x1>; clocks = <&cpupll>; clock-names = "cpuclk";