From patchwork Tue Jan 25 13:18:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Horatiu Vultur X-Patchwork-Id: 536664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E299C433FE for ; Tue, 25 Jan 2022 13:20:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1576333AbiAYNUi (ORCPT ); Tue, 25 Jan 2022 08:20:38 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:24122 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1575981AbiAYNSg (ORCPT ); Tue, 25 Jan 2022 08:18:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1643116714; x=1674652714; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vvI7xxALN8Ca1rL4bFGP5vkD357sP5EjMT1bx/alGhk=; b=lr5754exLlxygaLWBwfcMs3oqiNx33q6INHnyoQrSL38ZGk83IssPlp8 y99zSLTnjZ2I7RU3maHSW0AJbasN0/cRqL6TmBI2022HRbCFdLrcSLt1e Ms5lg+ChkD7U0/pQt4x5OcTQxiWZNBvW5hl2+QjZAFcV1ZyktgdQJuJrn opckjpX1rH5cotPRn2ZPO3Q6pavgZwTvzTkf7G8XIwAC07BY6AK9PiyYq QCDyTroD+LgMwtBMducawRAxWSATv3BOFJ+vX7UYZAcZQYYzeLYW0cu9J fsLcMk6KcVehDH4Eqv1rnMQk3KiD4vDinTy14o2wmhHGv/0Ajmx9Gc4BK w==; IronPort-SDR: HBC1ECpJBB1aDF8AZul142f1LxsTDJueQ7lEvq/YRoLXqZ8R0oqYkhjFQy08LldkYgzrt/6SOv sjil7+OU+6PAzyYeIFOT3T2/LUho1HwHuDMQeBhZQPR8ZfN0ylzSUAbDN48HuU+JRuh9JAlZmn tg2Fe5nfHmVJt2SEQ9PBy74TA5b0P/lNDEi0uGzp5cCdqu0WmolQ834vgU+5nWX3nSgMlXmqaS PpACcLNGnIsrXDQJq+gLEFvjhe2/oGstytZKZ2ugzcYdvHRLXI2ZU0EIAaOwhAyyoDElkU07kS DdadiCCRncldV3JQdX16i8we X-IronPort-AV: E=Sophos;i="5.88,315,1635231600"; d="scan'208";a="83600692" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Jan 2022 06:18:23 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 25 Jan 2022 06:18:23 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 25 Jan 2022 06:18:22 -0700 From: Horatiu Vultur To: , , CC: , , Horatiu Vultur Subject: [PATCH 1/2] dt-bindings: pinctrl: ocelot: Add ServalT SoC support Date: Tue, 25 Jan 2022 14:18:57 +0100 Message-ID: <20220125131858.309237-2-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220125131858.309237-1-horatiu.vultur@microchip.com> References: <20220125131858.309237-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the documentation for the Microsemi ServalT pinmuxing and gpio controller. Signed-off-by: Horatiu Vultur --- .../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt index 3bb76487669f..5d84fd299ccf 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -4,8 +4,8 @@ Microsemi Ocelot pin controller Device Tree Bindings Required properties: - compatible : Should be "mscc,ocelot-pinctrl", "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", - "mscc,luton-pinctrl", "mscc,serval-pinctrl" or - "microchip,lan966x-pinctrl" + "mscc,luton-pinctrl", "mscc,serval-pinctrl", + "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. From patchwork Tue Jan 25 13:18:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Horatiu Vultur X-Patchwork-Id: 536663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92D10C433FE for ; Tue, 25 Jan 2022 13:21:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1575747AbiAYNUk (ORCPT ); Tue, 25 Jan 2022 08:20:40 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:47315 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1575982AbiAYNSg (ORCPT ); Tue, 25 Jan 2022 08:18:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1643116714; x=1674652714; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zEy6c3Xr7K/oyYt7/Wet9D7vJ9CLbnE1y+wa+Dz6Xns=; b=sIKEqSha92jvmkDnSRUrWx4GNjIDgoQ6rL5qEqxobwVwaiY87hjrd7ax 6qgPU7mG3YyNC8QbbZ2pzgS6B8P68Ghb5w7w9Q+XW21O14O7XbNQov0g+ A32Ixa1OulUa+l+/Qc4RsaFCJ+8BO/IAyG6W69uDelyhXOxOWgLInWbX+ reIqLVgUeD9ku8tCVs3zkn2NVKhIpprGUb3NWCRiXPSwjbLz/mHZAWQVX WupQsxZQXhjaXAa3nHkOfsqB9RxbIedjCMGbeqS17Hg1x5x7rCwkatRYg mTOWnsO4YDmsGhIWkluvnzKP4lTYHNzj2bCXKabBmiym6tjLwONKZE1kF Q==; IronPort-SDR: LLQFX5w+UQNRZF5jDfF95sy2BnM9f5Mmn7Y7WQqT0dUfBEpnvqtLQKl2E1A+IC3GdW4lM9QNMz Jqp/PxtWLyoPeBMwWeyoizcjPzK2ccvhZahdxGJrjoJO0vQONgHd795jjoDxRcwZFaRYZ0c2lA Yo7hgm2cMX9deInCfVSevm01WqBEaFsCBzi+KdNOoq7Sm0QQ0xeO3JiJc4pGL+Cto4FQ4TEP04 oVxVDgCWcQFjn7nt69qHItKTEkFAirvqm0gW2Gom9uRGD5PXHbymRGZf37Ly9RuQAdSknl2Daa s7h/lrQNCokfFKWbumxKsrBD X-IronPort-AV: E=Sophos;i="5.88,315,1635231600"; d="scan'208";a="146528375" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Jan 2022 06:18:25 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 25 Jan 2022 06:18:25 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 25 Jan 2022 06:18:23 -0700 From: Horatiu Vultur To: , , CC: , , Horatiu Vultur Subject: [PATCH 2/2] pinctrl: ocelot: Add support for ServalT SoC Date: Tue, 25 Jan 2022 14:18:58 +0100 Message-ID: <20220125131858.309237-3-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220125131858.309237-1-horatiu.vultur@microchip.com> References: <20220125131858.309237-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds support for ServalT pinctrl, using the ocelot driver as basis. Signed-off-by: Horatiu Vultur --- drivers/pinctrl/pinctrl-ocelot.c | 102 +++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index fc969208d904..685c79e08d40 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -695,6 +695,98 @@ static const struct pinctrl_pin_desc jaguar2_pins[] = { JAGUAR2_PIN(63), }; +#define SERVALT_P(p, f0, f1, f2) \ +static struct ocelot_pin_caps servalt_pin_##p = { \ + .pin = p, \ + .functions = { \ + FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ + }, \ +} + +SERVALT_P(0, SG0, NONE, NONE); +SERVALT_P(1, SG0, NONE, NONE); +SERVALT_P(2, SG0, NONE, NONE); +SERVALT_P(3, SG0, NONE, NONE); +SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); +SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); +SERVALT_P(6, UART, NONE, NONE); +SERVALT_P(7, UART, NONE, NONE); +SERVALT_P(8, SI, SFP, TWI_SCL_M); +SERVALT_P(9, PCI_WAKE, SFP, SI); +SERVALT_P(10, PTP0, SFP, TWI_SCL_M); +SERVALT_P(11, PTP1, SFP, TWI_SCL_M); +SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); +SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); +SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); +SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); +SERVALT_P(16, TACHO, SFP, SI); +SERVALT_P(17, PWM, NONE, TWI_SCL_M); +SERVALT_P(18, PTP2, SFP, SI); +SERVALT_P(19, PTP3, SFP, SI); +SERVALT_P(20, UART2, SFP, SI); +SERVALT_P(21, UART2, NONE, NONE); +SERVALT_P(22, MIIM, SFP, TWI2); +SERVALT_P(23, MIIM, SFP, TWI2); +SERVALT_P(24, TWI, NONE, NONE); +SERVALT_P(25, TWI, SFP, TWI_SCL_M); +SERVALT_P(26, TWI_SCL_M, SFP, SI); +SERVALT_P(27, TWI_SCL_M, SFP, SI); +SERVALT_P(28, TWI_SCL_M, SFP, SI); +SERVALT_P(29, TWI_SCL_M, NONE, NONE); +SERVALT_P(30, TWI_SCL_M, NONE, NONE); +SERVALT_P(31, TWI_SCL_M, NONE, NONE); +SERVALT_P(32, TWI_SCL_M, NONE, NONE); +SERVALT_P(33, RCVRD_CLK, NONE, NONE); +SERVALT_P(34, RCVRD_CLK, NONE, NONE); +SERVALT_P(35, RCVRD_CLK, NONE, NONE); +SERVALT_P(36, RCVRD_CLK, NONE, NONE); + +#define SERVALT_PIN(n) { \ + .number = n, \ + .name = "GPIO_"#n, \ + .drv_data = &servalt_pin_##n \ +} + +static const struct pinctrl_pin_desc servalt_pins[] = { + SERVALT_PIN(0), + SERVALT_PIN(1), + SERVALT_PIN(2), + SERVALT_PIN(3), + SERVALT_PIN(4), + SERVALT_PIN(5), + SERVALT_PIN(6), + SERVALT_PIN(7), + SERVALT_PIN(8), + SERVALT_PIN(9), + SERVALT_PIN(10), + SERVALT_PIN(11), + SERVALT_PIN(12), + SERVALT_PIN(13), + SERVALT_PIN(14), + SERVALT_PIN(15), + SERVALT_PIN(16), + SERVALT_PIN(17), + SERVALT_PIN(18), + SERVALT_PIN(19), + SERVALT_PIN(20), + SERVALT_PIN(21), + SERVALT_PIN(22), + SERVALT_PIN(23), + SERVALT_PIN(24), + SERVALT_PIN(25), + SERVALT_PIN(26), + SERVALT_PIN(27), + SERVALT_PIN(28), + SERVALT_PIN(29), + SERVALT_PIN(30), + SERVALT_PIN(31), + SERVALT_PIN(32), + SERVALT_PIN(33), + SERVALT_PIN(34), + SERVALT_PIN(35), + SERVALT_PIN(36), +}; + #define SPARX5_P(p, f0, f1, f2) \ static struct ocelot_pin_caps sparx5_pin_##p = { \ .pin = p, \ @@ -1497,6 +1589,15 @@ static struct pinctrl_desc jaguar2_desc = { .owner = THIS_MODULE, }; +static struct pinctrl_desc servalt_desc = { + .name = "servalt-pinctrl", + .pins = servalt_pins, + .npins = ARRAY_SIZE(servalt_pins), + .pctlops = &ocelot_pctl_ops, + .pmxops = &ocelot_pmx_ops, + .owner = THIS_MODULE, +}; + static struct pinctrl_desc sparx5_desc = { .name = "sparx5-pinctrl", .pins = sparx5_pins, @@ -1774,6 +1875,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = { { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, + { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, {},