From patchwork Mon Jan 24 20:12:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 534629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0359C433FE for ; Mon, 24 Jan 2022 20:19:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1381111AbiAXUSz (ORCPT ); Mon, 24 Jan 2022 15:18:55 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:54008 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379804AbiAXUMl (ORCPT ); Mon, 24 Jan 2022 15:12:41 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 510AFB810AF; Mon, 24 Jan 2022 20:12:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EF883C340EB; Mon, 24 Jan 2022 20:12:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643055158; bh=46GvYvu2qBY0XJLufv8o7VnMQWHTSSvKJFHbggT3hWo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XzqZtHU43pqSF9cnPOVi8OzU/ekycmEQngryg7+eDdRwKqRJX2qpAum18krWHJGuf 5GqY3AfzVo+a5osEltJIsNqoz6lIsgLpVcAImdP7V5wvCkHZEsK7iswC2qVdhLy5NB TVv3rzPluMu3sGx9D/eX39AR5Evih3nlB6i1DFMJBB1iTYunHgWMUQqNnqmvHxTP7U PtzOuGJV0TEQPEzosRtaaa+/2Gl6FA9rCQ6ZIY6zfmyPyhL9m6G4sxfdU8DNBcARDt c5IYIPwMeWVuEfg5J6eKvKjZ2sTsQsXeZi9lLj5n+YScKJgy/UXjuAwmYEyhhScvpL bUOkTXBBFCMSg== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nC5hc-002Y3f-0D; Mon, 24 Jan 2022 20:12:36 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com, Rob Herring Subject: [PATCH v4 01/10] dt-bindings: arm-pmu: Document Apple PMU compatible strings Date: Mon, 24 Jan 2022 20:12:22 +0000 Message-Id: <20220124201231.298961-2-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220124201231.298961-1-maz@kernel.org> References: <20220124201231.298961-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com, robh@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As we are about to add support fur the Apple PMUs, document the compatible strings associated with the two micro-architectures present in the Apple M1. Acked-by: Rob Herring Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index 981bac451698..7a04b8aaaec3 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -20,6 +20,8 @@ properties: items: - enum: - apm,potenza-pmu + - apple,firestorm-pmu + - apple,icestorm-pmu - arm,armv8-pmuv3 # Only for s/w models - arm,arm1136-pmu - arm,arm1176-pmu From patchwork Mon Jan 24 20:12:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 534630 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16DDBC433EF for ; Mon, 24 Jan 2022 20:18:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1381068AbiAXUSv (ORCPT ); Mon, 24 Jan 2022 15:18:51 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:54018 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348693AbiAXUMl (ORCPT ); Mon, 24 Jan 2022 15:12:41 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id D3CE8B8123F; Mon, 24 Jan 2022 20:12:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 83020C340F5; Mon, 24 Jan 2022 20:12:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643055158; bh=LIpzrBypwYEGVNUjiOpGMHuLMUB4NRzeRBE/q+tX41U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O0w4JTLS/QPzG+PD1NU35JZbHIr5W+1sR2XF3TomuspTnLcw1SSE95XTSH+9A+aYA EEwhHMGpY1pSBYOWxDLDh6rm3SrBM4FCg96UgZwnnLlcb1LirMecVjvManY5yQfHng pkMggytohHcloxokTUvb5xlqvSGAzrxuR0chBgQVwPqJJubsUvGsZigL/Gsk5FJna3 04un9rXI/o6KX674qY5mFYorTU3mx61hJOU/uHIbXl0DAkcyDMJjfWsQJsa4aPTlz4 v6XzxNs+7sEE+O0WR8HUN/WYnizhQxszb/iUc8M6chuTwZyZ912WpN3yokS026Wc8I QuzdNqDrCrCMA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nC5hc-002Y3f-JF; Mon, 24 Jan 2022 20:12:36 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v4 03/10] dt-bindings: apple, aic: Add affinity description for per-cpu pseudo-interrupts Date: Mon, 24 Jan 2022 20:12:24 +0000 Message-Id: <20220124201231.298961-4-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220124201231.298961-1-maz@kernel.org> References: <20220124201231.298961-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some of the FIQ per-cpu pseudo-interrupts are better described with a specific affinity, the most obvious candidate being the CPU PMUs. Augment the AIC binding to be able to specify that affinity in the interrupt controller node. Signed-off-by: Marc Zyngier --- .../interrupt-controller/apple,aic.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml index c7577d401786..d97683eb2c54 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -70,6 +70,33 @@ properties: power-domains: maxItems: 1 + affinities: + type: object + description: + FIQ affinity can be expressed as a single "affinities" node, + containing a set of sub-nodes, one per FIQ with a non-default + affinity. + patternProperties: + "^.+-affinity$": + type: object + properties: + fiq-index: + description: + The interrupt number specified as a FIQ, and for which + the affinity is not the default. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 5 + + cpus: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should be a list of phandles to CPU nodes (as described in + Documentation/devicetree/bindings/arm/cpus.yaml). + + required: + - fiq-index + - cpus + required: - compatible - '#interrupt-cells' From patchwork Mon Jan 24 20:12:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 534626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1D18C4167D for ; Mon, 24 Jan 2022 21:38:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378131AbiAXViv (ORCPT ); Mon, 24 Jan 2022 16:38:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1450006AbiAXVRn (ORCPT ); Mon, 24 Jan 2022 16:17:43 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93E07C067A6C; Mon, 24 Jan 2022 12:12:41 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5A80EB81239; Mon, 24 Jan 2022 20:12:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0EEBAC340F0; Mon, 24 Jan 2022 20:12:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643055159; bh=YFbjp7SnnvEiZt+2COv/vSHjC8OQzGUpP2h1k/W2R1I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bZRhLu+xJf8N1IDy93rbW47QecJUpX77o8mQEIOOF7A8eQEBabUQ3kzXWctqC5O+E 8Cw2scnwPeTHNN56+3im/amP8m2TpqLLiH0HETbMaVCa9XNcrgXisLzs8/PSa/ZDeD DXnIXjnCS4hxznqN4IzgUtqdeKS+xG9ylWkmYDBm+aY6GVJVusxMDy/4summ4vUvT1 w2ClXvyYmsCCAzVp5zN7BADiQyi7ZGljw46Y+Ggpss/eRNkR/NbtwHCql7kn2IVzob y9TA8dqerw4krkJYAKNOkgXwNzwDtd9rTFN7RFjGjMh0xLl7sihOzu6sAZZOa84lbF dD1Yn/ysEJkxA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nC5hd-002Y3f-4l; Mon, 24 Jan 2022 20:12:37 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v4 05/10] irqchip/apple-aic: Wire PMU interrupts Date: Mon, 24 Jan 2022 20:12:26 +0000 Message-Id: <20220124201231.298961-6-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220124201231.298961-1-maz@kernel.org> References: <20220124201231.298961-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the necessary code to configure and P and E-core PMU interrupts with their respective affinities. When such an interrupt fires, map it onto the right pseudo-interrupt. Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-apple-aic.c | 34 +++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c index 2d31ac605573..9daa28c55fa1 100644 --- a/drivers/irqchip/irq-apple-aic.c +++ b/drivers/irqchip/irq-apple-aic.c @@ -155,7 +155,7 @@ #define SYS_IMP_APL_UPMSR_EL1 sys_reg(3, 7, 15, 6, 4) #define UPMSR_IACT BIT(0) -#define AIC_NR_FIQ 4 +#define AIC_NR_FIQ 6 #define AIC_NR_SWIPI 32 /* @@ -416,16 +416,15 @@ static void __exception_irq_entry aic_handle_fiq(struct pt_regs *regs) aic_irqc->nr_hw + AIC_TMR_EL02_VIRT); } - if ((read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & (PMCR0_IMODE | PMCR0_IACT)) == - (FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_FIQ) | PMCR0_IACT)) { - /* - * Not supported yet, let's figure out how to handle this when - * we implement these proprietary performance counters. For now, - * just mask it and move on. - */ - pr_err_ratelimited("PMC FIQ fired. Masking.\n"); - sysreg_clear_set_s(SYS_IMP_APL_PMCR0_EL1, PMCR0_IMODE | PMCR0_IACT, - FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_OFF)); + if (read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & PMCR0_IACT) { + int irq; + if (cpumask_test_cpu(smp_processor_id(), + &aic_irqc->fiq_aff[AIC_CPU_PMU_P]->aff)) + irq = AIC_CPU_PMU_P; + else + irq = AIC_CPU_PMU_E; + generic_handle_domain_irq(aic_irqc->hw_domain, + aic_irqc->nr_hw + irq); } if (FIELD_GET(UPMCR0_IMODE, read_sysreg_s(SYS_IMP_APL_UPMCR0_EL1)) == UPMCR0_IMODE_FIQ && @@ -465,7 +464,18 @@ static int aic_irq_domain_map(struct irq_domain *id, unsigned int irq, handle_fasteoi_irq, NULL, NULL); irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); } else { - irq_set_percpu_devid(irq); + int fiq = hw - ic->nr_hw; + + switch (fiq) { + case AIC_CPU_PMU_P: + case AIC_CPU_PMU_E: + irq_set_percpu_devid_partition(irq, &ic->fiq_aff[fiq]->aff); + break; + default: + irq_set_percpu_devid(irq); + break; + } + irq_domain_set_info(id, irq, hw, &fiq_chip, id->host_data, handle_percpu_devid_irq, NULL, NULL); } From patchwork Mon Jan 24 20:12:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 534631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89EC1C433F5 for ; Mon, 24 Jan 2022 20:18:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347747AbiAXUSr (ORCPT ); Mon, 24 Jan 2022 15:18:47 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:39684 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347369AbiAXUMk (ORCPT ); Mon, 24 Jan 2022 15:12:40 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2C44261446; Mon, 24 Jan 2022 20:12:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8CF9AC340EC; Mon, 24 Jan 2022 20:12:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643055159; bh=YaKveBwpxFwRietemPz69WhA3Q6XcSoMygr0LTUe+c4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dzdSp0Q/0bEw3FZcskjmxWxEv4BUzUpUo927d5k7SvXXcPEyMGltnVzcvfNiEjqFr yuVUkoOvuZKkm4rk50GKgf7+ncr9dn/XFDy7huf7kNMC77demCKwDc23kn+N6moIDe ix6y3tsXqiDFDuPxyKg+eHyHEbuyp29CtpygcpNqu9soLQYt77DY/ZcZdo+mC5CJ+H bnl4/ckal2VijVyUs/wyJplYBlARw5w960SEPbmzBtsWxqOh5wjyS9UmFmdLRPmZWu ZfnnJmqp5tKpz89g05zaXlhT7KbeLH1CDbJ9RwtYrx4tTI2bYVWpOUhlrUfuxZTYpq 3ysRYa5uA/XDQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nC5hd-002Y3f-Nx; Mon, 24 Jan 2022 20:12:37 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v4 07/10] arm64: dts: apple: Add t8303 PMU nodes Date: Mon, 24 Jan 2022 20:12:28 +0000 Message-Id: <20220124201231.298961-8-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220124201231.298961-1-maz@kernel.org> References: <20220124201231.298961-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Advertise the two PMU nodes for the t8103 SoC. Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- arch/arm64/boot/dts/apple/t8103.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index ca856f9955d8..aa0768ecb800 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -97,6 +97,18 @@ timer { ; }; + pmu-e { + compatible = "apple,icestorm-pmu"; + interrupt-parent = <&aic>; + interrupts = ; + }; + + pmu-p { + compatible = "apple,firestorm-pmu"; + interrupt-parent = <&aic>; + interrupts = ; + }; + clkref: clock-ref { compatible = "fixed-clock"; #clock-cells = <0>; From patchwork Mon Jan 24 20:12:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 534627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE839C43219 for ; Mon, 24 Jan 2022 21:38:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377999AbiAXVit (ORCPT ); Mon, 24 Jan 2022 16:38:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1449996AbiAXVRk (ORCPT ); Mon, 24 Jan 2022 16:17:40 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96958C067A6D; Mon, 24 Jan 2022 12:12:41 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6B37D6137A; Mon, 24 Jan 2022 20:12:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D139DC340EB; Mon, 24 Jan 2022 20:12:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643055160; bh=byMO3nYSC2TvSH32oHHrAxbZ7HoV85bYK3g6rU+Vckk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ebm4MB3E88Yqn7BvQzfMhMEsishhVM9UX7r3FPZu846+SL16XmVkZHDFFbeOw/RS9 TWWh5aN2GJa/EBJPnVKVQyVHCEiEN+t9tqlBHiUXiznH51+NefoYO/vDxfMVtDU+Hy /aYkJL44EeYBfkj1HjzdzSrRLARG5NjUu/O/NJ3/3uiyNTzZgsl1PlhTh4/4pxuTe/ K76MRh7c5RfUO/EgezAlJNQoo89bSIFXn80CR50EIkCRvbTR45TFXXKCuedF3mUVuG dgGYhI5GT/gtzT9eqsWjkPHE+c/uEmFWYa6I5pfHj+4ShNIcjkpkXTNiBMC3CcgOC1 K2lDT3qIKpfoA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nC5hf-002Y3f-07; Mon, 24 Jan 2022 20:12:39 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v4 09/10] drivers/perf: arm_pmu: Handle 47 bit counters Date: Mon, 24 Jan 2022 20:12:30 +0000 Message-Id: <20220124201231.298961-10-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220124201231.298961-1-maz@kernel.org> References: <20220124201231.298961-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The current ARM PMU framework can only deal with 32 or 64bit counters. Teach it about a 47bit flavour. Yes, this is odd. Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- drivers/perf/arm_pmu.c | 2 ++ include/linux/perf/arm_pmu.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 295cc7952d0e..0a9ed1a061ac 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -109,6 +109,8 @@ static inline u64 arm_pmu_event_max_period(struct perf_event *event) { if (event->hw.flags & ARMPMU_EVT_64BIT) return GENMASK_ULL(63, 0); + else if (event->hw.flags & ARMPMU_EVT_47BIT) + return GENMASK_ULL(46, 0); else return GENMASK_ULL(31, 0); } diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 2512e2f9cd4e..0407a38b470a 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -26,6 +26,8 @@ */ /* Event uses a 64bit counter */ #define ARMPMU_EVT_64BIT 1 +/* Event uses a 47bit counter */ +#define ARMPMU_EVT_47BIT 2 #define HW_OP_UNSUPPORTED 0xFFFF #define C(_x) PERF_COUNT_HW_CACHE_##_x