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Sat, 22 Jan 2022 03:24:19 -0800 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH v2 1/4] dt-bindings: Add headers for Tegra234 I2C Date: Sat, 22 Jan 2022 16:53:24 +0530 Message-ID: <1642850607-20664-2-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> References: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1f13cda8-c4d7-4149-3b62-08d9dd99be08 X-MS-TrafficTypeDiagnostic: BY5PR12MB4244:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1186; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qfL5c121iUji5f8obuBbdscSb987g8QAZ3RgAABNFXyippvMTSFlgYztOpO37oq4QX7PpOe8APokghUdEVAdu6iKLC1i1zqV/rqQPKq61UGnphYEYuUXcr0uTwAoDtH7RZChOa0p6Q8DJJ4oGF84LszHradvrNUcmeBPLaZTnj0PQc5X1CK4CGtniS7vlMIIlgWFOZesch0+9DotkaHrvMI3nvxp1kaISEPQsMIu3ufNZbRAbM4ir5CZxUPBG0Wz2mzczU3ysZZpTUtR5lcuCzrXqEfHpCH/3szP0EvorQsaIEOef7Y0HYL5QxI5Zpl/SCYal4KzeH0J7T7gUwxy6T0vYiDuv4UnV29Ipv3ir5BB1dNl0bFX43ZsQurH+Wrvw3Sr7u8CfTMY2drUok7+soPS3+3Evn+yvlGnczY65/Nd60TMs+x2rffEVv1my2vySOKfiW+x7kUNNjJDIll0gjLCg0OtP4MEY6D4rxJkgPKRsDb+yIEp0l95I4E9PpZVo+KEbMZGrnhded3f1X+VjxsNHVJzvcOUk2naqqyO6yW5TtI8IJMT2q8HIKgInZqbo5NBs3uKcJc/TZoklm3op1TYm3F6OWEard0m36CDEf53TFcuNUW0oD+Zyvnmq/ZnKHNR/n/DXnyTbDjiCvGlW688vg+SnfL8ct2iJdR6InI24x4lUgWB5lnzvkKXAHvCSQUfaKrYCciJTdA1rxUNVnCrYDHusdtOl0Pd3jjGAZWD/23NRhAkgaIJc4U5B2ONpAouGiqVJ61E/1w3a2BLQwpDuxHwomov+hQnb3YAAovCwJ1CTso2Qyb7IZSjsoEEzXAmqSHJqD4YznNfPJkpGCpaOEy+LbtmzxvhoHHCD58= X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(36840700001)(40470700004)(46966006)(107886003)(2906002)(5660300002)(86362001)(8936002)(40460700003)(921005)(508600001)(26005)(70586007)(186003)(316002)(70206006)(7696005)(426003)(36756003)(356005)(47076005)(83380400001)(8676002)(110136005)(4326008)(2616005)(81166007)(336012)(6666004)(82310400004)(36860700001)(36900700001)(83996005)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2022 11:24:23.6487 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f13cda8-c4d7-4149-3b62-08d9dd99be08 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4244 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add dt-bindings header files for I2C controllers for Tegra234 Signed-off-by: Akhil R --- include/dt-bindings/clock/tegra234-clock.h | 19 +++++++++++++++++++ include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++ 2 files changed, 27 insertions(+) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 8d7e66e..5d05c19 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -30,5 +30,24 @@ #define TEGRA234_CLK_PLLC4 237U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ +#define TEGRA234_CLK_I2C1 48U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ +#define TEGRA234_CLK_I2C2 49U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ +#define TEGRA234_CLK_I2C3 50U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ +#define TEGRA234_CLK_I2C4 51U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ +#define TEGRA234_CLK_I2C6 52U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ +#define TEGRA234_CLK_I2C7 53U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ +#define TEGRA234_CLK_I2C8 54U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ +#define TEGRA234_CLK_I2C9 55U + +/** @brief PLLP clk output */ +#define TEGRA234_CLK_PLLP_OUT0 102U #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 50e13bc..e07e898 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -12,6 +12,14 @@ */ #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U +#define TEGRA234_RESET_I2C1 24U +#define TEGRA234_RESET_I2C2 29U +#define TEGRA234_RESET_I2C3 30U +#define TEGRA234_RESET_I2C4 31U +#define TEGRA234_RESET_I2C6 32U +#define TEGRA234_RESET_I2C7 33U +#define TEGRA234_RESET_I2C8 34U +#define TEGRA234_RESET_I2C9 35U /** @} */ From patchwork Sat Jan 22 11:23:25 2022 Content-Type: text/plain; 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Sat, 22 Jan 2022 03:24:29 -0800 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH v2 2/4] arm64: tegra: Add Tegra234 I2C devicetree nodes Date: Sat, 22 Jan 2022 16:53:25 +0530 Message-ID: <1642850607-20664-3-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> References: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 559eeb59-d76d-42e3-1540-08d9dd99c43a X-MS-TrafficTypeDiagnostic: DM6PR12MB5022:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1079; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZDyJPmlX95md9OwBtC0dBNFMuzDaMqtKLEzEAaQOickuWmvn+cADzu6x9oR6u31Wy/JpCrnvy0kAvY3AcGwGUBC8NMhq69iXSt3FVbyYx3jknVGe/l9mbXuyxAB/3SMjTkEC3s5e85coKAQHSQ5bGsdWH54188QTcqmNwLSoVlbQBTh2SbXpIfzA6MhYnK0GAabs6SsFTExIi4xZQFfDeKrM8V4nyxJCF9ua46duGWVBr5pmJrVxrAzjPBRzyP3/thC1T3uGUsImsC2xcSzetPaZ5ijfJu+gMadt7HHNS77FRg+xc2vgsUKrJncZFQgm63+j8YfJOwMahQ9zaHX1ElH91+nK5KDh8zhFAsCu79fmQFOmA1FUu7G3cPhUJL/d71g6UnFHzlmT5ER7T4hcDNog+Yb871LI0psYwzY6NLQCNaR6yN1AoNw1FILFzsD6Uz0sYrKbkWz1uq5nchMCjwmWAmdes94LWwGpmrJt3agl8x9bWuOi9W9oa39KBpu8Qx3CR3aEwATma90QSPZG9lIoQHwA6cawlyq7JgJPQLN78eNw8iu02l5PB9Je0RpXo5jHF3fj4vmNvwBYWUEOwCvk22X0YWzQezKgHer0s3SxiJZDX3TwAVH2GTL4xBuk1X6jMV1JHP4ZOnlD2+lGNGPCz0piLz3EJwo42bhbe9/e6p6u7CRmAwdQMmgxGRP6NS9oOeGMl9jAJjoI8JhPPj1a+UkrhTu77T44m9Irch0h53CAaz7Mtge8S11jB7ODxe2iu0l9SrLYmJFrppvb+bpxYXLhVArbGuzEbWeFaAhaAa+VVHJQa7IIXLdpoY/qVul/VJgZEgEqOs0QxEpXGgXUte4V7ApxwraofpZObzE= X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(40470700004)(46966006)(36840700001)(316002)(8936002)(508600001)(81166007)(336012)(70206006)(26005)(86362001)(6666004)(186003)(36756003)(426003)(40460700003)(110136005)(5660300002)(83380400001)(47076005)(36860700001)(921005)(82310400004)(4326008)(8676002)(7696005)(2616005)(356005)(70586007)(107886003)(2906002)(83996005)(2101003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2022 11:24:34.0574 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 559eeb59-d76d-42e3-1540-08d9dd99c43a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB5022 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add device tree nodes for Tegra234 I2C controllers Signed-off-by: Akhil R --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 121 +++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 6b6f1580..c686827 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -144,6 +144,96 @@ status = "disabled"; }; + gen1_i2c: i2c@3160000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3160000 0x100>; + status = "disabled"; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C1 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C1>; + reset-names = "i2c"; + }; + + cam_i2c: i2c@3180000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3180000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C3 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C3>; + reset-names = "i2c"; + }; + + dp_aux_ch1_i2c: i2c@3190000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3190000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C4 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C4>; + reset-names = "i2c"; + }; + + dp_aux_ch0_i2c: i2c@31b0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31b0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C6 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C6>; + reset-names = "i2c"; + }; + + dp_aux_ch2_i2c: i2c@31c0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31c0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C7 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C7>; + reset-names = "i2c"; + }; + + dp_aux_ch3_i2c: i2c@31e0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31e0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C9 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C9>; + reset-names = "i2c"; + }; + mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; @@ -212,6 +302,37 @@ #mbox-cells = <2>; }; + gen2_i2c: i2c@c240000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0xc240000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C2 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_I2C2>; + reset-names = "i2c"; + }; + + gen8_i2c: i2c@c250000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0xc250000 0x100>; + nvidia,hw-instance-id = <0x7>; + interrupts = ; + status = "disabled"; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C8 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_I2C8>; + reset-names = "i2c"; + }; + rtc@c2a0000 { compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; reg = <0x0c2a0000 0x10000>; From patchwork Sat Jan 22 11:23:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 534359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02C21C4332F for ; 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Sat, 22 Jan 2022 11:24:40 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Sat, 22 Jan 2022 03:24:40 -0800 Received: from kyarlagadda-linux.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.9 via Frontend Transport; Sat, 22 Jan 2022 03:24:37 -0800 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH v2 3/4] dt-bindings: Add headers for Tegra234 PWM Date: Sat, 22 Jan 2022 16:53:26 +0530 Message-ID: <1642850607-20664-4-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> References: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 78f82fc8-45fa-46cd-522c-08d9dd99c88a X-MS-TrafficTypeDiagnostic: MN2PR12MB3246:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1186; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(40470700004)(46966006)(36840700001)(40460700003)(336012)(36860700001)(70206006)(4326008)(70586007)(8936002)(508600001)(107886003)(36756003)(8676002)(86362001)(186003)(81166007)(5660300002)(26005)(83380400001)(2906002)(2616005)(356005)(921005)(47076005)(82310400004)(6666004)(7696005)(110136005)(426003)(316002)(36900700001)(2101003)(83996005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2022 11:24:41.2628 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 78f82fc8-45fa-46cd-522c-08d9dd99c88a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3246 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add dt-bindings header files for PWM of Tegra234 Signed-off-by: Akhil R --- include/dt-bindings/clock/tegra234-clock.h | 17 +++++++++++++++++ include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++ 2 files changed, 25 insertions(+) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 5d05c19..9d17309 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -50,4 +50,21 @@ /** @brief PLLP clk output */ #define TEGRA234_CLK_PLLP_OUT0 102U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ +#define TEGRA234_CLK_PWM1 105U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ +#define TEGRA234_CLK_PWM2 106U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ +#define TEGRA234_CLK_PWM3 107U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ +#define TEGRA234_CLK_PWM4 108U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ +#define TEGRA234_CLK_PWM5 109U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ +#define TEGRA234_CLK_PWM6 110U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ +#define TEGRA234_CLK_PWM7 111U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ +#define TEGRA234_CLK_PWM8 112U + #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index e07e898..288524f 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -20,6 +20,14 @@ #define TEGRA234_RESET_I2C7 33U #define TEGRA234_RESET_I2C8 34U #define TEGRA234_RESET_I2C9 35U +#define TEGRA234_RESET_PWM1 68U +#define TEGRA234_RESET_PWM2 69U +#define TEGRA234_RESET_PWM3 70U +#define TEGRA234_RESET_PWM4 71U +#define TEGRA234_RESET_PWM5 72U +#define TEGRA234_RESET_PWM6 73U +#define TEGRA234_RESET_PWM7 74U +#define TEGRA234_RESET_PWM8 75U /** @} */ From patchwork Sat Jan 22 11:23:27 2022 Content-Type: text/plain; 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Sat, 22 Jan 2022 03:24:44 -0800 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH v2 4/4] arm64: tegra: Add Tegra234 PWM devicetree nodes Date: Sat, 22 Jan 2022 16:53:27 +0530 Message-ID: <1642850607-20664-5-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> References: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6b94ca34-6cee-4f86-5090-08d9dd99cd56 X-MS-TrafficTypeDiagnostic: DM6PR12MB3227:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1079; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sQLhvUA9/Rlzkx48uS+GGnnFG7VB0yL5oeHiw/tu0T18z4CjHH/PeVapMmJ4b1i7dTranqHKZ8A79EXZk7t8VvS93I9jy6zxVZ2p5DLzpatDcBqFmFogAj7xsJv5rqfv5H7lGmioUfkSxw4mJ5cEV4xFx6hdZfydnJuKr55z5IAdKgGptrgadcX9xoa0Atm/O1kobUcICrnCB1TAywADfs8VycmqEfBENR6DVHgowZDn5EfJllW1+ZDejp3tLWEVpGVsqKMAv54S4YLRWlDT4qL+UWH/2AbUQH6WY4hXnYAWECo5qsIAN7kETjuS+p8lObbnWLa+DqzrLW05mRj6mUNeQeVi1NKFzh4pOUr7TpKjN48/82RuH4n4KDL+KB9UiQNxmExp5je534xWsCJLh4uyVfHFz4Zfp3My/5usMCoQiKiFEUvxsZWVYNfEgu+5CLieB0CohfdwKY4I6iOz80fZLpU5RZVEUrg6yX25AIgg+8JAEbXbEovrx77wbo8iZ4oIZvoQ/cJlT7Hs8E61NF3Swll2FZYty23LXxb0YxT+d4gxwc/rnZOYleQYweAd88C0Mn88qtMJFSSHwDOkxZj3v5jgIz0hlIzYqknrMP1+x1W8u23W6ooALDjyUPx+kcAn+e20ztt3zHNnWV9cqWaNQc6VaxrHxdoN4lpr15KGdPm0fezCEK7QChw8FORHopBHZdUIY0PM8FEKpY5OLse4u/ELxm31iTuvC32UvvlIG2AfLVDli/cnaEAZw8jY+/4ieatyXbKAhtlR6IVDoVC4s8+wQvBnZGxqETjgQPSM1kZN8D+7bmtuou6/gQPOGrPXn7u96FKe01AaabLcqDPOODlMFo44o8TiYhJvS3tdX8sgOm74e4hs9bo+WElA X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(40470700004)(36840700001)(46966006)(4744005)(70206006)(107886003)(5660300002)(81166007)(4326008)(47076005)(7696005)(921005)(70586007)(40460700003)(6666004)(426003)(2906002)(36756003)(508600001)(336012)(8676002)(2616005)(82310400004)(356005)(110136005)(316002)(8936002)(26005)(36860700001)(86362001)(186003)(83380400001)(36900700001)(83996005)(2101003)(357404004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2022 11:24:49.3106 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b94ca34-6cee-4f86-5090-08d9dd99cd56 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3227 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add device tree nodes for Tegra234 PWM Signed-off-by: Akhil R --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index c686827..cbebf1e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -234,6 +234,18 @@ reset-names = "i2c"; }; + pwm1: pwm@3280000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x3280000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM1>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM1>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>;