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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.03.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:03:51 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 01/15] dt-bindings: clock: split qcom,gcc.yaml to common and specific schema Date: Fri, 21 Jan 2022 22:03:26 +0100 Message-Id: <20220121210340.32362-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Split qcom,gcc.yaml to common and specific schema to use it as a template for schema that needs to use the gcc bindings and require to add additional bindings. Signed-off-by: Ansuel Smith --- .../bindings/clock/qcom,gcc-common.yaml | 42 +++++++++++++++++++ .../devicetree/bindings/clock/qcom,gcc.yaml | 25 ++--------- 2 files changed, 46 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-common.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-common.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-common.yaml new file mode 100644 index 000000000000..ea1dd94d8bf1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-common.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding Common Bindings + +maintainers: + - Stephen Boyd + - Taniya Das + +description: | + Common bindings for Qualcomm global clock control module which supports + the clocks, resets and power domains. + +properties: + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index f66d703bd913..73e3ff4979c6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -34,6 +34,9 @@ description: | - dt-bindings/reset/qcom,gcc-mdm9615.h - dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660) +allOf: + - $ref: "qcom,gcc-common.yaml#" + properties: compatible: enum: @@ -55,30 +58,10 @@ properties: - qcom,gcc-sdm630 - qcom,gcc-sdm660 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +unevaluatedProperties: false examples: # Example for GCC for MSM8960: From patchwork Fri Jan 21 21:03:27 2022 Content-Type: text/plain; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.03.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:03:52 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation Date: Fri, 21 Jan 2022 22:03:27 +0100 Message-Id: <20220121210340.32362-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc-common.yaml as a template and remove the compatible from qcom,gcc.yaml Signed-off-by: Ansuel Smith --- .../bindings/clock/qcom,gcc-apq8064.yaml | 29 +++++-------------- .../devicetree/bindings/clock/qcom,gcc.yaml | 3 -- 2 files changed, 7 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml index 8e2eac6cbfb9..f31a260176e5 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml @@ -6,6 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global Clock & Reset Controller Binding for APQ8064 +allOf: + - $ref: qcom,gcc-common.yaml# + maintainers: - Stephen Boyd - Taniya Das @@ -17,22 +20,12 @@ description: | See also: - dt-bindings/clock/qcom,gcc-msm8960.h - dt-bindings/reset/qcom,gcc-msm8960.h + - dt-bindings/clock/qcom,gcc-apq8084.h + - dt-bindings/reset/qcom,gcc-apq8084.h properties: compatible: - const: qcom,gcc-apq8064 - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 + const: qcom,gcc-apq8084 nvmem-cells: minItems: 1 @@ -53,21 +46,13 @@ properties: '#thermal-sensor-cells': const: 1 - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' - nvmem-cells - nvmem-cell-names - '#thermal-sensor-cells' -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index 73e3ff4979c6..04745bb407be 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -15,8 +15,6 @@ description: | power domains. See also: - - dt-bindings/clock/qcom,gcc-apq8084.h - - dt-bindings/reset/qcom,gcc-apq8084.h - dt-bindings/clock/qcom,gcc-ipq4019.h - dt-bindings/clock/qcom,gcc-ipq6018.h - dt-bindings/reset/qcom,gcc-ipq6018.h @@ -40,7 +38,6 @@ allOf: properties: compatible: enum: - - qcom,gcc-apq8084 - qcom,gcc-ipq4019 - qcom,gcc-ipq6018 - qcom,gcc-ipq8064 From patchwork Fri Jan 21 21:03:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533881 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBC08C4332F for ; Fri, 21 Jan 2022 21:03:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232868AbiAUVD5 (ORCPT ); Fri, 21 Jan 2022 16:03:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232901AbiAUVDz (ORCPT ); Fri, 21 Jan 2022 16:03:55 -0500 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47D14C06173B; Fri, 21 Jan 2022 13:03:55 -0800 (PST) Received: by mail-ej1-x62e.google.com with SMTP id p15so3327975ejc.7; Fri, 21 Jan 2022 13:03:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Fu9s/T6wtJsMWKi3wycsF6L8ty8BEzxmIHzs5XytTf8=; b=UX1jwwY+pGihtIh1kvKPVw/ZdUZcZfpyTR8rb75lRd/CsbyuSsUsXPC5YcfBfdQ2cm fGYY9yABCspA71NvyiKsXmWzlD778+1N9pGSQD86BbunEQshH1r5JwFThJKkauR0tBsK iUIx2homGQoZ26ESF0nXz/oq2KiqQDC85FxlTthJNCRuHhDWgKqAGha3YmPwSDV8PsL5 fkwCek8Fv18unDLcuD05rz9fch+NW01p6+PjfeCTf/rWg/vg0SVBRrbjKxZU3V4UkT89 3EEF1IVUfrCOKNhfLmOtvM511f2CBv+K+qiz+zX+KSUzuwJKeVxMB0onivBZy/ITW4H1 ooFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Fu9s/T6wtJsMWKi3wycsF6L8ty8BEzxmIHzs5XytTf8=; b=d7vptPHc+cpDDr6o9u7dDWI4pnVsFCf3e4F0iOhpioNt0fTzu9799dmoeitRXv4qRt zBq8WdZx8fGy3tPthJQLMWdZijVTwAbqT7UOzt23z8QJvjVrvB/CdJRtzrIcvbkZCDoF x5TRZfxtX7gS+xDuF0pMLSU4RyGfiTGVeknloxjwubCXhG9xPAdBH7smOv7079dyKSBh MzRhhwdpgcS1z3ZR3UkQuvyG5RTj7D515J3+KiNllf1n/R1SbnuwF2q5kgs99IGpe2au o+bNISgA+8+xKHDAI9Ij/3jnAZfGqK5G2jiFEUWvPWAXnW+TQp95rS49g8j3/daG71lP Swlw== X-Gm-Message-State: AOAM533CWrEIpMKKdlMHIlsF4BWXuJvXj0dwYZE9Kg/WEUtvO4Cxx/Z9 g/9DamqXRZOPQboJini6NOqg1NwQFWY= X-Google-Smtp-Source: ABdhPJw1A5nL8FIEUzzZCiKPVR3xb5LxKg5hyb/8bEESHHwMO8XOnI8lLT0eysypFXe4lkb+z/UpOQ== X-Received: by 2002:a17:906:65c8:: with SMTP id z8mr4981284ejn.727.1642799033758; Fri, 21 Jan 2022 13:03:53 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.03.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:03:53 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 03/15] dt-bindings: clock: Document qcom,gcc-ipq8064 binding Date: Fri, 21 Jan 2022 22:03:28 +0100 Message-Id: <20220121210340.32362-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source clocks. The gcc node is also used by the tsens driver, already documented, to get the calib nvmem cells and the base reg from gcc. Use qcom,gcc-common.yaml as a template and remove the compatible from generic qcom,gcc.yaml Signed-off-by: Ansuel Smith --- .../bindings/clock/qcom,gcc-ipq8064.yaml | 76 +++++++++++++++++++ .../devicetree/bindings/clock/qcom,gcc.yaml | 3 - 2 files changed, 76 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml new file mode 100644 index 000000000000..fac9c10eba0b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064 + +allOf: + - $ref: qcom,gcc-common.yaml# + +maintainers: + - Ansuel Smith + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on IPQ8064. + + See also: + - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) + - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) + +properties: + compatible: + items: + - const: qcom,gcc-ipq8064 + - const: syscon + + clocks: + items: + - description: PXO source + - description: CXO source + + clock-names: + items: + - const: pxo + - const: cxo + + thermal-sensor: + type: object + + allOf: + - $ref: /schemas/thermal/qcom-tsens.yaml# + +required: + - compatible + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064", "syscon"; + reg = <0x00900000 0x4000>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + tsens: thermal-sensor { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index 04745bb407be..98057ed9bfc1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -18,8 +18,6 @@ description: | - dt-bindings/clock/qcom,gcc-ipq4019.h - dt-bindings/clock/qcom,gcc-ipq6018.h - dt-bindings/reset/qcom,gcc-ipq6018.h - - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) - - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) - dt-bindings/clock/qcom,gcc-msm8939.h - dt-bindings/clock/qcom,gcc-msm8953.h - dt-bindings/reset/qcom,gcc-msm8939.h @@ -40,7 +38,6 @@ properties: enum: - qcom,gcc-ipq4019 - qcom,gcc-ipq6018 - - qcom,gcc-ipq8064 - qcom,gcc-mdm9607 - qcom,gcc-msm8226 - qcom,gcc-msm8660 From patchwork Fri Jan 21 21:03:29 2022 Content-Type: text/plain; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.03.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:03:54 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 04/15] drivers: clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 Date: Fri, 21 Jan 2022 22:03:29 +0100 Message-Id: <20220121210340.32362-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Parent gcc_pxo_pll8_pll0 had the parent definition and parent map swapped. Fix this naming error. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index d6b7adb4be38..34cddf461dba 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] = { "pll3", }; -static const struct parent_map gcc_pxo_pll8_pll0[] = { +static const struct parent_map gcc_pxo_pll8_pll0_map[] = { { P_PXO, 0 }, { P_PLL8, 3 }, { P_PLL0, 2 } }; -static const char * const gcc_pxo_pll8_pll0_map[] = { +static const char * const gcc_pxo_pll8_pll0[] = { "pxo", "pll8_vote", "pll0_vote", @@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb30_master, .clkr = { @@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb30_utmi, .clkr = { @@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb, .clkr = { @@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb, .clkr = { @@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, From patchwork Fri Jan 21 21:03:30 2022 Content-Type: text/plain; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.03.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:03:55 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 05/15] drivers: clk: qcom: gcc-ipq806x: convert parent_names to parent_data Date: Fri, 21 Jan 2022 22:03:30 +0100 Message-Id: <20220121210340.32362-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert parent_names to parent_data to modernize the driver. Where possible use parent_hws directly. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 286 ++++++++++++++++++++------------- 1 file changed, 173 insertions(+), 113 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 34cddf461dba..828383c30322 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -25,6 +25,10 @@ #include "clk-hfpll.h" #include "reset.h" +static const struct clk_parent_data gcc_pxo[] = { + { .fw_name = "pxo" }, +}; + static struct clk_pll pll0 = { .l_reg = 0x30c4, .m_reg = 0x30c8, @@ -35,7 +39,7 @@ static struct clk_pll pll0 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll0", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -46,7 +50,9 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_names = (const char *[]){ "pll0" }, + .parent_hws = (const struct clk_hw*[]){ + &pll0.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -62,7 +68,7 @@ static struct clk_pll pll3 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll3", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -89,7 +95,7 @@ static struct clk_pll pll8 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll8", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -100,7 +106,9 @@ static struct clk_regmap pll8_vote = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "pll8_vote", - .parent_names = (const char *[]){ "pll8" }, + .parent_hws = (const struct clk_hw*[]){ + &pll8.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -123,7 +131,7 @@ static struct hfpll_data hfpll0_data = { static struct clk_hfpll hfpll0 = { .d = &hfpll0_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .name = "hfpll0", .ops = &clk_ops_hfpll, @@ -149,7 +157,7 @@ static struct hfpll_data hfpll1_data = { static struct clk_hfpll hfpll1 = { .d = &hfpll1_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .name = "hfpll1", .ops = &clk_ops_hfpll, @@ -175,7 +183,7 @@ static struct hfpll_data hfpll_l2_data = { static struct clk_hfpll hfpll_l2 = { .d = &hfpll_l2_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .name = "hfpll_l2", .ops = &clk_ops_hfpll, @@ -194,7 +202,7 @@ static struct clk_pll pll14 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll14", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -205,7 +213,9 @@ static struct clk_regmap pll14_vote = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "pll14_vote", - .parent_names = (const char *[]){ "pll14" }, + .parent_hws = (const struct clk_hw*[]){ + &pll14.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -238,7 +248,7 @@ static struct clk_pll pll18 = { .freq_tbl = pll18_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "pll18", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -259,9 +269,9 @@ static const struct parent_map gcc_pxo_pll8_map[] = { { P_PLL8, 3 } }; -static const char * const gcc_pxo_pll8[] = { - "pxo", - "pll8_vote", +static const struct clk_parent_data gcc_pxo_pll8[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, }; static const struct parent_map gcc_pxo_pll8_cxo_map[] = { @@ -270,10 +280,10 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = { { P_CXO, 5 } }; -static const char * const gcc_pxo_pll8_cxo[] = { - "pxo", - "pll8_vote", - "cxo", +static const struct clk_parent_data gcc_pxo_pll8_cxo[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .fw_name = "cxo" }, }; static const struct parent_map gcc_pxo_pll3_map[] = { @@ -286,9 +296,9 @@ static const struct parent_map gcc_pxo_pll3_sata_map[] = { { P_PLL3, 6 } }; -static const char * const gcc_pxo_pll3[] = { - "pxo", - "pll3", +static const struct clk_parent_data gcc_pxo_pll3[] = { + { .fw_name = "pxo" }, + { .hw = &pll3.clkr.hw }, }; static const struct parent_map gcc_pxo_pll8_pll0_map[] = { @@ -297,10 +307,10 @@ static const struct parent_map gcc_pxo_pll8_pll0_map[] = { { P_PLL0, 2 } }; -static const char * const gcc_pxo_pll8_pll0[] = { - "pxo", - "pll8_vote", - "pll0_vote", +static const struct clk_parent_data gcc_pxo_pll8_pll0[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, }; static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { @@ -311,12 +321,12 @@ static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { { P_PLL18, 1 } }; -static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = { - "pxo", - "pll8_vote", - "pll0_vote", - "pll14", - "pll18", +static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, }; static struct freq_tbl clk_tbl_gsbi_uart[] = { @@ -362,7 +372,7 @@ static struct clk_rcg gsbi1_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -378,8 +388,8 @@ static struct clk_branch gsbi1_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_clk", - .parent_names = (const char *[]){ - "gsbi1_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi1_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -413,7 +423,7 @@ static struct clk_rcg gsbi2_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -429,8 +439,8 @@ static struct clk_branch gsbi2_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_clk", - .parent_names = (const char *[]){ - "gsbi2_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi2_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -464,7 +474,7 @@ static struct clk_rcg gsbi4_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -480,8 +490,8 @@ static struct clk_branch gsbi4_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_clk", - .parent_names = (const char *[]){ - "gsbi4_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi4_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -515,7 +525,7 @@ static struct clk_rcg gsbi5_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -531,8 +541,8 @@ static struct clk_branch gsbi5_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_clk", - .parent_names = (const char *[]){ - "gsbi5_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi5_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -566,7 +576,7 @@ static struct clk_rcg gsbi6_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -582,8 +592,8 @@ static struct clk_branch gsbi6_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_clk", - .parent_names = (const char *[]){ - "gsbi6_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi6_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -617,7 +627,7 @@ static struct clk_rcg gsbi7_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -633,8 +643,8 @@ static struct clk_branch gsbi7_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_clk", - .parent_names = (const char *[]){ - "gsbi7_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi7_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -681,7 +691,7 @@ static struct clk_rcg gsbi1_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -697,7 +707,9 @@ static struct clk_branch gsbi1_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_clk", - .parent_names = (const char *[]){ "gsbi1_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi1_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -730,7 +742,7 @@ static struct clk_rcg gsbi2_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -746,7 +758,9 @@ static struct clk_branch gsbi2_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_clk", - .parent_names = (const char *[]){ "gsbi2_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi2_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -779,7 +793,7 @@ static struct clk_rcg gsbi4_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -795,7 +809,9 @@ static struct clk_branch gsbi4_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_clk", - .parent_names = (const char *[]){ "gsbi4_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi4_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -828,7 +844,7 @@ static struct clk_rcg gsbi5_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -844,7 +860,9 @@ static struct clk_branch gsbi5_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_clk", - .parent_names = (const char *[]){ "gsbi5_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi5_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -877,7 +895,7 @@ static struct clk_rcg gsbi6_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -893,7 +911,9 @@ static struct clk_branch gsbi6_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_clk", - .parent_names = (const char *[]){ "gsbi6_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi6_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -926,7 +946,7 @@ static struct clk_rcg gsbi7_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -942,7 +962,9 @@ static struct clk_branch gsbi7_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_clk", - .parent_names = (const char *[]){ "gsbi7_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi7_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1076,7 +1098,7 @@ static struct clk_rcg gp0_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp0_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -1092,7 +1114,9 @@ static struct clk_branch gp0_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp0_clk", - .parent_names = (const char *[]){ "gp0_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp0_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1125,7 +1149,7 @@ static struct clk_rcg gp1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp1_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1141,7 +1165,9 @@ static struct clk_branch gp1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp1_clk", - .parent_names = (const char *[]){ "gp1_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1174,7 +1200,7 @@ static struct clk_rcg gp2_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp2_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1190,7 +1216,9 @@ static struct clk_branch gp2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp2_clk", - .parent_names = (const char *[]){ "gp2_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp2_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1228,7 +1256,7 @@ static struct clk_rcg prng_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "prng_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1244,7 +1272,9 @@ static struct clk_branch prng_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "prng_clk", - .parent_names = (const char *[]){ "prng_src" }, + .parent_hws = (const struct clk_hw*[]){ + &prng_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -1290,7 +1320,7 @@ static struct clk_rcg sdc1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc1_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1305,7 +1335,9 @@ static struct clk_branch sdc1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc1_clk", - .parent_names = (const char *[]){ "sdc1_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdc1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1338,7 +1370,7 @@ static struct clk_rcg sdc3_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc3_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1353,7 +1385,9 @@ static struct clk_branch sdc3_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc3_clk", - .parent_names = (const char *[]){ "sdc3_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdc3_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1421,7 +1455,7 @@ static struct clk_rcg tsif_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "tsif_ref_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1436,7 +1470,9 @@ static struct clk_branch tsif_ref_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk", - .parent_names = (const char *[]){ "tsif_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &tsif_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1583,7 +1619,7 @@ static struct clk_rcg pcie_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1599,7 +1635,9 @@ static struct clk_branch pcie_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src_clk", - .parent_names = (const char *[]){ "pcie_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1675,7 +1713,7 @@ static struct clk_rcg pcie1_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1691,7 +1729,9 @@ static struct clk_branch pcie1_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src_clk", - .parent_names = (const char *[]){ "pcie1_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie1_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1767,7 +1807,7 @@ static struct clk_rcg pcie2_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1783,7 +1823,9 @@ static struct clk_branch pcie2_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src_clk", - .parent_names = (const char *[]){ "pcie2_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie2_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1864,7 +1906,7 @@ static struct clk_rcg sata_ref_src = { .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "sata_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1880,7 +1922,9 @@ static struct clk_branch sata_rxoob_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_rxoob_clk", - .parent_names = (const char *[]){ "sata_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sata_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1896,7 +1940,9 @@ static struct clk_branch sata_pmalive_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_pmalive_clk", - .parent_names = (const char *[]){ "sata_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sata_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1912,7 +1958,7 @@ static struct clk_branch sata_phy_ref_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_phy_ref_clk", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -2001,7 +2047,7 @@ static struct clk_rcg usb30_master_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2017,7 +2063,9 @@ static struct clk_branch usb30_0_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_0_branch_clk", - .parent_names = (const char *[]){ "usb30_master_ref_src", }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2033,7 +2081,9 @@ static struct clk_branch usb30_1_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_1_branch_clk", - .parent_names = (const char *[]){ "usb30_master_ref_src", }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2071,7 +2121,7 @@ static struct clk_rcg usb30_utmi_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2087,7 +2137,9 @@ static struct clk_branch usb30_0_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_0_utmi_clk_ctl", - .parent_names = (const char *[]){ "usb30_utmi_clk", }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_utmi_clk.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2103,7 +2155,9 @@ static struct clk_branch usb30_1_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_1_utmi_clk_ctl", - .parent_names = (const char *[]){ "usb30_utmi_clk", }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_utmi_clk.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2141,7 +2195,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2157,7 +2211,9 @@ static struct clk_branch usb_hs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_clk", - .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb_hs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2205,7 +2261,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2221,7 +2277,9 @@ static struct clk_branch usb_fs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_clk", - .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, + .parent_hws = (const struct clk_hw*[]){ + &usb_fs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2237,7 +2295,9 @@ static struct clk_branch usb_fs1_sys_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_sys_clk", - .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, + .parent_hws = (const struct clk_hw*[]){ + &usb_fs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2337,7 +2397,7 @@ static struct clk_dyn_rcg gmac_core1_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core1_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2354,8 +2414,8 @@ static struct clk_branch gmac_core1_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core1_clk", - .parent_names = (const char *[]){ - "gmac_core1_src", + .parent_hws = (const struct clk_hw*[]){ + &gmac_core1_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2409,7 +2469,7 @@ static struct clk_dyn_rcg gmac_core2_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core2_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2426,8 +2486,8 @@ static struct clk_branch gmac_core2_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core2_clk", - .parent_names = (const char *[]){ - "gmac_core2_src", + .parent_hws = (const struct clk_hw*[]){ + &gmac_core2_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2481,7 +2541,7 @@ static struct clk_dyn_rcg gmac_core3_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core3_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2498,8 +2558,8 @@ static struct clk_branch gmac_core3_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core3_clk", - .parent_names = (const char *[]){ - "gmac_core3_src", + .parent_hws = (const struct clk_hw*[]){ + &gmac_core3_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2553,7 +2613,7 @@ static struct clk_dyn_rcg gmac_core4_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core4_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2570,8 +2630,8 @@ static struct clk_branch gmac_core4_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core4_clk", - .parent_names = (const char *[]){ - "gmac_core4_src", + .parent_hws = (const struct clk_hw*[]){ + &gmac_core4_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2613,7 +2673,7 @@ static struct clk_dyn_rcg nss_tcm_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "nss_tcm_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2628,8 +2688,8 @@ static struct clk_branch nss_tcm_clk = { .enable_mask = BIT(6) | BIT(4), .hw.init = &(struct clk_init_data){ .name = "nss_tcm_clk", - .parent_names = (const char *[]){ - "nss_tcm_src", + .parent_hws = (const struct clk_hw*[]){ + &nss_tcm_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2691,7 +2751,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "ubi32_core1_src_clk", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, @@ -2744,7 +2804,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "ubi32_core2_src_clk", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, From patchwork Fri Jan 21 21:03:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533879 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDEB8C4332F for ; Fri, 21 Jan 2022 21:04:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233114AbiAUVEE (ORCPT ); Fri, 21 Jan 2022 16:04:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232585AbiAUVD7 (ORCPT ); Fri, 21 Jan 2022 16:03:59 -0500 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D19ADC06173B; Fri, 21 Jan 2022 13:03:58 -0800 (PST) Received: by mail-ej1-x635.google.com with SMTP id o12so3328617eju.13; Fri, 21 Jan 2022 13:03:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uhs8yO3Tw+6wvqO+3KXCFZjOTAYX1wXl4HfqPcifPzU=; b=UgK2QxT8FAJo5/T3BnBuehFUGi7syDgsm7KABs7+SBvr/3UBDE/s2V59RtGvvH2F5G ZsQUftBD+h+bPchPTsj81fa9QGy96Y7kC2YdH2n7TbknX3eqUwkf6vr0kgrNNF9WQlgk HLqiHbddQt0ve9BxgxWVvBlxs2UKzeMNbv54OICOMdP/WWfjMODf288xlvEXwNqaUH3Q NfsZkWlVVUvlOWHASnWlsSNXxDjzz788B742PUCCSrFZMvpTL5FYJjFiusQ/LKLjYDlH KZoPov+AWMAvn2Q6QE5zETjrfvbBAIAHGFmSx6Qu0+/hw7xpeuXM0tyh1yyR3+szFTdk 4DKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uhs8yO3Tw+6wvqO+3KXCFZjOTAYX1wXl4HfqPcifPzU=; b=sjGTYprIscfFh79CVKULpDTf4xafHz28SkhmPh2KrhKGjsuoncmjrF8dw7kC6juvVd Ldk9icRPpjHZa4ICyxPThJm3GbT23LApgw7C9dUMgl0YXmw4uQLpoT3qhkLH7WStJZ0Y eYypJyHIXB2b5wCcQqsFqZ4kb1XVfLk37EJLp6igS9roq9bJmg36AtLRavrdLlLz40Br nfvzSdJB1npOaE3rXknPQOZqlXbVPtDElKnXU3vwC6sX6b7oWIh8C/ctDKLORBcDAdKJ scODLXhUTvdNAcL6VmHlcR29VV+vqYQJYLrkxSF02LBqgDvY0Za4BXt/5ntI4O5QvVgY YuVQ== X-Gm-Message-State: AOAM531QS9iOHFjDZEzVXCFELjwSoYovPmLBvkkKaUuGENlHY0yySGVK V4UKo7POxfCxzpAw19GSY1c= X-Google-Smtp-Source: ABdhPJxJ+QayySQmraYxX7ss2mQNVNQLcLfOCWAAP1bx7/XJlgGFpMM2aT1OG+GaNq7+4UA65Vb/5Q== X-Received: by 2002:a17:907:7e85:: with SMTP id qb5mr476450ejc.557.1642799037255; Fri, 21 Jan 2022 13:03:57 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.03.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:03:56 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 06/15] drivers: clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents Date: Fri, 21 Jan 2022 22:03:31 +0100 Message-Id: <20220121210340.32362-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++----------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 828383c30322..f6db7247835e 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -373,7 +373,7 @@ static struct clk_rcg gsbi1_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -424,7 +424,7 @@ static struct clk_rcg gsbi2_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -475,7 +475,7 @@ static struct clk_rcg gsbi4_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -526,7 +526,7 @@ static struct clk_rcg gsbi5_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -577,7 +577,7 @@ static struct clk_rcg gsbi6_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -628,7 +628,7 @@ static struct clk_rcg gsbi7_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -692,7 +692,7 @@ static struct clk_rcg gsbi1_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -743,7 +743,7 @@ static struct clk_rcg gsbi2_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -794,7 +794,7 @@ static struct clk_rcg gsbi4_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -845,7 +845,7 @@ static struct clk_rcg gsbi5_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -896,7 +896,7 @@ static struct clk_rcg gsbi6_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -947,7 +947,7 @@ static struct clk_rcg gsbi7_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1099,7 +1099,7 @@ static struct clk_rcg gp0_src = { .hw.init = &(struct clk_init_data){ .name = "gp0_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1150,7 +1150,7 @@ static struct clk_rcg gp1_src = { .hw.init = &(struct clk_init_data){ .name = "gp1_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1201,7 +1201,7 @@ static struct clk_rcg gp2_src = { .hw.init = &(struct clk_init_data){ .name = "gp2_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1257,7 +1257,7 @@ static struct clk_rcg prng_src = { .hw.init = &(struct clk_init_data){ .name = "prng_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, }, @@ -1321,7 +1321,7 @@ static struct clk_rcg sdc1_src = { .hw.init = &(struct clk_init_data){ .name = "sdc1_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1371,7 +1371,7 @@ static struct clk_rcg sdc3_src = { .hw.init = &(struct clk_init_data){ .name = "sdc3_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1456,7 +1456,7 @@ static struct clk_rcg tsif_ref_src = { .hw.init = &(struct clk_init_data){ .name = "tsif_ref_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1620,7 +1620,7 @@ static struct clk_rcg pcie_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1714,7 +1714,7 @@ static struct clk_rcg pcie1_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1808,7 +1808,7 @@ static struct clk_rcg pcie2_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1907,7 +1907,7 @@ static struct clk_rcg sata_ref_src = { .hw.init = &(struct clk_init_data){ .name = "sata_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2048,7 +2048,7 @@ static struct clk_rcg usb30_master_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2122,7 +2122,7 @@ static struct clk_rcg usb30_utmi_clk = { .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2196,7 +2196,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2262,7 +2262,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2398,7 +2398,7 @@ static struct clk_dyn_rcg gmac_core1_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core1_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2470,7 +2470,7 @@ static struct clk_dyn_rcg gmac_core2_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core2_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2542,7 +2542,7 @@ static struct clk_dyn_rcg gmac_core3_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core3_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2614,7 +2614,7 @@ static struct clk_dyn_rcg gmac_core4_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core4_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2674,7 +2674,7 @@ static struct clk_dyn_rcg nss_tcm_src = { .hw.init = &(struct clk_init_data){ .name = "nss_tcm_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2752,7 +2752,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = { .hw.init = &(struct clk_init_data){ .name = "ubi32_core1_src_clk", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, @@ -2805,7 +2805,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { .hw.init = &(struct clk_init_data){ .name = "ubi32_core2_src_clk", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, From patchwork Fri Jan 21 21:03:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533880 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63B17C4167E for ; Fri, 21 Jan 2022 21:04:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233289AbiAUVEF (ORCPT ); Fri, 21 Jan 2022 16:04:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233204AbiAUVEA (ORCPT ); Fri, 21 Jan 2022 16:04:00 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFA5FC061749; Fri, 21 Jan 2022 13:03:59 -0800 (PST) Received: by mail-ed1-x52f.google.com with SMTP id a18so44753353edj.7; Fri, 21 Jan 2022 13:03:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=RtUb0uNm8GCwaxKxVgq9cIPVLkXV4oSCeOPZFznLHNM=; b=AFbGQf7jDc5FFQyPVtJ9HIzjjCGEWxCvoFKNDaXDUx0oNK31FGeMGxt6/PS1Oz2deV nGtiUcyiKyI/RNg3uToMBrhtH3JPNZHfCCwiAPuqLivHDdc5prl2+YQ2ttCpCAyWqb4J lyMIXiwV7ognLAjZLnDPjzAKz03U316dRbTPr4EwpM/SAX4MVMRgEBJ+QDIIWHpKCzPa +48vV2fOMHf2KCOMLy+s3yuY84xukpzt64Ys1b6v+n8FclxesfdM6oG6mExT+jPkSle0 MpCNKDrMdylJKTkJA/tW0EyfpcHY1nQhhpeQ4LVvYbCX4XS9TWOLnf5q28bQmMOxxb+J vbvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RtUb0uNm8GCwaxKxVgq9cIPVLkXV4oSCeOPZFznLHNM=; b=DduzpR9ycgK+dFYs5g9gZJXFpyBZP7vMO7GHrSB08Gi+5Pz0NdNlSyNYWgqwb9sAgs b/2sB2E0MMPKUFlRF0ZBCkt+i8l/qqRdaelYsze74wBTNc6tdRqJr3Pgae1V7kZmVMcX 62jasIcIDKRGuOfimn9vBIh0JdoHDXBSuZxfU8ooxOP1MaiAB9pLz3SvFmywjY5nlUqO oLO3OuDLHmeDEqSEB3h2uxeOU6pXXalt0Hj7ESI1qysnEP3VrmwZ4hGWXpDHxhVY+ZDf 21esN5xS/uc9IrWLJ+3JI9kAv+FVOuKz/ig9fMl040kc9URx/i1ZKcenGXYVeGfIjHpP ZD2A== X-Gm-Message-State: AOAM5317V5hYKVk7zZqdBfiAJ4SAIoS44MfVvDioklX6Pv3GQ8/rMe0l mCtaMA6jGg/SaFlNxBeeIdE= X-Google-Smtp-Source: ABdhPJzkz6Y0i6kHjYIL8msgv2r16C9YqtFHMuJBumIgeEN/m29hBALrc407O/kQlA3gD9pdTRpQ5w== X-Received: by 2002:a50:9e0f:: with SMTP id z15mr5861386ede.278.1642799038353; Fri, 21 Jan 2022 13:03:58 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.03.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:03:57 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 07/15] drivers: clk: qcom: gcc-ipq806x: drop hardcoded pxo and cxo source clk Date: Fri, 21 Jan 2022 22:03:32 +0100 Message-Id: <20220121210340.32362-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We now define these clk in dts. Drop pxo and cxo hardcoded in the gcc probe function. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index f6db7247835e..a4bf78fe8678 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -3119,23 +3119,14 @@ MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table); static int gcc_ipq806x_probe(struct platform_device *pdev) { - struct device *dev = &pdev->dev; struct regmap *regmap; int ret; - ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); - if (ret) - return ret; - - ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); - if (ret) - return ret; - ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); if (ret) return ret; - regmap = dev_get_regmap(dev, NULL); + regmap = dev_get_regmap(&pdev->dev, NULL); if (!regmap) return -ENODEV; From patchwork Fri Jan 21 21:03:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533878 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A838DC43219 for ; Fri, 21 Jan 2022 21:04:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233240AbiAUVEF (ORCPT ); Fri, 21 Jan 2022 16:04:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233244AbiAUVEB (ORCPT ); Fri, 21 Jan 2022 16:04:01 -0500 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E927EC06173B; Fri, 21 Jan 2022 13:04:00 -0800 (PST) Received: by mail-ej1-x633.google.com with SMTP id s13so3332148ejy.3; Fri, 21 Jan 2022 13:04:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cBE+j0nomJ1s8ZdluzXzBh2EPO3NhAaZtGzkoFt0ias=; b=p+OEMoYjp1wmAlYEkkuigWlBg7Zy4CMhAJLn++e5Hk/NRY90CvWuEojecN5xOJFbIs EzIwoVoBO2cIMxGoWe08hVc4yAqAgq2eQLzWiRzQIqNz9kkp3FJ1X3/k94wmBbc5IXuc mWk8dlf5siCFsfN1kp19oCc9jM7+y03nxZcxuXI6nDFkQ+QSwWQ1WxJN2Jffhp1KVsqt hw+cAWqwRr1m1P3eVvsfaS+FXzx1j7uKMFPvAk0Euc38g4DQkS7ddYYwvAhgPolIaaku LsYWldCsW98a48tNTAgfN5GhuCxRpgIOfARhiUTnPoFBFTJVBC3qdHsPNFUi0SAH1XTU ryCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cBE+j0nomJ1s8ZdluzXzBh2EPO3NhAaZtGzkoFt0ias=; b=wHtSQ4yBed5bPFJL4JaWozfknx5AdUqzi45SAtwnAq9dBB6/VKTYB5PpLehyqyfglw Mf/BbltMy3RXrG1Zw+xT4zIOnTpOB03z63cDVESn8M2jJZ9H677DeSFrtoyxeALN+fLH V6pXRiWQxaOQv4Q8X/sjZ+T3KXtK2qqkvBctEEfCex9fAQ1SV9FwWFETSQBhlo1Wlktb qIEZgk9+4M8T3VDFdeWOvEWBYFHBbtecL1AeSwQGhmgNSskJfj0VZOvX7R4Y0wL489Qm XKiIUmUgJRB4qatH4OZ79aVSvFUs1QeC3BFJg9eQp9basdwvstYrpBYl85kSa9gdefWf TjOA== X-Gm-Message-State: AOAM533xrQ4lqhzUub5u8MoVNtxJpisccv0SCMyg0OCtsezK7VwIYuC7 wVeNsivk+e609UcwR1L1YGHUGH5x6GU= X-Google-Smtp-Source: ABdhPJxacA3tLPuYYhhgIpyp64NzbYmlYOno8GnheijYS0XTKfEUrahSrPuf55gpE0+xiN802GLyBQ== X-Received: by 2002:a17:906:8292:: with SMTP id h18mr4826243ejx.504.1642799039452; Fri, 21 Jan 2022 13:03:59 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.03.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:03:59 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 08/15] drivers: clk: qcom: gcc-ipq806x: add additional freq nss cores Date: Fri, 21 Jan 2022 22:03:33 +0100 Message-Id: <20220121210340.32362-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be clocked to 800MHz. Add these missing freq to the gcc driver. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index a4bf78fe8678..53a61860063d 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = { static struct pll_freq_tbl pll18_freq_tbl[] = { NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), + NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625), NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), + NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625), }; static struct clk_pll pll18 = { @@ -2702,7 +2704,9 @@ static const struct freq_tbl clk_tbl_nss[] = { { 110000000, P_PLL18, 1, 1, 5 }, { 275000000, P_PLL18, 2, 0, 0 }, { 550000000, P_PLL18, 1, 0, 0 }, + { 600000000, P_PLL18, 1, 0, 0 }, { 733000000, P_PLL18, 1, 0, 0 }, + { 800000000, P_PLL18, 1, 0, 0 }, { } }; From patchwork Fri Jan 21 21:03:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533875 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DE0AC433FE for ; Fri, 21 Jan 2022 21:04:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233309AbiAUVEq (ORCPT ); Fri, 21 Jan 2022 16:04:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233256AbiAUVEC (ORCPT ); Fri, 21 Jan 2022 16:04:02 -0500 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 300FFC061401; Fri, 21 Jan 2022 13:04:02 -0800 (PST) Received: by mail-ej1-x62d.google.com with SMTP id ka4so3334224ejc.11; Fri, 21 Jan 2022 13:04:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=clnqaNqyzpxcBB6mJhgn58xxBFPn79gkEl2JvXBz70c=; b=OOH9ocpXMafyNcmPxn8I1HcnS7JCORDOLvZKmoeiyMMJ92ELuW9RJr/+G77KhUy2F2 8NR47mvrMEQDVJknr+cpFQYk9Dn3tbBk/eCw1kTWKuQMG2DA7qV+XuCM9+qAUnc0+plJ SaUouILc8tyobC+ZirMmVW7r86M2jPCHAbhCCyc59HMZecE+Q+4N1Yf7ejcmaBoDnXLe Gl2d2u/F0PcooPCpLw1JWZzmyjPacfeJ4tQFCpiFGULgR2dmaQ5UlJ0wOTGW2/zStRYc 9G+vojpwU5oglIIwBD4fqruugrRQIAqT9G6qRzj2i0QJivR7OTjQh0MEFWKnbyctmvlw N7Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=clnqaNqyzpxcBB6mJhgn58xxBFPn79gkEl2JvXBz70c=; b=F7twbwDzU/0pfoEWnK0MwOuhh2W+pqs96+eLC5UmUc0o/zq6DqHtqiFx+hGRXzIchs 0PT86+zL8Jf9SpMjxqGtsmUneiQwsgYFcU1gUeV0Q8WdQFfjH9qGo3D4Q/Y6uhhltDnQ FRHBx7wgTVqNJ5BudzkvmCgnmIATDzi9cFesrlGYYsq+w5l+sh5ztBk3JQLLwPxy4vx7 XzdEAVJsRXaRhSpdhqqeVDDE98b2FlwIkEBG3YqtBwCpQJbHF8TYAXsIf++AYSDsBR9e 9n47fUZS6UwVPtsCzxr5RRfpEeNuKMBAl7WC40I3iYYMmD5Dvm92BWgZLHe1Rukrp/eQ jrDw== X-Gm-Message-State: AOAM530GiyzAqedRwjguRLfQCLtUxZS2YrzCKFCJSuISt3IWd490iHGc +Qoo93szqmONLuTkthQjDxk= X-Google-Smtp-Source: ABdhPJxh9JWMfnq6qGWgfnJ4mvaKe3SfbWHN60KbNA3Fqoy8b2Df3/WaoMX9PmUtMJlHkTa6t6u+cw== X-Received: by 2002:a17:906:4d18:: with SMTP id r24mr4596501eju.451.1642799040638; Fri, 21 Jan 2022 13:04:00 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.03.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:04:00 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 09/15] drivers: clk: qcom: gcc-ipq806x: add unusued flag for critical clock Date: Fri, 21 Jan 2022 22:03:34 +0100 Message-Id: <20220121210340.32362-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some clocks are used by other devices present on the SoC. For example the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to reject any regulator change command. These clock should never be disabled. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 53a61860063d..77bc3d94f580 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -798,7 +798,7 @@ static struct clk_rcg gsbi4_qup_src = { .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, }, }, }; @@ -816,7 +816,7 @@ static struct clk_branch gsbi4_qup_clk = { }, .num_parents = 1, .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }, }; @@ -900,7 +900,7 @@ static struct clk_rcg gsbi6_qup_src = { .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, }, }, }; @@ -969,7 +969,7 @@ static struct clk_branch gsbi7_qup_clk = { }, .num_parents = 1, .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }, }; @@ -1015,6 +1015,7 @@ static struct clk_branch gsbi4_h_clk = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_h_clk", .ops = &clk_branch_ops, + .flags = CLK_IGNORE_UNUSED, }, }, }; From patchwork Fri Jan 21 21:03:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 534298 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B619C433FE for ; Fri, 21 Jan 2022 21:04:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233358AbiAUVEH (ORCPT ); Fri, 21 Jan 2022 16:04:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233273AbiAUVED (ORCPT ); Fri, 21 Jan 2022 16:04:03 -0500 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DF56C061748; Fri, 21 Jan 2022 13:04:03 -0800 (PST) Received: by mail-ed1-x532.google.com with SMTP id r10so13787866edt.1; Fri, 21 Jan 2022 13:04:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=EXW/q6yX9wxCGxkY1EpqijRPyr0+7BNt2tp7DEwa3FY=; b=UdC/xozdghrR7wipNAqHVhJb4vbNlKh3k0bozRMY2NKauAeHPZ2VchII0bxl4C3PG4 SqRNW6NlDZ8S2xHQzrtI7VM3a9uCtIS/n4/z0uClXRVWdEYGUGA3RO0SCQwY+bTzGnMS jtUuXO2TyXJ5vU25YVpK7uhjS2ulCm2HwHAtwoSBczwjdwLFc4HqTbzVpjzGKoCJRR+m xeIZMsQNYtMn8GaSuE3Ckdn9yzlOuP+lqvrQpZDkB8zMKXbUZDpNyiOcy93Vrh/Q3nk3 HlKaMafd89yrAVJRJevLl27qJQswvXbcPgaN+XYYHHAUxHEFawTo58N7ogqhCzr6rSAS Bwog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EXW/q6yX9wxCGxkY1EpqijRPyr0+7BNt2tp7DEwa3FY=; b=tBZfP4FUY54OCbzVQ8tbTyJ9UXO41y2o2vCKPX/jodsXWsSxdvKeF2nO2xh+kNdBRz jCMVRdgiRSyAumwJcSssY7IZxZ+nT9FA3PKzMyh5UiHHEEwBly6aQR+DjtQ8caTbVVjO CTq0oSDkorsbJwoonL5fOMATWz81uQsnZz5fmYMOJu8iZWCtxg9MJ8u9Qm/P5Ah4Ti4T mqkCXgunHXjkTcmpPSwHe16eOauq1weu/bO17LDCCKvJbSi/d0u3ebKb8HYZvUfySAVJ TmqBO6f5A9CnFLhruM8nYSHOpDdybTWdoJZue6gUqBBr75Hx/fvJVDjD/D+Hg4SblvH8 74nw== X-Gm-Message-State: AOAM532Eei2iEA9sekMh2a8/or4R+K34GSxtJU0MQL8yEE6S2/HVfr9L c8ceB1Q8QuJBr7Ju/rkQ0QECxTuf5LI= X-Google-Smtp-Source: ABdhPJxNez6dTFFZyWzE66suCITTdZnjexrqF9hdoU+Do6PNAxQ3wcdYSoOV2Vpr645Kyz/kP6XXkA== X-Received: by 2002:a05:6402:50c6:: with SMTP id h6mr5922260edb.156.1642799041772; Fri, 21 Jan 2022 13:04:01 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.04.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:04:01 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 10/15] drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table Date: Fri, 21 Jan 2022 22:03:35 +0100 Message-Id: <20220121210340.32362-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add additional freq supported for the sdc table. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 77bc3d94f580..dbd61e4844b0 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc[] = { { 20210000, P_PLL8, 1, 1, 19 }, { 24000000, P_PLL8, 4, 1, 4 }, { 48000000, P_PLL8, 4, 1, 2 }, + { 52000000, P_PLL8, 1, 2, 15 }, /* 51.2 Mhz */ { 64000000, P_PLL8, 3, 1, 2 }, { 96000000, P_PLL8, 4, 0, 0 }, { 192000000, P_PLL8, 2, 0, 0 }, From patchwork Fri Jan 21 21:03:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 534297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BA2FC4167B for ; Fri, 21 Jan 2022 21:04:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233392AbiAUVEJ (ORCPT ); Fri, 21 Jan 2022 16:04:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233126AbiAUVEF (ORCPT ); Fri, 21 Jan 2022 16:04:05 -0500 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8102DC061755; Fri, 21 Jan 2022 13:04:04 -0800 (PST) Received: by mail-ed1-x533.google.com with SMTP id n10so29198049edv.2; Fri, 21 Jan 2022 13:04:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CXVZRlEKPP4hcCweUpH3JuNpFEE+gl2M3UXNpQ3IHj0=; b=mcQt3QQuz8soITCTpwVuo8Dx4/K7umNypJgMjwKSj55Z1PfHWVAfu4UWskKCcT3EWd rldbdvu16iGSPYv96Xy0/Xx274rd/Z0uNl4KjDZMowC+eXo35KmnfutLZ/mgSH+VYJAw aZ/eB6uNiS7qKBnbLAmm1z4AAg6J7buGFhuyEnvsUMmvtlMSC/lug248DXrLHR5Bt4r4 4/R+8/ESqqZQchJNnKMHAOAjn8EMH95abNyboWko2rzIzRFuiAzmhakjD5RzYo3hxXAK WfTQwW113L4JoVO1bt49gBPnXLVZGzt0Cp1Y+oJL4UNyz+pMRZFECUi5od47qp4mGee6 q67g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CXVZRlEKPP4hcCweUpH3JuNpFEE+gl2M3UXNpQ3IHj0=; b=hGlhUWPC4OW0wzTkZPXmBqrvDOdyks0aFnK3IEUeq7qaIJfePW29Tv45WGveTei1Qg 5pPHvhqUOIj7HjamHO2qTbcW9FABRWqro/5YkuX53x9uHRJjMzqRPHzbC62P+P6O3ekg 3fcQOrNnt3x/fiV2q4u/eh4bFK4OFYcxYorKTvDdTDCefoAIB9EudP7kEcpmOo4EWndX DSy4GcMaLyyFrgF2kUeEvVzjYZU1Yw0oAO3zRuBPU2xf1N63VoNncKQAAdyt8lM8E4pl d3EsOiJQKTEdvjTkOd0q09xP448dpnOb4RhcJg6EBwGrTHglysohn8sh2c5uCT4aeyXd C2YQ== X-Gm-Message-State: AOAM530r5uNvbdWL4c766dqp968JZDhXYUHHD/WDH/PtOTapfDZloyhz fMXti8rIcbTpFCSTbttQI4c= X-Google-Smtp-Source: ABdhPJxFu9Aw6F9p69w0CcpdMnivsQPmOxAwDuYEJ9Yv+/EwnUbTiGFkSEfMT7UpCgHA+MdsIcbSvA== X-Received: by 2002:a05:6402:5107:: with SMTP id m7mr5715878edd.292.1642799042879; Fri, 21 Jan 2022 13:04:02 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.04.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:04:02 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 11/15] dt-bindings: clock: add ipq8064 ce5 clk define Date: Fri, 21 Jan 2022 22:03:36 +0100 Message-Id: <20220121210340.32362-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver. Signed-off-by: Ansuel Smith --- include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h index 7deec14a6dee..02262d2ac899 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h @@ -240,7 +240,7 @@ #define PLL14 232 #define PLL14_VOTE 233 #define PLL18 234 -#define CE5_SRC 235 +#define CE5_A_CLK 235 #define CE5_H_CLK 236 #define CE5_CORE_CLK 237 #define CE3_SLEEP_CLK 238 @@ -283,5 +283,8 @@ #define EBI2_AON_CLK 281 #define NSSTCM_CLK_SRC 282 #define NSSTCM_CLK 283 +#define CE5_A_CLK_SRC 285 +#define CE5_H_CLK_SRC 286 +#define CE5_CORE_CLK_SRC 287 #endif From patchwork Fri Jan 21 21:03:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 534295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8EB3C433F5 for ; Fri, 21 Jan 2022 21:04:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233316AbiAUVEp (ORCPT ); Fri, 21 Jan 2022 16:04:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233315AbiAUVEG (ORCPT ); Fri, 21 Jan 2022 16:04:06 -0500 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99C30C06173B; Fri, 21 Jan 2022 13:04:05 -0800 (PST) Received: by mail-ej1-x632.google.com with SMTP id j2so3315671ejk.6; Fri, 21 Jan 2022 13:04:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vaOb6lzR+ohDnwzAKg4t+EygQuxBAzQ4LziIApjliUg=; b=iwMy/bvTpkMwewugrerKyOEO3KydgN75A7zThNxfNUZSkukoizcNQScynIEINLb6ZQ fzjM1FZql4ZKwW+whmzdQYbXKYv5gT9GCUEpw0kpy5KA+w8LQWKB5gBaaVn2ipdfBREx MgDiKSUzV2IgPILR5EVp+8oeYnvGkAdTw3SoRZ+mNdtP3lpy7kjMUGwHx9nWZG9Q8hLw kcfPi6g2SMA5P7Zd3HEziwFL8f+3Bg6WkoTlvwXrgvHGXi4/GR+KnK7EmOMrd6L4HtoE YFsi1UH1+ClEYWASnDG2rqEGw4IKQkE3xKRFdgU7ag3wYpBovJtrlbDFF7NernlNVQo5 eePw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vaOb6lzR+ohDnwzAKg4t+EygQuxBAzQ4LziIApjliUg=; b=nFWgR+j0CGdK8hnfA90QKjsdqhyYU9JBqeUjKG38G/Qx+tPIUps5fSz07D219toJ27 EWCvpbudGZzy+2F08rzlj/9u055YMqClJ3oDxgIR6IXAlRCJ4VIzaDVUKxUCTIA9U+H7 htZQGA1Cat9N4uaXAABCD6SdiZo+S6B5+8MXmFUXj493kXNIowxKMhADBCxBWdeASk3j t1q18RZ2UpMxfdkpdZPUi51DcJbDSet/t9lnVvb1Wi4mPqhVsoIlFRsnvvts7qAHuaBA NrWndC5YVEMurMyHhBgQyQGVEJGG/rlExIE99GmX/kjyLbTNz294ty7N6Hf9ugxlGwi6 VIXg== X-Gm-Message-State: AOAM531479LQFD8x1YGx0KvH5ZUSYnO47CwZ0B79/2ixSC6xuffcgGk2 YH2b9pUBPQR1lRuUd8nIat4= X-Google-Smtp-Source: ABdhPJzvPXcJMXAZk8tvx8Q6lU8Aka+RDfQIAUpNWzpccNHVGgoGEx9vvyDKN5vw7w4t4JxbukWPyg== X-Received: by 2002:a17:907:d24:: with SMTP id gn36mr4645255ejc.324.1642799044024; Fri, 21 Jan 2022 13:04:04 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.04.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:04:03 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 12/15] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine clocks Date: Fri, 21 Jan 2022 22:03:37 +0100 Message-Id: <20220121210340.32362-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing CryptoEngine clocks and pll11 required clock. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++ 1 file changed, 244 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index dbd61e4844b0..a86d1504a149 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -256,6 +256,24 @@ static struct clk_pll pll18 = { }, }; +static struct clk_pll pll11 = { + .l_reg = 0x3184, + .m_reg = 0x3188, + .n_reg = 0x318c, + .config_reg = 0x3194, + .mode_reg = 0x3180, + .status_reg = 0x3198, + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll11", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + enum { P_PXO, P_PLL8, @@ -264,6 +282,7 @@ enum { P_CXO, P_PLL14, P_PLL18, + P_PLL11, }; static const struct parent_map gcc_pxo_pll8_map[] = { @@ -331,6 +350,44 @@ static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { { .hw = &pll18.clkr.hw }, }; +static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = { + { P_PXO, 0 }, + { P_PLL8, 4 }, + { P_PLL0, 2 }, + { P_PLL14, 5 }, + { P_PLL18, 1 }, + { P_PLL11, 3 }, +}; + +static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, + { .hw = &pll11.clkr.hw }, + +}; + +static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = { + { P_PXO, 0 }, + { P_PLL3, 6 }, + { P_PLL0, 2 }, + { P_PLL14, 5 }, + { P_PLL18, 1 }, + { P_PLL11, 3 }, +}; + +static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = { + { .fw_name = "pxo" }, + { .hw = &pll3.clkr.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, + { .hw = &pll11.clkr.hw }, + +}; + static struct freq_tbl clk_tbl_gsbi_uart[] = { { 1843200, P_PLL8, 2, 6, 625 }, { 3686400, P_PLL8, 2, 12, 625 }, @@ -2818,6 +2875,186 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { }, }; +static const struct freq_tbl clk_tbl_ce5_core[] = { + { 150000000, P_PLL3, 8, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_core_src = { + .ns_reg[0] = 0x36C4, + .ns_reg[1] = 0x36C8, + .bank_reg = 0x36C0, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_core, + .clkr = { + .enable_reg = 0x36C0, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_core_src", + .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_core_clk = { + .halt_reg = 0x2FDC, + .halt_bit = 5, + .hwcg_reg = 0x36CC, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x36CC, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_core_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_core_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl clk_tbl_ce5_a_clk[] = { + { 160000000, P_PLL0, 5, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_a_clk_src = { + .ns_reg[0] = 0x3d84, + .ns_reg[1] = 0x3d88, + .bank_reg = 0x3d80, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_a_clk, + .clkr = { + .enable_reg = 0x3d80, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_a_clk_src", + .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_a_clk = { + .halt_reg = 0x3c20, + .halt_bit = 12, + .hwcg_reg = 0x3d8c, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x3d8c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_a_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_a_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl clk_tbl_ce5_h_clk[] = { + { 160000000, P_PLL0, 5, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_h_clk_src = { + .ns_reg[0] = 0x3c64, + .ns_reg[1] = 0x3c68, + .bank_reg = 0x3c60, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_h_clk, + .clkr = { + .enable_reg = 0x3c60, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_h_clk_src", + .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_h_clk = { + .halt_reg = 0x3c20, + .halt_bit = 11, + .hwcg_reg = 0x3c6c, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x3c6c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_h_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_h_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, @@ -2825,6 +3062,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL4_VOTE] = &pll4_vote, [PLL8] = &pll8.clkr, [PLL8_VOTE] = &pll8_vote, + [PLL11] = &pll11.clkr, [PLL14] = &pll14.clkr, [PLL14_VOTE] = &pll14_vote, [PLL18] = &pll18.clkr, @@ -2939,6 +3177,12 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL9] = &hfpll0.clkr, [PLL10] = &hfpll1.clkr, [PLL12] = &hfpll_l2.clkr, + [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr, + [CE5_A_CLK] = &ce5_a_clk.clkr, + [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr, + [CE5_H_CLK] = &ce5_h_clk.clkr, + [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr, + [CE5_CORE_CLK] = &ce5_core_clk.clkr, }; static const struct qcom_reset_map gcc_ipq806x_resets[] = { From patchwork Fri Jan 21 21:03:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533876 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 113F0C433F5 for ; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.04.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:04:04 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 13/15] dt-bindings: reset: add ipq8064 ce5 resets Date: Fri, 21 Jan 2022 22:03:38 +0100 Message-Id: <20220121210340.32362-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add ipq8064 ce5 resets needed for CryptoEngine gcc driver. Signed-off-by: Ansuel Smith --- include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h index 26b6f9200620..020c9cf18751 100644 --- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h +++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h @@ -163,5 +163,10 @@ #define NSS_CAL_PRBS_RST_N_RESET 154 #define NSS_LCKDT_RST_N_RESET 155 #define NSS_SRDS_N_RESET 156 +#define CRYPTO_ENG1_RESET 157 +#define CRYPTO_ENG2_RESET 158 +#define CRYPTO_ENG3_RESET 159 +#define CRYPTO_ENG4_RESET 160 +#define CRYPTO_AHB_RESET 161 #endif From patchwork Fri Jan 21 21:03:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 534296 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 306BCC43219 for ; Fri, 21 Jan 2022 21:04:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233567AbiAUVET (ORCPT ); Fri, 21 Jan 2022 16:04:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233248AbiAUVEI (ORCPT ); Fri, 21 Jan 2022 16:04:08 -0500 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9E68C061753; Fri, 21 Jan 2022 13:04:07 -0800 (PST) Received: by mail-ej1-x632.google.com with SMTP id k25so3317696ejp.5; Fri, 21 Jan 2022 13:04:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ETUvc/o8aObyUn/852ohaMGKgdelmVW4X0FnpFAGyTY=; b=U8dWSor/0YyFBqGMqi9a6UpicY5NAJY62a+F1s+KYcg8fNSiuXtmhxzEObqfUDF0dv DCRszTQSnPn/NZHbv7dj+wN07M0U7+WyApMv6fjNs80/02v8ryXWQ1XdAghU6JbMgHXo kRtENAxBoy4xG0+1AA2+Cn8ldvgu8eCaV7vFV8EjckLfBeWlW0krIy5yeoUHpcH+yu9c vZxAuWHH8JeR6xXEbVAO8Y3uoHal7kVblMFF27cESd9xulopSHBVazTpxYpL8vF5OvzS eFB21nwt0yB70BdGKiXcYUoUYUFne7rYojW9oDAuOgtoBq+Y+bIkSFIVsAEqs1f39Gg4 UBVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ETUvc/o8aObyUn/852ohaMGKgdelmVW4X0FnpFAGyTY=; b=jKDZG5IfJNtZZcKxX39kfdbhC0XCra/DxCjpWVrF9O3H2rpTDKR2A5gvvZxZXcEXoX K2CsYdW/odUx+6rNwJB1I+ndRv+58VSDbra0g3k++hm0BTDtTofGGBNhgaW755ttsmQ/ tBta4zR1r1KrXZJ7Xle4heZ6wA0C/sL81hgMACrhDuVmY8wB23qELHqyxetbyQQXqmEJ ni2+oSWgCYJhC3E9K5EkJzJc61ehwZLBHZya1Md2E8uyR2ePP3yv5D8Mpvt/9FzAtqeq I1BYpkUX+fbs+4T03WXIoU7NBnCWbzQSIFKDZxAxSy4Y2p9pzvFnxr8bCYlAhCZT4JDF GVUA== X-Gm-Message-State: AOAM531RFFyB10lMN78RhA8sMq7T6l9F5mEdKjsQqWisGdDuNz2aJO47 HlHeVnmQLUEvISmNSWUyggc= X-Google-Smtp-Source: ABdhPJzn/KRg26oikuPegx58DPOkjFlNQ/1WvK13ekvmie0j1EjoXI/VIE2cIIJ8eYBkRt7J1ECQ4g== X-Received: by 2002:a17:907:3e07:: with SMTP id hp7mr4585504ejc.469.1642799046269; Fri, 21 Jan 2022 13:04:06 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.04.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:04:05 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 14/15] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine resets Date: Fri, 21 Jan 2022 22:03:39 +0100 Message-Id: <20220121210340.32362-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing CryptoEngine resets. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index a86d1504a149..8f025cef2ec3 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -3314,6 +3314,11 @@ static const struct qcom_reset_map gcc_ipq806x_resets[] = { [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, [GMAC_AHB_RESET] = { 0x3e24, 0 }, + [CRYPTO_ENG1_RESET] = { 0x3e00, 0}, + [CRYPTO_ENG2_RESET] = { 0x3e04, 0}, + [CRYPTO_ENG3_RESET] = { 0x3e08, 0}, + [CRYPTO_ENG4_RESET] = { 0x3e0c, 0}, + [CRYPTO_AHB_RESET] = { 0x3e10, 0}, [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, From patchwork Fri Jan 21 21:03:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533877 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 150EAC4332F for ; Fri, 21 Jan 2022 21:04:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233433AbiAUVER (ORCPT ); Fri, 21 Jan 2022 16:04:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233437AbiAUVEK (ORCPT ); Fri, 21 Jan 2022 16:04:10 -0500 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E523CC06175A; Fri, 21 Jan 2022 13:04:08 -0800 (PST) Received: by mail-ed1-x52e.google.com with SMTP id l5so27759882edv.3; Fri, 21 Jan 2022 13:04:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=70y9nP+1TJuyoQVHWKHYrgk62/1kbAozVgHhQoGQnWU=; b=ifaBPUIYWqx0Yuxwid+52Kneq6qIIEZpQyCGPZBb+SdwutjTuyrN/oWw8oiyCbLJ/4 JWNQWjVEd/tMRmtzrg1+Vp0Y9SEKG8h6m6ue3U3cXDOxv42tsqAet4qqt0HcFhztaDtG j/6fGOWsEhoqiqLUrXk5rc1rKrfSi5gXBWqnaDtx7Ae73aH8qX9boL2yfxLD2gbGYFKw HVgGDv5RL8q05bcDRzhiDltJvNTL8QXvqp5d0pwmqVKp0yTbSz7mLQ8He1qYyxSX/iGA slqJ8p3O+RiqiRI7evjb7n3SbBCv1C4cPjyyLnQ+ZT5wZvr+5PwaC6CestOwpIYs2Zph U2lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=70y9nP+1TJuyoQVHWKHYrgk62/1kbAozVgHhQoGQnWU=; b=vJ4oNSnSmEcrKpBxiENzCONaJ0O8+g2FEaiNXtA4/bf7oIF3Kwmj3oP5Vdw71/KVWI QDcotawdN6YqOQP64SIyiy6ccCGbJOVf0NGDsD6BUR7BLgYtrVzxINjjs2j5Er5ocSyd 108VyzmVblq7j8CH0y74GuhlztwYbZp3s0VFTMKivC0NZ44xLt9NxqA+r46jHWzo8CY7 RXCV6gm+sGDlAQ2no1cP0luU6SortxyURW4Mn9AVkHHCkqYBMwq4UY6kqUC4kwtKzZum MRoNmIVxlpvBIeaN9QtLBAcXokpITpzH58y7DNZQPX+TbWeD1xOl9Wt9G7EkscEOCMO4 EMPA== X-Gm-Message-State: AOAM533smrrKmyHpyiiemTo+70EsGAirSRrVMkv1X9HbBWxhRn8bskej 4Jkj853Tqs5LyI8T3/Q0xt0= X-Google-Smtp-Source: ABdhPJy1y4HO8/1WaxNmwSExaeBcf58GI14B5KbdtJCqWCaEiOtb20D7eSoT8DXN+D/CEEd8o4jPGQ== X-Received: by 2002:a05:6402:b4c:: with SMTP id bx12mr5776585edb.363.1642799047385; Fri, 21 Jan 2022 13:04:07 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id p23sm2898595edx.86.2022.01.21.13.04.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 13:04:06 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 15/15] ARM: dts: qcom: Add syscon and cxo/pxo clock to gcc node for ipq8064 Date: Fri, 21 Jan 2022 22:03:40 +0100 Message-Id: <20220121210340.32362-16-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220121210340.32362-1-ansuelsmth@gmail.com> References: <20220121210340.32362-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add syscon compatible required for tsens driver to correctly probe driver and access the reg. Also add cxo and pxo tag and declare them as gcc clock now requires them for the ipq8064 gcc driver that has now been modernized. Signed-off-by: Ansuel Smith --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 11481313bdb6..5524a68cf3d1 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -298,13 +298,13 @@ smem: smem@41000000 { }; clocks { - cxo_board { + cxo_board: cxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; @@ -736,7 +736,9 @@ tsens_calib_backup: calib_backup@410 { }; gcc: clock-controller@900000 { - compatible = "qcom,gcc-ipq8064"; + compatible = "qcom,gcc-ipq8064", "syscon"; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>;